logicpd-torpedo-som.dtsi 4.8 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License version 2 as
  4. * published by the Free Software Foundation.
  5. */
  6. #include <dt-bindings/input/input.h>
  7. / {
  8. chosen {
  9. stdout-path = &uart1;
  10. };
  11. cpus {
  12. cpu@0 {
  13. cpu0-supply = <&vcc>;
  14. };
  15. };
  16. memory@80000000 {
  17. device_type = "memory";
  18. reg = <0x80000000 0>;
  19. };
  20. leds {
  21. compatible = "gpio-leds";
  22. user0 {
  23. label = "user0";
  24. gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
  25. linux,default-trigger = "none";
  26. };
  27. };
  28. };
  29. &gpmc {
  30. ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
  31. nand@0,0 {
  32. compatible = "ti,omap2-nand";
  33. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  34. interrupt-parent = <&gpmc>;
  35. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  36. <1 IRQ_TYPE_NONE>; /* termcount */
  37. linux,mtd-name = "micron,mt29f4g16abbda3w";
  38. nand-bus-width = <16>;
  39. ti,nand-ecc-opt = "bch8";
  40. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  41. gpmc,sync-clk-ps = <0>;
  42. gpmc,cs-on-ns = <0>;
  43. gpmc,cs-rd-off-ns = <44>;
  44. gpmc,cs-wr-off-ns = <44>;
  45. gpmc,adv-on-ns = <6>;
  46. gpmc,adv-rd-off-ns = <34>;
  47. gpmc,adv-wr-off-ns = <44>;
  48. gpmc,we-off-ns = <40>;
  49. gpmc,oe-off-ns = <54>;
  50. gpmc,access-ns = <64>;
  51. gpmc,rd-cycle-ns = <82>;
  52. gpmc,wr-cycle-ns = <82>;
  53. gpmc,wr-access-ns = <40>;
  54. gpmc,wr-data-mux-bus-ns = <0>;
  55. gpmc,device-width = <2>;
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. };
  59. };
  60. &i2c1 {
  61. pinctrl-names = "default";
  62. pinctrl-0 = <&i2c1_pins>;
  63. clock-frequency = <2600000>;
  64. twl: twl@48 {
  65. reg = <0x48>;
  66. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  67. interrupt-parent = <&intc>;
  68. twl_audio: audio {
  69. compatible = "ti,twl4030-audio";
  70. codec {
  71. };
  72. };
  73. };
  74. };
  75. &i2c2 {
  76. clock-frequency = <400000>;
  77. };
  78. &i2c3 {
  79. clock-frequency = <400000>;
  80. at24@50 {
  81. compatible = "atmel,24c64";
  82. readonly;
  83. reg = <0x50>;
  84. };
  85. };
  86. &omap3_pmx_core {
  87. mcbsp2_pins: pinmux_mcbsp2_pins {
  88. pinctrl-single,pins = <
  89. OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
  90. OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
  91. OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
  92. OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
  93. >;
  94. };
  95. uart2_pins: pinmux_uart2_pins {
  96. pinctrl-single,pins = <
  97. OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
  98. OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
  99. OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
  100. OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
  101. OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
  102. >;
  103. };
  104. mcspi1_pins: pinmux_mcspi1_pins {
  105. pinctrl-single,pins = <
  106. OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
  107. OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
  108. OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
  109. OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
  110. >;
  111. };
  112. hsusb_otg_pins: pinmux_hsusb_otg_pins {
  113. pinctrl-single,pins = <
  114. OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
  115. OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
  116. OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
  117. OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
  118. OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
  119. OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
  120. OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
  121. OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
  122. OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
  123. OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
  124. OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
  125. OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
  126. >;
  127. };
  128. i2c1_pins: pinmux_i2c1_pins {
  129. pinctrl-single,pins = <
  130. OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
  131. OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
  132. >;
  133. };
  134. };
  135. &uart2 {
  136. interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&uart2_pins>;
  139. };
  140. &mcspi1 {
  141. pinctrl-names = "default";
  142. pinctrl-0 = <&mcspi1_pins>;
  143. };
  144. #include "twl4030.dtsi"
  145. #include "twl4030_omap3.dtsi"
  146. &twl {
  147. twl_power: power {
  148. compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
  149. ti,use_poweroff;
  150. };
  151. };
  152. &twl_gpio {
  153. ti,use-leds;
  154. };