rtc-ds1307.c 32 KB

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  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/bcd.h>
  14. #include <linux/i2c.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/rtc/ds1307.h>
  18. #include <linux/rtc.h>
  19. #include <linux/slab.h>
  20. #include <linux/string.h>
  21. /*
  22. * We can't determine type by probing, but if we expect pre-Linux code
  23. * to have set the chip up as a clock (turning on the oscillator and
  24. * setting the date and time), Linux can ignore the non-clock features.
  25. * That's a natural job for a factory or repair bench.
  26. */
  27. enum ds_type {
  28. ds_1307,
  29. ds_1337,
  30. ds_1338,
  31. ds_1339,
  32. ds_1340,
  33. ds_1388,
  34. ds_3231,
  35. m41t00,
  36. mcp794xx,
  37. rx_8025,
  38. last_ds_type /* always last */
  39. /* rs5c372 too? different address... */
  40. };
  41. /* RTC registers don't differ much, except for the century flag */
  42. #define DS1307_REG_SECS 0x00 /* 00-59 */
  43. # define DS1307_BIT_CH 0x80
  44. # define DS1340_BIT_nEOSC 0x80
  45. # define MCP794XX_BIT_ST 0x80
  46. #define DS1307_REG_MIN 0x01 /* 00-59 */
  47. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  48. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  49. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  50. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  51. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  52. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  53. # define MCP794XX_BIT_VBATEN 0x08
  54. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  55. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  56. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  57. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  58. /*
  59. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  60. * start at 7, and they differ a LOT. Only control and status matter for
  61. * basic RTC date and time functionality; be careful using them.
  62. */
  63. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  64. # define DS1307_BIT_OUT 0x80
  65. # define DS1338_BIT_OSF 0x20
  66. # define DS1307_BIT_SQWE 0x10
  67. # define DS1307_BIT_RS1 0x02
  68. # define DS1307_BIT_RS0 0x01
  69. #define DS1337_REG_CONTROL 0x0e
  70. # define DS1337_BIT_nEOSC 0x80
  71. # define DS1339_BIT_BBSQI 0x20
  72. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  73. # define DS1337_BIT_RS2 0x10
  74. # define DS1337_BIT_RS1 0x08
  75. # define DS1337_BIT_INTCN 0x04
  76. # define DS1337_BIT_A2IE 0x02
  77. # define DS1337_BIT_A1IE 0x01
  78. #define DS1340_REG_CONTROL 0x07
  79. # define DS1340_BIT_OUT 0x80
  80. # define DS1340_BIT_FT 0x40
  81. # define DS1340_BIT_CALIB_SIGN 0x20
  82. # define DS1340_M_CALIBRATION 0x1f
  83. #define DS1340_REG_FLAG 0x09
  84. # define DS1340_BIT_OSF 0x80
  85. #define DS1337_REG_STATUS 0x0f
  86. # define DS1337_BIT_OSF 0x80
  87. # define DS1337_BIT_A2I 0x02
  88. # define DS1337_BIT_A1I 0x01
  89. #define DS1339_REG_ALARM1_SECS 0x07
  90. #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
  91. #define RX8025_REG_CTRL1 0x0e
  92. # define RX8025_BIT_2412 0x20
  93. #define RX8025_REG_CTRL2 0x0f
  94. # define RX8025_BIT_PON 0x10
  95. # define RX8025_BIT_VDET 0x40
  96. # define RX8025_BIT_XST 0x20
  97. struct ds1307 {
  98. u8 offset; /* register's offset */
  99. u8 regs[11];
  100. u16 nvram_offset;
  101. struct bin_attribute *nvram;
  102. enum ds_type type;
  103. unsigned long flags;
  104. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  105. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  106. struct i2c_client *client;
  107. struct rtc_device *rtc;
  108. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  109. u8 length, u8 *values);
  110. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  111. u8 length, const u8 *values);
  112. };
  113. struct chip_desc {
  114. unsigned alarm:1;
  115. u16 nvram_offset;
  116. u16 nvram_size;
  117. u16 trickle_charger_reg;
  118. u8 trickle_charger_setup;
  119. u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool);
  120. };
  121. static u8 do_trickle_setup_ds1339(struct i2c_client *,
  122. uint32_t ohms, bool diode);
  123. static struct chip_desc chips[last_ds_type] = {
  124. [ds_1307] = {
  125. .nvram_offset = 8,
  126. .nvram_size = 56,
  127. },
  128. [ds_1337] = {
  129. .alarm = 1,
  130. },
  131. [ds_1338] = {
  132. .nvram_offset = 8,
  133. .nvram_size = 56,
  134. },
  135. [ds_1339] = {
  136. .alarm = 1,
  137. .trickle_charger_reg = 0x10,
  138. .do_trickle_setup = &do_trickle_setup_ds1339,
  139. },
  140. [ds_1340] = {
  141. .trickle_charger_reg = 0x08,
  142. },
  143. [ds_1388] = {
  144. .trickle_charger_reg = 0x0a,
  145. },
  146. [ds_3231] = {
  147. .alarm = 1,
  148. },
  149. [mcp794xx] = {
  150. .alarm = 1,
  151. /* this is battery backed SRAM */
  152. .nvram_offset = 0x20,
  153. .nvram_size = 0x40,
  154. },
  155. };
  156. static const struct i2c_device_id ds1307_id[] = {
  157. { "ds1307", ds_1307 },
  158. { "ds1337", ds_1337 },
  159. { "ds1338", ds_1338 },
  160. { "ds1339", ds_1339 },
  161. { "ds1388", ds_1388 },
  162. { "ds1340", ds_1340 },
  163. { "ds3231", ds_3231 },
  164. { "m41t00", m41t00 },
  165. { "mcp7940x", mcp794xx },
  166. { "mcp7941x", mcp794xx },
  167. { "pt7c4338", ds_1307 },
  168. { "rx8025", rx_8025 },
  169. { }
  170. };
  171. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  172. /*----------------------------------------------------------------------*/
  173. #define BLOCK_DATA_MAX_TRIES 10
  174. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  175. u8 command, u8 length, u8 *values)
  176. {
  177. s32 i, data;
  178. for (i = 0; i < length; i++) {
  179. data = i2c_smbus_read_byte_data(client, command + i);
  180. if (data < 0)
  181. return data;
  182. values[i] = data;
  183. }
  184. return i;
  185. }
  186. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  187. u8 length, u8 *values)
  188. {
  189. u8 oldvalues[255];
  190. s32 ret;
  191. int tries = 0;
  192. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  193. ret = ds1307_read_block_data_once(client, command, length, values);
  194. if (ret < 0)
  195. return ret;
  196. do {
  197. if (++tries > BLOCK_DATA_MAX_TRIES) {
  198. dev_err(&client->dev,
  199. "ds1307_read_block_data failed\n");
  200. return -EIO;
  201. }
  202. memcpy(oldvalues, values, length);
  203. ret = ds1307_read_block_data_once(client, command, length,
  204. values);
  205. if (ret < 0)
  206. return ret;
  207. } while (memcmp(oldvalues, values, length));
  208. return length;
  209. }
  210. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  211. u8 length, const u8 *values)
  212. {
  213. u8 currvalues[255];
  214. int tries = 0;
  215. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  216. do {
  217. s32 i, ret;
  218. if (++tries > BLOCK_DATA_MAX_TRIES) {
  219. dev_err(&client->dev,
  220. "ds1307_write_block_data failed\n");
  221. return -EIO;
  222. }
  223. for (i = 0; i < length; i++) {
  224. ret = i2c_smbus_write_byte_data(client, command + i,
  225. values[i]);
  226. if (ret < 0)
  227. return ret;
  228. }
  229. ret = ds1307_read_block_data_once(client, command, length,
  230. currvalues);
  231. if (ret < 0)
  232. return ret;
  233. } while (memcmp(currvalues, values, length));
  234. return length;
  235. }
  236. /*----------------------------------------------------------------------*/
  237. /* These RTC devices are not designed to be connected to a SMbus adapter.
  238. SMbus limits block operations length to 32 bytes, whereas it's not
  239. limited on I2C buses. As a result, accesses may exceed 32 bytes;
  240. in that case, split them into smaller blocks */
  241. static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
  242. u8 command, u8 length, const u8 *values)
  243. {
  244. u8 suboffset = 0;
  245. if (length <= I2C_SMBUS_BLOCK_MAX)
  246. return i2c_smbus_write_i2c_block_data(client,
  247. command, length, values);
  248. while (suboffset < length) {
  249. s32 retval = i2c_smbus_write_i2c_block_data(client,
  250. command + suboffset,
  251. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  252. values + suboffset);
  253. if (retval < 0)
  254. return retval;
  255. suboffset += I2C_SMBUS_BLOCK_MAX;
  256. }
  257. return length;
  258. }
  259. static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
  260. u8 command, u8 length, u8 *values)
  261. {
  262. u8 suboffset = 0;
  263. if (length <= I2C_SMBUS_BLOCK_MAX)
  264. return i2c_smbus_read_i2c_block_data(client,
  265. command, length, values);
  266. while (suboffset < length) {
  267. s32 retval = i2c_smbus_read_i2c_block_data(client,
  268. command + suboffset,
  269. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  270. values + suboffset);
  271. if (retval < 0)
  272. return retval;
  273. suboffset += I2C_SMBUS_BLOCK_MAX;
  274. }
  275. return length;
  276. }
  277. /*----------------------------------------------------------------------*/
  278. /*
  279. * The ds1337 and ds1339 both have two alarms, but we only use the first
  280. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  281. * signal; ds1339 chips have only one alarm signal.
  282. */
  283. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  284. {
  285. struct i2c_client *client = dev_id;
  286. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  287. struct mutex *lock = &ds1307->rtc->ops_lock;
  288. int stat, control;
  289. mutex_lock(lock);
  290. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  291. if (stat < 0)
  292. goto out;
  293. if (stat & DS1337_BIT_A1I) {
  294. stat &= ~DS1337_BIT_A1I;
  295. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  296. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  297. if (control < 0)
  298. goto out;
  299. control &= ~DS1337_BIT_A1IE;
  300. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  301. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  302. }
  303. out:
  304. mutex_unlock(lock);
  305. return IRQ_HANDLED;
  306. }
  307. /*----------------------------------------------------------------------*/
  308. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  309. {
  310. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  311. int tmp;
  312. /* read the RTC date and time registers all at once */
  313. tmp = ds1307->read_block_data(ds1307->client,
  314. ds1307->offset, 7, ds1307->regs);
  315. if (tmp != 7) {
  316. dev_err(dev, "%s error %d\n", "read", tmp);
  317. return -EIO;
  318. }
  319. dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
  320. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  321. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  322. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  323. t->tm_hour = bcd2bin(tmp);
  324. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  325. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  326. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  327. t->tm_mon = bcd2bin(tmp) - 1;
  328. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  329. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  330. dev_dbg(dev, "%s secs=%d, mins=%d, "
  331. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  332. "read", t->tm_sec, t->tm_min,
  333. t->tm_hour, t->tm_mday,
  334. t->tm_mon, t->tm_year, t->tm_wday);
  335. /* initial clock setting can be undefined */
  336. return rtc_valid_tm(t);
  337. }
  338. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  339. {
  340. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  341. int result;
  342. int tmp;
  343. u8 *buf = ds1307->regs;
  344. dev_dbg(dev, "%s secs=%d, mins=%d, "
  345. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  346. "write", t->tm_sec, t->tm_min,
  347. t->tm_hour, t->tm_mday,
  348. t->tm_mon, t->tm_year, t->tm_wday);
  349. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  350. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  351. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  352. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  353. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  354. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  355. /* assume 20YY not 19YY */
  356. tmp = t->tm_year - 100;
  357. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  358. switch (ds1307->type) {
  359. case ds_1337:
  360. case ds_1339:
  361. case ds_3231:
  362. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  363. break;
  364. case ds_1340:
  365. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  366. | DS1340_BIT_CENTURY;
  367. break;
  368. case mcp794xx:
  369. /*
  370. * these bits were cleared when preparing the date/time
  371. * values and need to be set again before writing the
  372. * buffer out to the device.
  373. */
  374. buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
  375. buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
  376. break;
  377. default:
  378. break;
  379. }
  380. dev_dbg(dev, "%s: %7ph\n", "write", buf);
  381. result = ds1307->write_block_data(ds1307->client,
  382. ds1307->offset, 7, buf);
  383. if (result < 0) {
  384. dev_err(dev, "%s error %d\n", "write", result);
  385. return result;
  386. }
  387. return 0;
  388. }
  389. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  390. {
  391. struct i2c_client *client = to_i2c_client(dev);
  392. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  393. int ret;
  394. if (!test_bit(HAS_ALARM, &ds1307->flags))
  395. return -EINVAL;
  396. /* read all ALARM1, ALARM2, and status registers at once */
  397. ret = ds1307->read_block_data(client,
  398. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  399. if (ret != 9) {
  400. dev_err(dev, "%s error %d\n", "alarm read", ret);
  401. return -EIO;
  402. }
  403. dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
  404. &ds1307->regs[0], &ds1307->regs[4], &ds1307->regs[7]);
  405. /*
  406. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  407. * and that all four fields are checked matches
  408. */
  409. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  410. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  411. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  412. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  413. t->time.tm_mon = -1;
  414. t->time.tm_year = -1;
  415. t->time.tm_wday = -1;
  416. t->time.tm_yday = -1;
  417. t->time.tm_isdst = -1;
  418. /* ... and status */
  419. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  420. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  421. dev_dbg(dev, "%s secs=%d, mins=%d, "
  422. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  423. "alarm read", t->time.tm_sec, t->time.tm_min,
  424. t->time.tm_hour, t->time.tm_mday,
  425. t->enabled, t->pending);
  426. return 0;
  427. }
  428. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  429. {
  430. struct i2c_client *client = to_i2c_client(dev);
  431. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  432. unsigned char *buf = ds1307->regs;
  433. u8 control, status;
  434. int ret;
  435. if (!test_bit(HAS_ALARM, &ds1307->flags))
  436. return -EINVAL;
  437. dev_dbg(dev, "%s secs=%d, mins=%d, "
  438. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  439. "alarm set", t->time.tm_sec, t->time.tm_min,
  440. t->time.tm_hour, t->time.tm_mday,
  441. t->enabled, t->pending);
  442. /* read current status of both alarms and the chip */
  443. ret = ds1307->read_block_data(client,
  444. DS1339_REG_ALARM1_SECS, 9, buf);
  445. if (ret != 9) {
  446. dev_err(dev, "%s error %d\n", "alarm write", ret);
  447. return -EIO;
  448. }
  449. control = ds1307->regs[7];
  450. status = ds1307->regs[8];
  451. dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
  452. &ds1307->regs[0], &ds1307->regs[4], control, status);
  453. /* set ALARM1, using 24 hour and day-of-month modes */
  454. buf[0] = bin2bcd(t->time.tm_sec);
  455. buf[1] = bin2bcd(t->time.tm_min);
  456. buf[2] = bin2bcd(t->time.tm_hour);
  457. buf[3] = bin2bcd(t->time.tm_mday);
  458. /* set ALARM2 to non-garbage */
  459. buf[4] = 0;
  460. buf[5] = 0;
  461. buf[6] = 0;
  462. /* optionally enable ALARM1 */
  463. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  464. if (t->enabled) {
  465. dev_dbg(dev, "alarm IRQ armed\n");
  466. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  467. }
  468. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  469. ret = ds1307->write_block_data(client,
  470. DS1339_REG_ALARM1_SECS, 9, buf);
  471. if (ret < 0) {
  472. dev_err(dev, "can't set alarm time\n");
  473. return ret;
  474. }
  475. return 0;
  476. }
  477. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  478. {
  479. struct i2c_client *client = to_i2c_client(dev);
  480. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  481. int ret;
  482. if (!test_bit(HAS_ALARM, &ds1307->flags))
  483. return -ENOTTY;
  484. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  485. if (ret < 0)
  486. return ret;
  487. if (enabled)
  488. ret |= DS1337_BIT_A1IE;
  489. else
  490. ret &= ~DS1337_BIT_A1IE;
  491. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  492. if (ret < 0)
  493. return ret;
  494. return 0;
  495. }
  496. static const struct rtc_class_ops ds13xx_rtc_ops = {
  497. .read_time = ds1307_get_time,
  498. .set_time = ds1307_set_time,
  499. .read_alarm = ds1337_read_alarm,
  500. .set_alarm = ds1337_set_alarm,
  501. .alarm_irq_enable = ds1307_alarm_irq_enable,
  502. };
  503. /*----------------------------------------------------------------------*/
  504. /*
  505. * Alarm support for mcp794xx devices.
  506. */
  507. #define MCP794XX_REG_CONTROL 0x07
  508. # define MCP794XX_BIT_ALM0_EN 0x10
  509. # define MCP794XX_BIT_ALM1_EN 0x20
  510. #define MCP794XX_REG_ALARM0_BASE 0x0a
  511. #define MCP794XX_REG_ALARM0_CTRL 0x0d
  512. #define MCP794XX_REG_ALARM1_BASE 0x11
  513. #define MCP794XX_REG_ALARM1_CTRL 0x14
  514. # define MCP794XX_BIT_ALMX_IF (1 << 3)
  515. # define MCP794XX_BIT_ALMX_C0 (1 << 4)
  516. # define MCP794XX_BIT_ALMX_C1 (1 << 5)
  517. # define MCP794XX_BIT_ALMX_C2 (1 << 6)
  518. # define MCP794XX_BIT_ALMX_POL (1 << 7)
  519. # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
  520. MCP794XX_BIT_ALMX_C1 | \
  521. MCP794XX_BIT_ALMX_C2)
  522. static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
  523. {
  524. struct i2c_client *client = dev_id;
  525. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  526. struct mutex *lock = &ds1307->rtc->ops_lock;
  527. int reg, ret;
  528. mutex_lock(lock);
  529. /* Check and clear alarm 0 interrupt flag. */
  530. reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_ALARM0_CTRL);
  531. if (reg < 0)
  532. goto out;
  533. if (!(reg & MCP794XX_BIT_ALMX_IF))
  534. goto out;
  535. reg &= ~MCP794XX_BIT_ALMX_IF;
  536. ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_ALARM0_CTRL, reg);
  537. if (ret < 0)
  538. goto out;
  539. /* Disable alarm 0. */
  540. reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
  541. if (reg < 0)
  542. goto out;
  543. reg &= ~MCP794XX_BIT_ALM0_EN;
  544. ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
  545. if (ret < 0)
  546. goto out;
  547. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  548. out:
  549. mutex_unlock(lock);
  550. return IRQ_HANDLED;
  551. }
  552. static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  553. {
  554. struct i2c_client *client = to_i2c_client(dev);
  555. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  556. u8 *regs = ds1307->regs;
  557. int ret;
  558. if (!test_bit(HAS_ALARM, &ds1307->flags))
  559. return -EINVAL;
  560. /* Read control and alarm 0 registers. */
  561. ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
  562. if (ret < 0)
  563. return ret;
  564. t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
  565. /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
  566. t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
  567. t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
  568. t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
  569. t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
  570. t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
  571. t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
  572. t->time.tm_year = -1;
  573. t->time.tm_yday = -1;
  574. t->time.tm_isdst = -1;
  575. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  576. "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
  577. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  578. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
  579. !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
  580. !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
  581. (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
  582. return 0;
  583. }
  584. static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  585. {
  586. struct i2c_client *client = to_i2c_client(dev);
  587. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  588. unsigned char *regs = ds1307->regs;
  589. int ret;
  590. if (!test_bit(HAS_ALARM, &ds1307->flags))
  591. return -EINVAL;
  592. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  593. "enabled=%d pending=%d\n", __func__,
  594. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  595. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
  596. t->enabled, t->pending);
  597. /* Read control and alarm 0 registers. */
  598. ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
  599. if (ret < 0)
  600. return ret;
  601. /* Set alarm 0, using 24-hour and day-of-month modes. */
  602. regs[3] = bin2bcd(t->time.tm_sec);
  603. regs[4] = bin2bcd(t->time.tm_min);
  604. regs[5] = bin2bcd(t->time.tm_hour);
  605. regs[6] = bin2bcd(t->time.tm_wday + 1);
  606. regs[7] = bin2bcd(t->time.tm_mday);
  607. regs[8] = bin2bcd(t->time.tm_mon + 1);
  608. /* Clear the alarm 0 interrupt flag. */
  609. regs[6] &= ~MCP794XX_BIT_ALMX_IF;
  610. /* Set alarm match: second, minute, hour, day, date, month. */
  611. regs[6] |= MCP794XX_MSK_ALMX_MATCH;
  612. /* Disable interrupt. We will not enable until completely programmed */
  613. regs[0] &= ~MCP794XX_BIT_ALM0_EN;
  614. ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
  615. if (ret < 0)
  616. return ret;
  617. if (!t->enabled)
  618. return 0;
  619. regs[0] |= MCP794XX_BIT_ALM0_EN;
  620. return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, regs[0]);
  621. }
  622. static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
  623. {
  624. struct i2c_client *client = to_i2c_client(dev);
  625. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  626. int reg;
  627. if (!test_bit(HAS_ALARM, &ds1307->flags))
  628. return -EINVAL;
  629. reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
  630. if (reg < 0)
  631. return reg;
  632. if (enabled)
  633. reg |= MCP794XX_BIT_ALM0_EN;
  634. else
  635. reg &= ~MCP794XX_BIT_ALM0_EN;
  636. return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
  637. }
  638. static const struct rtc_class_ops mcp794xx_rtc_ops = {
  639. .read_time = ds1307_get_time,
  640. .set_time = ds1307_set_time,
  641. .read_alarm = mcp794xx_read_alarm,
  642. .set_alarm = mcp794xx_set_alarm,
  643. .alarm_irq_enable = mcp794xx_alarm_irq_enable,
  644. };
  645. /*----------------------------------------------------------------------*/
  646. static ssize_t
  647. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  648. struct bin_attribute *attr,
  649. char *buf, loff_t off, size_t count)
  650. {
  651. struct i2c_client *client;
  652. struct ds1307 *ds1307;
  653. int result;
  654. client = kobj_to_i2c_client(kobj);
  655. ds1307 = i2c_get_clientdata(client);
  656. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  657. count, buf);
  658. if (result < 0)
  659. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  660. return result;
  661. }
  662. static ssize_t
  663. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  664. struct bin_attribute *attr,
  665. char *buf, loff_t off, size_t count)
  666. {
  667. struct i2c_client *client;
  668. struct ds1307 *ds1307;
  669. int result;
  670. client = kobj_to_i2c_client(kobj);
  671. ds1307 = i2c_get_clientdata(client);
  672. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  673. count, buf);
  674. if (result < 0) {
  675. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  676. return result;
  677. }
  678. return count;
  679. }
  680. /*----------------------------------------------------------------------*/
  681. static u8 do_trickle_setup_ds1339(struct i2c_client *client,
  682. uint32_t ohms, bool diode)
  683. {
  684. u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
  685. DS1307_TRICKLE_CHARGER_NO_DIODE;
  686. switch (ohms) {
  687. case 250:
  688. setup |= DS1307_TRICKLE_CHARGER_250_OHM;
  689. break;
  690. case 2000:
  691. setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
  692. break;
  693. case 4000:
  694. setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
  695. break;
  696. default:
  697. dev_warn(&client->dev,
  698. "Unsupported ohm value %u in dt\n", ohms);
  699. return 0;
  700. }
  701. return setup;
  702. }
  703. static void ds1307_trickle_of_init(struct i2c_client *client,
  704. struct chip_desc *chip)
  705. {
  706. uint32_t ohms = 0;
  707. bool diode = true;
  708. if (!chip->do_trickle_setup)
  709. goto out;
  710. if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms))
  711. goto out;
  712. if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable"))
  713. diode = false;
  714. chip->trickle_charger_setup = chip->do_trickle_setup(client,
  715. ohms, diode);
  716. out:
  717. return;
  718. }
  719. static int ds1307_probe(struct i2c_client *client,
  720. const struct i2c_device_id *id)
  721. {
  722. struct ds1307 *ds1307;
  723. int err = -ENODEV;
  724. int tmp;
  725. struct chip_desc *chip = &chips[id->driver_data];
  726. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  727. bool want_irq = false;
  728. unsigned char *buf;
  729. struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
  730. irq_handler_t irq_handler = ds1307_irq;
  731. static const int bbsqi_bitpos[] = {
  732. [ds_1337] = 0,
  733. [ds_1339] = DS1339_BIT_BBSQI,
  734. [ds_3231] = DS3231_BIT_BBSQW,
  735. };
  736. const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
  737. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  738. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  739. return -EIO;
  740. ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
  741. if (!ds1307)
  742. return -ENOMEM;
  743. i2c_set_clientdata(client, ds1307);
  744. ds1307->client = client;
  745. ds1307->type = id->driver_data;
  746. if (!pdata && client->dev.of_node)
  747. ds1307_trickle_of_init(client, chip);
  748. else if (pdata && pdata->trickle_charger_setup)
  749. chip->trickle_charger_setup = pdata->trickle_charger_setup;
  750. if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
  751. dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n",
  752. DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
  753. chip->trickle_charger_reg);
  754. i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
  755. DS13XX_TRICKLE_CHARGER_MAGIC |
  756. chip->trickle_charger_setup);
  757. }
  758. buf = ds1307->regs;
  759. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  760. ds1307->read_block_data = ds1307_native_smbus_read_block_data;
  761. ds1307->write_block_data = ds1307_native_smbus_write_block_data;
  762. } else {
  763. ds1307->read_block_data = ds1307_read_block_data;
  764. ds1307->write_block_data = ds1307_write_block_data;
  765. }
  766. switch (ds1307->type) {
  767. case ds_1337:
  768. case ds_1339:
  769. case ds_3231:
  770. /* get registers that the "rtc" read below won't read... */
  771. tmp = ds1307->read_block_data(ds1307->client,
  772. DS1337_REG_CONTROL, 2, buf);
  773. if (tmp != 2) {
  774. dev_dbg(&client->dev, "read error %d\n", tmp);
  775. err = -EIO;
  776. goto exit;
  777. }
  778. /* oscillator off? turn it on, so clock can tick. */
  779. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  780. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  781. /*
  782. * Using IRQ? Disable the square wave and both alarms.
  783. * For some variants, be sure alarms can trigger when we're
  784. * running on Vbackup (BBSQI/BBSQW)
  785. */
  786. if (ds1307->client->irq > 0 && chip->alarm) {
  787. ds1307->regs[0] |= DS1337_BIT_INTCN
  788. | bbsqi_bitpos[ds1307->type];
  789. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  790. want_irq = true;
  791. }
  792. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  793. ds1307->regs[0]);
  794. /* oscillator fault? clear flag, and warn */
  795. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  796. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  797. ds1307->regs[1] & ~DS1337_BIT_OSF);
  798. dev_warn(&client->dev, "SET TIME!\n");
  799. }
  800. break;
  801. case rx_8025:
  802. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  803. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  804. if (tmp != 2) {
  805. dev_dbg(&client->dev, "read error %d\n", tmp);
  806. err = -EIO;
  807. goto exit;
  808. }
  809. /* oscillator off? turn it on, so clock can tick. */
  810. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  811. ds1307->regs[1] |= RX8025_BIT_XST;
  812. i2c_smbus_write_byte_data(client,
  813. RX8025_REG_CTRL2 << 4 | 0x08,
  814. ds1307->regs[1]);
  815. dev_warn(&client->dev,
  816. "oscillator stop detected - SET TIME!\n");
  817. }
  818. if (ds1307->regs[1] & RX8025_BIT_PON) {
  819. ds1307->regs[1] &= ~RX8025_BIT_PON;
  820. i2c_smbus_write_byte_data(client,
  821. RX8025_REG_CTRL2 << 4 | 0x08,
  822. ds1307->regs[1]);
  823. dev_warn(&client->dev, "power-on detected\n");
  824. }
  825. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  826. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  827. i2c_smbus_write_byte_data(client,
  828. RX8025_REG_CTRL2 << 4 | 0x08,
  829. ds1307->regs[1]);
  830. dev_warn(&client->dev, "voltage drop detected\n");
  831. }
  832. /* make sure we are running in 24hour mode */
  833. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  834. u8 hour;
  835. /* switch to 24 hour mode */
  836. i2c_smbus_write_byte_data(client,
  837. RX8025_REG_CTRL1 << 4 | 0x08,
  838. ds1307->regs[0] |
  839. RX8025_BIT_2412);
  840. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  841. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  842. if (tmp != 2) {
  843. dev_dbg(&client->dev, "read error %d\n", tmp);
  844. err = -EIO;
  845. goto exit;
  846. }
  847. /* correct hour */
  848. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  849. if (hour == 12)
  850. hour = 0;
  851. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  852. hour += 12;
  853. i2c_smbus_write_byte_data(client,
  854. DS1307_REG_HOUR << 4 | 0x08,
  855. hour);
  856. }
  857. break;
  858. case ds_1388:
  859. ds1307->offset = 1; /* Seconds starts at 1 */
  860. break;
  861. case mcp794xx:
  862. rtc_ops = &mcp794xx_rtc_ops;
  863. if (ds1307->client->irq > 0 && chip->alarm) {
  864. irq_handler = mcp794xx_irq;
  865. want_irq = true;
  866. }
  867. break;
  868. default:
  869. break;
  870. }
  871. read_rtc:
  872. /* read RTC registers */
  873. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  874. if (tmp != 8) {
  875. dev_dbg(&client->dev, "read error %d\n", tmp);
  876. err = -EIO;
  877. goto exit;
  878. }
  879. /*
  880. * minimal sanity checking; some chips (like DS1340) don't
  881. * specify the extra bits as must-be-zero, but there are
  882. * still a few values that are clearly out-of-range.
  883. */
  884. tmp = ds1307->regs[DS1307_REG_SECS];
  885. switch (ds1307->type) {
  886. case ds_1307:
  887. case m41t00:
  888. /* clock halted? turn it on, so clock can tick. */
  889. if (tmp & DS1307_BIT_CH) {
  890. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  891. dev_warn(&client->dev, "SET TIME!\n");
  892. goto read_rtc;
  893. }
  894. break;
  895. case ds_1338:
  896. /* clock halted? turn it on, so clock can tick. */
  897. if (tmp & DS1307_BIT_CH)
  898. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  899. /* oscillator fault? clear flag, and warn */
  900. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  901. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  902. ds1307->regs[DS1307_REG_CONTROL]
  903. & ~DS1338_BIT_OSF);
  904. dev_warn(&client->dev, "SET TIME!\n");
  905. goto read_rtc;
  906. }
  907. break;
  908. case ds_1340:
  909. /* clock halted? turn it on, so clock can tick. */
  910. if (tmp & DS1340_BIT_nEOSC)
  911. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  912. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  913. if (tmp < 0) {
  914. dev_dbg(&client->dev, "read error %d\n", tmp);
  915. err = -EIO;
  916. goto exit;
  917. }
  918. /* oscillator fault? clear flag, and warn */
  919. if (tmp & DS1340_BIT_OSF) {
  920. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  921. dev_warn(&client->dev, "SET TIME!\n");
  922. }
  923. break;
  924. case mcp794xx:
  925. /* make sure that the backup battery is enabled */
  926. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
  927. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  928. ds1307->regs[DS1307_REG_WDAY]
  929. | MCP794XX_BIT_VBATEN);
  930. }
  931. /* clock halted? turn it on, so clock can tick. */
  932. if (!(tmp & MCP794XX_BIT_ST)) {
  933. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  934. MCP794XX_BIT_ST);
  935. dev_warn(&client->dev, "SET TIME!\n");
  936. goto read_rtc;
  937. }
  938. break;
  939. default:
  940. break;
  941. }
  942. tmp = ds1307->regs[DS1307_REG_HOUR];
  943. switch (ds1307->type) {
  944. case ds_1340:
  945. case m41t00:
  946. /*
  947. * NOTE: ignores century bits; fix before deploying
  948. * systems that will run through year 2100.
  949. */
  950. break;
  951. case rx_8025:
  952. break;
  953. default:
  954. if (!(tmp & DS1307_BIT_12HR))
  955. break;
  956. /*
  957. * Be sure we're in 24 hour mode. Multi-master systems
  958. * take note...
  959. */
  960. tmp = bcd2bin(tmp & 0x1f);
  961. if (tmp == 12)
  962. tmp = 0;
  963. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  964. tmp += 12;
  965. i2c_smbus_write_byte_data(client,
  966. ds1307->offset + DS1307_REG_HOUR,
  967. bin2bcd(tmp));
  968. }
  969. if (want_irq) {
  970. device_set_wakeup_capable(&client->dev, true);
  971. set_bit(HAS_ALARM, &ds1307->flags);
  972. }
  973. ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
  974. rtc_ops, THIS_MODULE);
  975. if (IS_ERR(ds1307->rtc)) {
  976. return PTR_ERR(ds1307->rtc);
  977. }
  978. if (want_irq) {
  979. err = devm_request_threaded_irq(&client->dev,
  980. client->irq, NULL, irq_handler,
  981. IRQF_SHARED | IRQF_ONESHOT,
  982. ds1307->rtc->name, client);
  983. if (err) {
  984. client->irq = 0;
  985. device_set_wakeup_capable(&client->dev, false);
  986. clear_bit(HAS_ALARM, &ds1307->flags);
  987. dev_err(&client->dev, "unable to request IRQ!\n");
  988. } else
  989. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  990. }
  991. if (chip->nvram_size) {
  992. ds1307->nvram = devm_kzalloc(&client->dev,
  993. sizeof(struct bin_attribute),
  994. GFP_KERNEL);
  995. if (!ds1307->nvram) {
  996. dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
  997. } else {
  998. ds1307->nvram->attr.name = "nvram";
  999. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  1000. sysfs_bin_attr_init(ds1307->nvram);
  1001. ds1307->nvram->read = ds1307_nvram_read;
  1002. ds1307->nvram->write = ds1307_nvram_write;
  1003. ds1307->nvram->size = chip->nvram_size;
  1004. ds1307->nvram_offset = chip->nvram_offset;
  1005. err = sysfs_create_bin_file(&client->dev.kobj,
  1006. ds1307->nvram);
  1007. if (err) {
  1008. dev_err(&client->dev,
  1009. "unable to create sysfs file: %s\n",
  1010. ds1307->nvram->attr.name);
  1011. } else {
  1012. set_bit(HAS_NVRAM, &ds1307->flags);
  1013. dev_info(&client->dev, "%zu bytes nvram\n",
  1014. ds1307->nvram->size);
  1015. }
  1016. }
  1017. }
  1018. return 0;
  1019. exit:
  1020. return err;
  1021. }
  1022. static int ds1307_remove(struct i2c_client *client)
  1023. {
  1024. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  1025. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
  1026. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  1027. return 0;
  1028. }
  1029. static struct i2c_driver ds1307_driver = {
  1030. .driver = {
  1031. .name = "rtc-ds1307",
  1032. },
  1033. .probe = ds1307_probe,
  1034. .remove = ds1307_remove,
  1035. .id_table = ds1307_id,
  1036. };
  1037. module_i2c_driver(ds1307_driver);
  1038. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  1039. MODULE_LICENSE("GPL");