uc.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578
  1. /*
  2. * Copyright(c) 2015, 2016 Intel Corporation.
  3. *
  4. * This file is provided under a dual BSD/GPLv2 license. When using or
  5. * redistributing this file, you may do so under either license.
  6. *
  7. * GPL LICENSE SUMMARY
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of version 2 of the GNU General Public License as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. * BSD LICENSE
  19. *
  20. * Redistribution and use in source and binary forms, with or without
  21. * modification, are permitted provided that the following conditions
  22. * are met:
  23. *
  24. * - Redistributions of source code must retain the above copyright
  25. * notice, this list of conditions and the following disclaimer.
  26. * - Redistributions in binary form must reproduce the above copyright
  27. * notice, this list of conditions and the following disclaimer in
  28. * the documentation and/or other materials provided with the
  29. * distribution.
  30. * - Neither the name of Intel Corporation nor the names of its
  31. * contributors may be used to endorse or promote products derived
  32. * from this software without specific prior written permission.
  33. *
  34. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45. *
  46. */
  47. #include "hfi.h"
  48. #include "verbs_txreq.h"
  49. #include "qp.h"
  50. /* cut down ridiculously long IB macro names */
  51. #define OP(x) UC_OP(x)
  52. /**
  53. * hfi1_make_uc_req - construct a request packet (SEND, RDMA write)
  54. * @qp: a pointer to the QP
  55. *
  56. * Assume s_lock is held.
  57. *
  58. * Return 1 if constructed; otherwise, return 0.
  59. */
  60. int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
  61. {
  62. struct hfi1_qp_priv *priv = qp->priv;
  63. struct ib_other_headers *ohdr;
  64. struct rvt_swqe *wqe;
  65. u32 hwords = 5;
  66. u32 bth0 = 0;
  67. u32 len;
  68. u32 pmtu = qp->pmtu;
  69. int middle = 0;
  70. ps->s_txreq = get_txreq(ps->dev, qp);
  71. if (IS_ERR(ps->s_txreq))
  72. goto bail_no_tx;
  73. if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_SEND_OK)) {
  74. if (!(ib_rvt_state_ops[qp->state] & RVT_FLUSH_SEND))
  75. goto bail;
  76. /* We are in the error state, flush the work request. */
  77. smp_read_barrier_depends(); /* see post_one_send() */
  78. if (qp->s_last == ACCESS_ONCE(qp->s_head))
  79. goto bail;
  80. /* If DMAs are in progress, we can't flush immediately. */
  81. if (iowait_sdma_pending(&priv->s_iowait)) {
  82. qp->s_flags |= RVT_S_WAIT_DMA;
  83. goto bail;
  84. }
  85. clear_ahg(qp);
  86. wqe = rvt_get_swqe_ptr(qp, qp->s_last);
  87. hfi1_send_complete(qp, wqe, IB_WC_WR_FLUSH_ERR);
  88. goto done_free_tx;
  89. }
  90. ohdr = &ps->s_txreq->phdr.hdr.u.oth;
  91. if (rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH)
  92. ohdr = &ps->s_txreq->phdr.hdr.u.l.oth;
  93. /* Get the next send request. */
  94. wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
  95. qp->s_wqe = NULL;
  96. switch (qp->s_state) {
  97. default:
  98. if (!(ib_rvt_state_ops[qp->state] &
  99. RVT_PROCESS_NEXT_SEND_OK))
  100. goto bail;
  101. /* Check if send work queue is empty. */
  102. smp_read_barrier_depends(); /* see post_one_send() */
  103. if (qp->s_cur == ACCESS_ONCE(qp->s_head)) {
  104. clear_ahg(qp);
  105. goto bail;
  106. }
  107. /*
  108. * Local operations are processed immediately
  109. * after all prior requests have completed.
  110. */
  111. if (wqe->wr.opcode == IB_WR_REG_MR ||
  112. wqe->wr.opcode == IB_WR_LOCAL_INV) {
  113. int local_ops = 0;
  114. int err = 0;
  115. if (qp->s_last != qp->s_cur)
  116. goto bail;
  117. if (++qp->s_cur == qp->s_size)
  118. qp->s_cur = 0;
  119. if (!(wqe->wr.send_flags & RVT_SEND_COMPLETION_ONLY)) {
  120. err = rvt_invalidate_rkey(
  121. qp, wqe->wr.ex.invalidate_rkey);
  122. local_ops = 1;
  123. }
  124. hfi1_send_complete(qp, wqe, err ? IB_WC_LOC_PROT_ERR
  125. : IB_WC_SUCCESS);
  126. if (local_ops)
  127. atomic_dec(&qp->local_ops_pending);
  128. qp->s_hdrwords = 0;
  129. goto done_free_tx;
  130. }
  131. /*
  132. * Start a new request.
  133. */
  134. qp->s_psn = wqe->psn;
  135. qp->s_sge.sge = wqe->sg_list[0];
  136. qp->s_sge.sg_list = wqe->sg_list + 1;
  137. qp->s_sge.num_sge = wqe->wr.num_sge;
  138. qp->s_sge.total_len = wqe->length;
  139. len = wqe->length;
  140. qp->s_len = len;
  141. switch (wqe->wr.opcode) {
  142. case IB_WR_SEND:
  143. case IB_WR_SEND_WITH_IMM:
  144. if (len > pmtu) {
  145. qp->s_state = OP(SEND_FIRST);
  146. len = pmtu;
  147. break;
  148. }
  149. if (wqe->wr.opcode == IB_WR_SEND) {
  150. qp->s_state = OP(SEND_ONLY);
  151. } else {
  152. qp->s_state =
  153. OP(SEND_ONLY_WITH_IMMEDIATE);
  154. /* Immediate data comes after the BTH */
  155. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  156. hwords += 1;
  157. }
  158. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  159. bth0 |= IB_BTH_SOLICITED;
  160. qp->s_wqe = wqe;
  161. if (++qp->s_cur >= qp->s_size)
  162. qp->s_cur = 0;
  163. break;
  164. case IB_WR_RDMA_WRITE:
  165. case IB_WR_RDMA_WRITE_WITH_IMM:
  166. ohdr->u.rc.reth.vaddr =
  167. cpu_to_be64(wqe->rdma_wr.remote_addr);
  168. ohdr->u.rc.reth.rkey =
  169. cpu_to_be32(wqe->rdma_wr.rkey);
  170. ohdr->u.rc.reth.length = cpu_to_be32(len);
  171. hwords += sizeof(struct ib_reth) / 4;
  172. if (len > pmtu) {
  173. qp->s_state = OP(RDMA_WRITE_FIRST);
  174. len = pmtu;
  175. break;
  176. }
  177. if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
  178. qp->s_state = OP(RDMA_WRITE_ONLY);
  179. } else {
  180. qp->s_state =
  181. OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
  182. /* Immediate data comes after the RETH */
  183. ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
  184. hwords += 1;
  185. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  186. bth0 |= IB_BTH_SOLICITED;
  187. }
  188. qp->s_wqe = wqe;
  189. if (++qp->s_cur >= qp->s_size)
  190. qp->s_cur = 0;
  191. break;
  192. default:
  193. goto bail;
  194. }
  195. break;
  196. case OP(SEND_FIRST):
  197. qp->s_state = OP(SEND_MIDDLE);
  198. /* FALLTHROUGH */
  199. case OP(SEND_MIDDLE):
  200. len = qp->s_len;
  201. if (len > pmtu) {
  202. len = pmtu;
  203. middle = HFI1_CAP_IS_KSET(SDMA_AHG);
  204. break;
  205. }
  206. if (wqe->wr.opcode == IB_WR_SEND) {
  207. qp->s_state = OP(SEND_LAST);
  208. } else {
  209. qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
  210. /* Immediate data comes after the BTH */
  211. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  212. hwords += 1;
  213. }
  214. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  215. bth0 |= IB_BTH_SOLICITED;
  216. qp->s_wqe = wqe;
  217. if (++qp->s_cur >= qp->s_size)
  218. qp->s_cur = 0;
  219. break;
  220. case OP(RDMA_WRITE_FIRST):
  221. qp->s_state = OP(RDMA_WRITE_MIDDLE);
  222. /* FALLTHROUGH */
  223. case OP(RDMA_WRITE_MIDDLE):
  224. len = qp->s_len;
  225. if (len > pmtu) {
  226. len = pmtu;
  227. middle = HFI1_CAP_IS_KSET(SDMA_AHG);
  228. break;
  229. }
  230. if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
  231. qp->s_state = OP(RDMA_WRITE_LAST);
  232. } else {
  233. qp->s_state =
  234. OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
  235. /* Immediate data comes after the BTH */
  236. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  237. hwords += 1;
  238. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  239. bth0 |= IB_BTH_SOLICITED;
  240. }
  241. qp->s_wqe = wqe;
  242. if (++qp->s_cur >= qp->s_size)
  243. qp->s_cur = 0;
  244. break;
  245. }
  246. qp->s_len -= len;
  247. qp->s_hdrwords = hwords;
  248. ps->s_txreq->sde = priv->s_sde;
  249. ps->s_txreq->ss = &qp->s_sge;
  250. ps->s_txreq->s_cur_size = len;
  251. hfi1_make_ruc_header(qp, ohdr, bth0 | (qp->s_state << 24),
  252. mask_psn(qp->s_psn++), middle, ps);
  253. /* pbc */
  254. ps->s_txreq->hdr_dwords = qp->s_hdrwords + 2;
  255. return 1;
  256. done_free_tx:
  257. hfi1_put_txreq(ps->s_txreq);
  258. ps->s_txreq = NULL;
  259. return 1;
  260. bail:
  261. hfi1_put_txreq(ps->s_txreq);
  262. bail_no_tx:
  263. ps->s_txreq = NULL;
  264. qp->s_flags &= ~RVT_S_BUSY;
  265. qp->s_hdrwords = 0;
  266. return 0;
  267. }
  268. /**
  269. * hfi1_uc_rcv - handle an incoming UC packet
  270. * @ibp: the port the packet came in on
  271. * @hdr: the header of the packet
  272. * @rcv_flags: flags relevant to rcv processing
  273. * @data: the packet data
  274. * @tlen: the length of the packet
  275. * @qp: the QP for this packet.
  276. *
  277. * This is called from qp_rcv() to process an incoming UC packet
  278. * for the given QP.
  279. * Called at interrupt level.
  280. */
  281. void hfi1_uc_rcv(struct hfi1_packet *packet)
  282. {
  283. struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
  284. void *data = packet->ebuf;
  285. u32 tlen = packet->tlen;
  286. struct rvt_qp *qp = packet->qp;
  287. struct ib_other_headers *ohdr = packet->ohdr;
  288. u32 opcode = packet->opcode;
  289. u32 hdrsize = packet->hlen;
  290. u32 psn;
  291. u32 pad = packet->pad;
  292. struct ib_wc wc;
  293. u32 pmtu = qp->pmtu;
  294. struct ib_reth *reth;
  295. int ret;
  296. if (hfi1_ruc_check_hdr(ibp, packet))
  297. return;
  298. process_ecn(qp, packet, true);
  299. psn = ib_bth_get_psn(ohdr);
  300. /* Compare the PSN verses the expected PSN. */
  301. if (unlikely(cmp_psn(psn, qp->r_psn) != 0)) {
  302. /*
  303. * Handle a sequence error.
  304. * Silently drop any current message.
  305. */
  306. qp->r_psn = psn;
  307. inv:
  308. if (qp->r_state == OP(SEND_FIRST) ||
  309. qp->r_state == OP(SEND_MIDDLE)) {
  310. set_bit(RVT_R_REWIND_SGE, &qp->r_aflags);
  311. qp->r_sge.num_sge = 0;
  312. } else {
  313. rvt_put_ss(&qp->r_sge);
  314. }
  315. qp->r_state = OP(SEND_LAST);
  316. switch (opcode) {
  317. case OP(SEND_FIRST):
  318. case OP(SEND_ONLY):
  319. case OP(SEND_ONLY_WITH_IMMEDIATE):
  320. goto send_first;
  321. case OP(RDMA_WRITE_FIRST):
  322. case OP(RDMA_WRITE_ONLY):
  323. case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
  324. goto rdma_first;
  325. default:
  326. goto drop;
  327. }
  328. }
  329. /* Check for opcode sequence errors. */
  330. switch (qp->r_state) {
  331. case OP(SEND_FIRST):
  332. case OP(SEND_MIDDLE):
  333. if (opcode == OP(SEND_MIDDLE) ||
  334. opcode == OP(SEND_LAST) ||
  335. opcode == OP(SEND_LAST_WITH_IMMEDIATE))
  336. break;
  337. goto inv;
  338. case OP(RDMA_WRITE_FIRST):
  339. case OP(RDMA_WRITE_MIDDLE):
  340. if (opcode == OP(RDMA_WRITE_MIDDLE) ||
  341. opcode == OP(RDMA_WRITE_LAST) ||
  342. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  343. break;
  344. goto inv;
  345. default:
  346. if (opcode == OP(SEND_FIRST) ||
  347. opcode == OP(SEND_ONLY) ||
  348. opcode == OP(SEND_ONLY_WITH_IMMEDIATE) ||
  349. opcode == OP(RDMA_WRITE_FIRST) ||
  350. opcode == OP(RDMA_WRITE_ONLY) ||
  351. opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
  352. break;
  353. goto inv;
  354. }
  355. if (qp->state == IB_QPS_RTR && !(qp->r_flags & RVT_R_COMM_EST))
  356. rvt_comm_est(qp);
  357. /* OK, process the packet. */
  358. switch (opcode) {
  359. case OP(SEND_FIRST):
  360. case OP(SEND_ONLY):
  361. case OP(SEND_ONLY_WITH_IMMEDIATE):
  362. send_first:
  363. if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags)) {
  364. qp->r_sge = qp->s_rdma_read_sge;
  365. } else {
  366. ret = hfi1_rvt_get_rwqe(qp, 0);
  367. if (ret < 0)
  368. goto op_err;
  369. if (!ret)
  370. goto drop;
  371. /*
  372. * qp->s_rdma_read_sge will be the owner
  373. * of the mr references.
  374. */
  375. qp->s_rdma_read_sge = qp->r_sge;
  376. }
  377. qp->r_rcv_len = 0;
  378. if (opcode == OP(SEND_ONLY))
  379. goto no_immediate_data;
  380. else if (opcode == OP(SEND_ONLY_WITH_IMMEDIATE))
  381. goto send_last_imm;
  382. /* FALLTHROUGH */
  383. case OP(SEND_MIDDLE):
  384. /* Check for invalid length PMTU or posted rwqe len. */
  385. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  386. goto rewind;
  387. qp->r_rcv_len += pmtu;
  388. if (unlikely(qp->r_rcv_len > qp->r_len))
  389. goto rewind;
  390. hfi1_copy_sge(&qp->r_sge, data, pmtu, false, false);
  391. break;
  392. case OP(SEND_LAST_WITH_IMMEDIATE):
  393. send_last_imm:
  394. wc.ex.imm_data = ohdr->u.imm_data;
  395. wc.wc_flags = IB_WC_WITH_IMM;
  396. goto send_last;
  397. case OP(SEND_LAST):
  398. no_immediate_data:
  399. wc.ex.imm_data = 0;
  400. wc.wc_flags = 0;
  401. send_last:
  402. /* Check for invalid length. */
  403. /* LAST len should be >= 1 */
  404. if (unlikely(tlen < (hdrsize + pad + 4)))
  405. goto rewind;
  406. /* Don't count the CRC. */
  407. tlen -= (hdrsize + pad + 4);
  408. wc.byte_len = tlen + qp->r_rcv_len;
  409. if (unlikely(wc.byte_len > qp->r_len))
  410. goto rewind;
  411. wc.opcode = IB_WC_RECV;
  412. hfi1_copy_sge(&qp->r_sge, data, tlen, false, false);
  413. rvt_put_ss(&qp->s_rdma_read_sge);
  414. last_imm:
  415. wc.wr_id = qp->r_wr_id;
  416. wc.status = IB_WC_SUCCESS;
  417. wc.qp = &qp->ibqp;
  418. wc.src_qp = qp->remote_qpn;
  419. wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr);
  420. /*
  421. * It seems that IB mandates the presence of an SL in a
  422. * work completion only for the UD transport (see section
  423. * 11.4.2 of IBTA Vol. 1).
  424. *
  425. * However, the way the SL is chosen below is consistent
  426. * with the way that IB/qib works and is trying avoid
  427. * introducing incompatibilities.
  428. *
  429. * See also OPA Vol. 1, section 9.7.6, and table 9-17.
  430. */
  431. wc.sl = rdma_ah_get_sl(&qp->remote_ah_attr);
  432. /* zero fields that are N/A */
  433. wc.vendor_err = 0;
  434. wc.pkey_index = 0;
  435. wc.dlid_path_bits = 0;
  436. wc.port_num = 0;
  437. /* Signal completion event if the solicited bit is set. */
  438. rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.recv_cq), &wc,
  439. (ohdr->bth[0] &
  440. cpu_to_be32(IB_BTH_SOLICITED)) != 0);
  441. break;
  442. case OP(RDMA_WRITE_FIRST):
  443. case OP(RDMA_WRITE_ONLY):
  444. case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): /* consume RWQE */
  445. rdma_first:
  446. if (unlikely(!(qp->qp_access_flags &
  447. IB_ACCESS_REMOTE_WRITE))) {
  448. goto drop;
  449. }
  450. reth = &ohdr->u.rc.reth;
  451. qp->r_len = be32_to_cpu(reth->length);
  452. qp->r_rcv_len = 0;
  453. qp->r_sge.sg_list = NULL;
  454. if (qp->r_len != 0) {
  455. u32 rkey = be32_to_cpu(reth->rkey);
  456. u64 vaddr = be64_to_cpu(reth->vaddr);
  457. int ok;
  458. /* Check rkey */
  459. ok = rvt_rkey_ok(qp, &qp->r_sge.sge, qp->r_len,
  460. vaddr, rkey, IB_ACCESS_REMOTE_WRITE);
  461. if (unlikely(!ok))
  462. goto drop;
  463. qp->r_sge.num_sge = 1;
  464. } else {
  465. qp->r_sge.num_sge = 0;
  466. qp->r_sge.sge.mr = NULL;
  467. qp->r_sge.sge.vaddr = NULL;
  468. qp->r_sge.sge.length = 0;
  469. qp->r_sge.sge.sge_length = 0;
  470. }
  471. if (opcode == OP(RDMA_WRITE_ONLY)) {
  472. goto rdma_last;
  473. } else if (opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) {
  474. wc.ex.imm_data = ohdr->u.rc.imm_data;
  475. goto rdma_last_imm;
  476. }
  477. /* FALLTHROUGH */
  478. case OP(RDMA_WRITE_MIDDLE):
  479. /* Check for invalid length PMTU or posted rwqe len. */
  480. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  481. goto drop;
  482. qp->r_rcv_len += pmtu;
  483. if (unlikely(qp->r_rcv_len > qp->r_len))
  484. goto drop;
  485. hfi1_copy_sge(&qp->r_sge, data, pmtu, true, false);
  486. break;
  487. case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
  488. wc.ex.imm_data = ohdr->u.imm_data;
  489. rdma_last_imm:
  490. wc.wc_flags = IB_WC_WITH_IMM;
  491. /* Check for invalid length. */
  492. /* LAST len should be >= 1 */
  493. if (unlikely(tlen < (hdrsize + pad + 4)))
  494. goto drop;
  495. /* Don't count the CRC. */
  496. tlen -= (hdrsize + pad + 4);
  497. if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
  498. goto drop;
  499. if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags)) {
  500. rvt_put_ss(&qp->s_rdma_read_sge);
  501. } else {
  502. ret = hfi1_rvt_get_rwqe(qp, 1);
  503. if (ret < 0)
  504. goto op_err;
  505. if (!ret)
  506. goto drop;
  507. }
  508. wc.byte_len = qp->r_len;
  509. wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
  510. hfi1_copy_sge(&qp->r_sge, data, tlen, true, false);
  511. rvt_put_ss(&qp->r_sge);
  512. goto last_imm;
  513. case OP(RDMA_WRITE_LAST):
  514. rdma_last:
  515. /* Get the number of bytes the message was padded by. */
  516. pad = ib_bth_get_pad(ohdr);
  517. /* Check for invalid length. */
  518. /* LAST len should be >= 1 */
  519. if (unlikely(tlen < (hdrsize + pad + 4)))
  520. goto drop;
  521. /* Don't count the CRC. */
  522. tlen -= (hdrsize + pad + 4);
  523. if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
  524. goto drop;
  525. hfi1_copy_sge(&qp->r_sge, data, tlen, true, false);
  526. rvt_put_ss(&qp->r_sge);
  527. break;
  528. default:
  529. /* Drop packet for unknown opcodes. */
  530. goto drop;
  531. }
  532. qp->r_psn++;
  533. qp->r_state = opcode;
  534. return;
  535. rewind:
  536. set_bit(RVT_R_REWIND_SGE, &qp->r_aflags);
  537. qp->r_sge.num_sge = 0;
  538. drop:
  539. ibp->rvp.n_pkt_drops++;
  540. return;
  541. op_err:
  542. rvt_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
  543. }