mcdi.c 50 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2008-2013 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include <asm/cmpxchg.h>
  11. #include "net_driver.h"
  12. #include "nic.h"
  13. #include "io.h"
  14. #include "farch_regs.h"
  15. #include "mcdi_pcol.h"
  16. #include "phy.h"
  17. /**************************************************************************
  18. *
  19. * Management-Controller-to-Driver Interface
  20. *
  21. **************************************************************************
  22. */
  23. #define MCDI_RPC_TIMEOUT (10 * HZ)
  24. /* A reboot/assertion causes the MCDI status word to be set after the
  25. * command word is set or a REBOOT event is sent. If we notice a reboot
  26. * via these mechanisms then wait 250ms for the status word to be set.
  27. */
  28. #define MCDI_STATUS_DELAY_US 100
  29. #define MCDI_STATUS_DELAY_COUNT 2500
  30. #define MCDI_STATUS_SLEEP_MS \
  31. (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
  32. #define SEQ_MASK \
  33. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  34. struct efx_mcdi_async_param {
  35. struct list_head list;
  36. unsigned int cmd;
  37. size_t inlen;
  38. size_t outlen;
  39. bool quiet;
  40. efx_mcdi_async_completer *complete;
  41. unsigned long cookie;
  42. /* followed by request/response buffer */
  43. };
  44. static void efx_mcdi_timeout_async(unsigned long context);
  45. static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  46. bool *was_attached_out);
  47. static bool efx_mcdi_poll_once(struct efx_nic *efx);
  48. static void efx_mcdi_abandon(struct efx_nic *efx);
  49. int efx_mcdi_init(struct efx_nic *efx)
  50. {
  51. struct efx_mcdi_iface *mcdi;
  52. bool already_attached;
  53. int rc;
  54. efx->mcdi = kzalloc(sizeof(*efx->mcdi), GFP_KERNEL);
  55. if (!efx->mcdi)
  56. return -ENOMEM;
  57. mcdi = efx_mcdi(efx);
  58. mcdi->efx = efx;
  59. init_waitqueue_head(&mcdi->wq);
  60. spin_lock_init(&mcdi->iface_lock);
  61. mcdi->state = MCDI_STATE_QUIESCENT;
  62. mcdi->mode = MCDI_MODE_POLL;
  63. spin_lock_init(&mcdi->async_lock);
  64. INIT_LIST_HEAD(&mcdi->async_list);
  65. setup_timer(&mcdi->async_timer, efx_mcdi_timeout_async,
  66. (unsigned long)mcdi);
  67. (void) efx_mcdi_poll_reboot(efx);
  68. mcdi->new_epoch = true;
  69. /* Recover from a failed assertion before probing */
  70. rc = efx_mcdi_handle_assertion(efx);
  71. if (rc)
  72. return rc;
  73. /* Let the MC (and BMC, if this is a LOM) know that the driver
  74. * is loaded. We should do this before we reset the NIC.
  75. */
  76. rc = efx_mcdi_drv_attach(efx, true, &already_attached);
  77. if (rc) {
  78. netif_err(efx, probe, efx->net_dev,
  79. "Unable to register driver with MCPU\n");
  80. return rc;
  81. }
  82. if (already_attached)
  83. /* Not a fatal error */
  84. netif_err(efx, probe, efx->net_dev,
  85. "Host already registered with MCPU\n");
  86. if (efx->mcdi->fn_flags &
  87. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
  88. efx->primary = efx;
  89. return 0;
  90. }
  91. void efx_mcdi_fini(struct efx_nic *efx)
  92. {
  93. if (!efx->mcdi)
  94. return;
  95. BUG_ON(efx->mcdi->iface.state != MCDI_STATE_QUIESCENT);
  96. /* Relinquish the device (back to the BMC, if this is a LOM) */
  97. efx_mcdi_drv_attach(efx, false, NULL);
  98. kfree(efx->mcdi);
  99. }
  100. static void efx_mcdi_send_request(struct efx_nic *efx, unsigned cmd,
  101. const efx_dword_t *inbuf, size_t inlen)
  102. {
  103. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  104. efx_dword_t hdr[2];
  105. size_t hdr_len;
  106. u32 xflags, seqno;
  107. BUG_ON(mcdi->state == MCDI_STATE_QUIESCENT);
  108. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  109. spin_lock_bh(&mcdi->iface_lock);
  110. ++mcdi->seqno;
  111. spin_unlock_bh(&mcdi->iface_lock);
  112. seqno = mcdi->seqno & SEQ_MASK;
  113. xflags = 0;
  114. if (mcdi->mode == MCDI_MODE_EVENTS)
  115. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  116. if (efx->type->mcdi_max_ver == 1) {
  117. /* MCDI v1 */
  118. EFX_POPULATE_DWORD_7(hdr[0],
  119. MCDI_HEADER_RESPONSE, 0,
  120. MCDI_HEADER_RESYNC, 1,
  121. MCDI_HEADER_CODE, cmd,
  122. MCDI_HEADER_DATALEN, inlen,
  123. MCDI_HEADER_SEQ, seqno,
  124. MCDI_HEADER_XFLAGS, xflags,
  125. MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch);
  126. hdr_len = 4;
  127. } else {
  128. /* MCDI v2 */
  129. BUG_ON(inlen > MCDI_CTL_SDU_LEN_MAX_V2);
  130. EFX_POPULATE_DWORD_7(hdr[0],
  131. MCDI_HEADER_RESPONSE, 0,
  132. MCDI_HEADER_RESYNC, 1,
  133. MCDI_HEADER_CODE, MC_CMD_V2_EXTN,
  134. MCDI_HEADER_DATALEN, 0,
  135. MCDI_HEADER_SEQ, seqno,
  136. MCDI_HEADER_XFLAGS, xflags,
  137. MCDI_HEADER_NOT_EPOCH, !mcdi->new_epoch);
  138. EFX_POPULATE_DWORD_2(hdr[1],
  139. MC_CMD_V2_EXTN_IN_EXTENDED_CMD, cmd,
  140. MC_CMD_V2_EXTN_IN_ACTUAL_LEN, inlen);
  141. hdr_len = 8;
  142. }
  143. efx->type->mcdi_request(efx, hdr, hdr_len, inbuf, inlen);
  144. mcdi->new_epoch = false;
  145. }
  146. static int efx_mcdi_errno(unsigned int mcdi_err)
  147. {
  148. switch (mcdi_err) {
  149. case 0:
  150. return 0;
  151. #define TRANSLATE_ERROR(name) \
  152. case MC_CMD_ERR_ ## name: \
  153. return -name;
  154. TRANSLATE_ERROR(EPERM);
  155. TRANSLATE_ERROR(ENOENT);
  156. TRANSLATE_ERROR(EINTR);
  157. TRANSLATE_ERROR(EAGAIN);
  158. TRANSLATE_ERROR(EACCES);
  159. TRANSLATE_ERROR(EBUSY);
  160. TRANSLATE_ERROR(EINVAL);
  161. TRANSLATE_ERROR(EDEADLK);
  162. TRANSLATE_ERROR(ENOSYS);
  163. TRANSLATE_ERROR(ETIME);
  164. TRANSLATE_ERROR(EALREADY);
  165. TRANSLATE_ERROR(ENOSPC);
  166. #undef TRANSLATE_ERROR
  167. case MC_CMD_ERR_ENOTSUP:
  168. return -EOPNOTSUPP;
  169. case MC_CMD_ERR_ALLOC_FAIL:
  170. return -ENOBUFS;
  171. case MC_CMD_ERR_MAC_EXIST:
  172. return -EADDRINUSE;
  173. default:
  174. return -EPROTO;
  175. }
  176. }
  177. static void efx_mcdi_read_response_header(struct efx_nic *efx)
  178. {
  179. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  180. unsigned int respseq, respcmd, error;
  181. efx_dword_t hdr;
  182. efx->type->mcdi_read_response(efx, &hdr, 0, 4);
  183. respseq = EFX_DWORD_FIELD(hdr, MCDI_HEADER_SEQ);
  184. respcmd = EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE);
  185. error = EFX_DWORD_FIELD(hdr, MCDI_HEADER_ERROR);
  186. if (respcmd != MC_CMD_V2_EXTN) {
  187. mcdi->resp_hdr_len = 4;
  188. mcdi->resp_data_len = EFX_DWORD_FIELD(hdr, MCDI_HEADER_DATALEN);
  189. } else {
  190. efx->type->mcdi_read_response(efx, &hdr, 4, 4);
  191. mcdi->resp_hdr_len = 8;
  192. mcdi->resp_data_len =
  193. EFX_DWORD_FIELD(hdr, MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
  194. }
  195. if (error && mcdi->resp_data_len == 0) {
  196. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  197. mcdi->resprc = -EIO;
  198. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  199. netif_err(efx, hw, efx->net_dev,
  200. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  201. respseq, mcdi->seqno);
  202. mcdi->resprc = -EIO;
  203. } else if (error) {
  204. efx->type->mcdi_read_response(efx, &hdr, mcdi->resp_hdr_len, 4);
  205. mcdi->resprc =
  206. efx_mcdi_errno(EFX_DWORD_FIELD(hdr, EFX_DWORD_0));
  207. } else {
  208. mcdi->resprc = 0;
  209. }
  210. }
  211. static bool efx_mcdi_poll_once(struct efx_nic *efx)
  212. {
  213. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  214. rmb();
  215. if (!efx->type->mcdi_poll_response(efx))
  216. return false;
  217. spin_lock_bh(&mcdi->iface_lock);
  218. efx_mcdi_read_response_header(efx);
  219. spin_unlock_bh(&mcdi->iface_lock);
  220. return true;
  221. }
  222. static int efx_mcdi_poll(struct efx_nic *efx)
  223. {
  224. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  225. unsigned long time, finish;
  226. unsigned int spins;
  227. int rc;
  228. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  229. rc = efx_mcdi_poll_reboot(efx);
  230. if (rc) {
  231. spin_lock_bh(&mcdi->iface_lock);
  232. mcdi->resprc = rc;
  233. mcdi->resp_hdr_len = 0;
  234. mcdi->resp_data_len = 0;
  235. spin_unlock_bh(&mcdi->iface_lock);
  236. return 0;
  237. }
  238. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  239. * because generally mcdi responses are fast. After that, back off
  240. * and poll once a jiffy (approximately)
  241. */
  242. spins = TICK_USEC;
  243. finish = jiffies + MCDI_RPC_TIMEOUT;
  244. while (1) {
  245. if (spins != 0) {
  246. --spins;
  247. udelay(1);
  248. } else {
  249. schedule_timeout_uninterruptible(1);
  250. }
  251. time = jiffies;
  252. if (efx_mcdi_poll_once(efx))
  253. break;
  254. if (time_after(time, finish))
  255. return -ETIMEDOUT;
  256. }
  257. /* Return rc=0 like wait_event_timeout() */
  258. return 0;
  259. }
  260. /* Test and clear MC-rebooted flag for this port/function; reset
  261. * software state as necessary.
  262. */
  263. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  264. {
  265. if (!efx->mcdi)
  266. return 0;
  267. return efx->type->mcdi_poll_reboot(efx);
  268. }
  269. static bool efx_mcdi_acquire_async(struct efx_mcdi_iface *mcdi)
  270. {
  271. return cmpxchg(&mcdi->state,
  272. MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_ASYNC) ==
  273. MCDI_STATE_QUIESCENT;
  274. }
  275. static void efx_mcdi_acquire_sync(struct efx_mcdi_iface *mcdi)
  276. {
  277. /* Wait until the interface becomes QUIESCENT and we win the race
  278. * to mark it RUNNING_SYNC.
  279. */
  280. wait_event(mcdi->wq,
  281. cmpxchg(&mcdi->state,
  282. MCDI_STATE_QUIESCENT, MCDI_STATE_RUNNING_SYNC) ==
  283. MCDI_STATE_QUIESCENT);
  284. }
  285. static int efx_mcdi_await_completion(struct efx_nic *efx)
  286. {
  287. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  288. if (wait_event_timeout(mcdi->wq, mcdi->state == MCDI_STATE_COMPLETED,
  289. MCDI_RPC_TIMEOUT) == 0)
  290. return -ETIMEDOUT;
  291. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  292. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  293. * completed the request first, then we'll just end up completing the
  294. * request again, which is safe.
  295. *
  296. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  297. * wait_event_timeout() implicitly provides.
  298. */
  299. if (mcdi->mode == MCDI_MODE_POLL)
  300. return efx_mcdi_poll(efx);
  301. return 0;
  302. }
  303. /* If the interface is RUNNING_SYNC, switch to COMPLETED and wake the
  304. * requester. Return whether this was done. Does not take any locks.
  305. */
  306. static bool efx_mcdi_complete_sync(struct efx_mcdi_iface *mcdi)
  307. {
  308. if (cmpxchg(&mcdi->state,
  309. MCDI_STATE_RUNNING_SYNC, MCDI_STATE_COMPLETED) ==
  310. MCDI_STATE_RUNNING_SYNC) {
  311. wake_up(&mcdi->wq);
  312. return true;
  313. }
  314. return false;
  315. }
  316. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  317. {
  318. if (mcdi->mode == MCDI_MODE_EVENTS) {
  319. struct efx_mcdi_async_param *async;
  320. struct efx_nic *efx = mcdi->efx;
  321. /* Process the asynchronous request queue */
  322. spin_lock_bh(&mcdi->async_lock);
  323. async = list_first_entry_or_null(
  324. &mcdi->async_list, struct efx_mcdi_async_param, list);
  325. if (async) {
  326. mcdi->state = MCDI_STATE_RUNNING_ASYNC;
  327. efx_mcdi_send_request(efx, async->cmd,
  328. (const efx_dword_t *)(async + 1),
  329. async->inlen);
  330. mod_timer(&mcdi->async_timer,
  331. jiffies + MCDI_RPC_TIMEOUT);
  332. }
  333. spin_unlock_bh(&mcdi->async_lock);
  334. if (async)
  335. return;
  336. }
  337. mcdi->state = MCDI_STATE_QUIESCENT;
  338. wake_up(&mcdi->wq);
  339. }
  340. /* If the interface is RUNNING_ASYNC, switch to COMPLETED, call the
  341. * asynchronous completion function, and release the interface.
  342. * Return whether this was done. Must be called in bh-disabled
  343. * context. Will take iface_lock and async_lock.
  344. */
  345. static bool efx_mcdi_complete_async(struct efx_mcdi_iface *mcdi, bool timeout)
  346. {
  347. struct efx_nic *efx = mcdi->efx;
  348. struct efx_mcdi_async_param *async;
  349. size_t hdr_len, data_len, err_len;
  350. efx_dword_t *outbuf;
  351. MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0);
  352. int rc;
  353. if (cmpxchg(&mcdi->state,
  354. MCDI_STATE_RUNNING_ASYNC, MCDI_STATE_COMPLETED) !=
  355. MCDI_STATE_RUNNING_ASYNC)
  356. return false;
  357. spin_lock(&mcdi->iface_lock);
  358. if (timeout) {
  359. /* Ensure that if the completion event arrives later,
  360. * the seqno check in efx_mcdi_ev_cpl() will fail
  361. */
  362. ++mcdi->seqno;
  363. ++mcdi->credits;
  364. rc = -ETIMEDOUT;
  365. hdr_len = 0;
  366. data_len = 0;
  367. } else {
  368. rc = mcdi->resprc;
  369. hdr_len = mcdi->resp_hdr_len;
  370. data_len = mcdi->resp_data_len;
  371. }
  372. spin_unlock(&mcdi->iface_lock);
  373. /* Stop the timer. In case the timer function is running, we
  374. * must wait for it to return so that there is no possibility
  375. * of it aborting the next request.
  376. */
  377. if (!timeout)
  378. del_timer_sync(&mcdi->async_timer);
  379. spin_lock(&mcdi->async_lock);
  380. async = list_first_entry(&mcdi->async_list,
  381. struct efx_mcdi_async_param, list);
  382. list_del(&async->list);
  383. spin_unlock(&mcdi->async_lock);
  384. outbuf = (efx_dword_t *)(async + 1);
  385. efx->type->mcdi_read_response(efx, outbuf, hdr_len,
  386. min(async->outlen, data_len));
  387. if (!timeout && rc && !async->quiet) {
  388. err_len = min(sizeof(errbuf), data_len);
  389. efx->type->mcdi_read_response(efx, errbuf, hdr_len,
  390. sizeof(errbuf));
  391. efx_mcdi_display_error(efx, async->cmd, async->inlen, errbuf,
  392. err_len, rc);
  393. }
  394. async->complete(efx, async->cookie, rc, outbuf, data_len);
  395. kfree(async);
  396. efx_mcdi_release(mcdi);
  397. return true;
  398. }
  399. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  400. unsigned int datalen, unsigned int mcdi_err)
  401. {
  402. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  403. bool wake = false;
  404. spin_lock(&mcdi->iface_lock);
  405. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  406. if (mcdi->credits)
  407. /* The request has been cancelled */
  408. --mcdi->credits;
  409. else
  410. netif_err(efx, hw, efx->net_dev,
  411. "MC response mismatch tx seq 0x%x rx "
  412. "seq 0x%x\n", seqno, mcdi->seqno);
  413. } else {
  414. if (efx->type->mcdi_max_ver >= 2) {
  415. /* MCDI v2 responses don't fit in an event */
  416. efx_mcdi_read_response_header(efx);
  417. } else {
  418. mcdi->resprc = efx_mcdi_errno(mcdi_err);
  419. mcdi->resp_hdr_len = 4;
  420. mcdi->resp_data_len = datalen;
  421. }
  422. wake = true;
  423. }
  424. spin_unlock(&mcdi->iface_lock);
  425. if (wake) {
  426. if (!efx_mcdi_complete_async(mcdi, false))
  427. (void) efx_mcdi_complete_sync(mcdi);
  428. /* If the interface isn't RUNNING_ASYNC or
  429. * RUNNING_SYNC then we've received a duplicate
  430. * completion after we've already transitioned back to
  431. * QUIESCENT. [A subsequent invocation would increment
  432. * seqno, so would have failed the seqno check].
  433. */
  434. }
  435. }
  436. static void efx_mcdi_timeout_async(unsigned long context)
  437. {
  438. struct efx_mcdi_iface *mcdi = (struct efx_mcdi_iface *)context;
  439. efx_mcdi_complete_async(mcdi, true);
  440. }
  441. static int
  442. efx_mcdi_check_supported(struct efx_nic *efx, unsigned int cmd, size_t inlen)
  443. {
  444. if (efx->type->mcdi_max_ver < 0 ||
  445. (efx->type->mcdi_max_ver < 2 &&
  446. cmd > MC_CMD_CMD_SPACE_ESCAPE_7))
  447. return -EINVAL;
  448. if (inlen > MCDI_CTL_SDU_LEN_MAX_V2 ||
  449. (efx->type->mcdi_max_ver < 2 &&
  450. inlen > MCDI_CTL_SDU_LEN_MAX_V1))
  451. return -EMSGSIZE;
  452. return 0;
  453. }
  454. static int _efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
  455. efx_dword_t *outbuf, size_t outlen,
  456. size_t *outlen_actual, bool quiet)
  457. {
  458. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  459. MCDI_DECLARE_BUF_OUT_OR_ERR(errbuf, 0);
  460. int rc;
  461. if (mcdi->mode == MCDI_MODE_POLL)
  462. rc = efx_mcdi_poll(efx);
  463. else
  464. rc = efx_mcdi_await_completion(efx);
  465. if (rc != 0) {
  466. netif_err(efx, hw, efx->net_dev,
  467. "MC command 0x%x inlen %d mode %d timed out\n",
  468. cmd, (int)inlen, mcdi->mode);
  469. if (mcdi->mode == MCDI_MODE_EVENTS && efx_mcdi_poll_once(efx)) {
  470. netif_err(efx, hw, efx->net_dev,
  471. "MCDI request was completed without an event\n");
  472. rc = 0;
  473. }
  474. efx_mcdi_abandon(efx);
  475. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  476. * and completing a request we've just cancelled, by ensuring
  477. * that the seqno check therein fails.
  478. */
  479. spin_lock_bh(&mcdi->iface_lock);
  480. ++mcdi->seqno;
  481. ++mcdi->credits;
  482. spin_unlock_bh(&mcdi->iface_lock);
  483. }
  484. if (rc != 0) {
  485. if (outlen_actual)
  486. *outlen_actual = 0;
  487. } else {
  488. size_t hdr_len, data_len, err_len;
  489. /* At the very least we need a memory barrier here to ensure
  490. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  491. * a spurious efx_mcdi_ev_cpl() running concurrently by
  492. * acquiring the iface_lock. */
  493. spin_lock_bh(&mcdi->iface_lock);
  494. rc = mcdi->resprc;
  495. hdr_len = mcdi->resp_hdr_len;
  496. data_len = mcdi->resp_data_len;
  497. err_len = min(sizeof(errbuf), data_len);
  498. spin_unlock_bh(&mcdi->iface_lock);
  499. BUG_ON(rc > 0);
  500. efx->type->mcdi_read_response(efx, outbuf, hdr_len,
  501. min(outlen, data_len));
  502. if (outlen_actual)
  503. *outlen_actual = data_len;
  504. efx->type->mcdi_read_response(efx, errbuf, hdr_len, err_len);
  505. if (cmd == MC_CMD_REBOOT && rc == -EIO) {
  506. /* Don't reset if MC_CMD_REBOOT returns EIO */
  507. } else if (rc == -EIO || rc == -EINTR) {
  508. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  509. -rc);
  510. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  511. } else if (rc && !quiet) {
  512. efx_mcdi_display_error(efx, cmd, inlen, errbuf, err_len,
  513. rc);
  514. }
  515. if (rc == -EIO || rc == -EINTR) {
  516. msleep(MCDI_STATUS_SLEEP_MS);
  517. efx_mcdi_poll_reboot(efx);
  518. mcdi->new_epoch = true;
  519. }
  520. }
  521. efx_mcdi_release(mcdi);
  522. return rc;
  523. }
  524. static int _efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  525. const efx_dword_t *inbuf, size_t inlen,
  526. efx_dword_t *outbuf, size_t outlen,
  527. size_t *outlen_actual, bool quiet)
  528. {
  529. int rc;
  530. rc = efx_mcdi_rpc_start(efx, cmd, inbuf, inlen);
  531. if (rc) {
  532. if (outlen_actual)
  533. *outlen_actual = 0;
  534. return rc;
  535. }
  536. return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
  537. outlen_actual, quiet);
  538. }
  539. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  540. const efx_dword_t *inbuf, size_t inlen,
  541. efx_dword_t *outbuf, size_t outlen,
  542. size_t *outlen_actual)
  543. {
  544. return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen,
  545. outlen_actual, false);
  546. }
  547. /* Normally, on receiving an error code in the MCDI response,
  548. * efx_mcdi_rpc will log an error message containing (among other
  549. * things) the raw error code, by means of efx_mcdi_display_error.
  550. * This _quiet version suppresses that; if the caller wishes to log
  551. * the error conditionally on the return code, it should call this
  552. * function and is then responsible for calling efx_mcdi_display_error
  553. * as needed.
  554. */
  555. int efx_mcdi_rpc_quiet(struct efx_nic *efx, unsigned cmd,
  556. const efx_dword_t *inbuf, size_t inlen,
  557. efx_dword_t *outbuf, size_t outlen,
  558. size_t *outlen_actual)
  559. {
  560. return _efx_mcdi_rpc(efx, cmd, inbuf, inlen, outbuf, outlen,
  561. outlen_actual, true);
  562. }
  563. int efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd,
  564. const efx_dword_t *inbuf, size_t inlen)
  565. {
  566. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  567. int rc;
  568. rc = efx_mcdi_check_supported(efx, cmd, inlen);
  569. if (rc)
  570. return rc;
  571. if (efx->mc_bist_for_other_fn)
  572. return -ENETDOWN;
  573. if (mcdi->mode == MCDI_MODE_FAIL)
  574. return -ENETDOWN;
  575. efx_mcdi_acquire_sync(mcdi);
  576. efx_mcdi_send_request(efx, cmd, inbuf, inlen);
  577. return 0;
  578. }
  579. static int _efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd,
  580. const efx_dword_t *inbuf, size_t inlen,
  581. size_t outlen,
  582. efx_mcdi_async_completer *complete,
  583. unsigned long cookie, bool quiet)
  584. {
  585. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  586. struct efx_mcdi_async_param *async;
  587. int rc;
  588. rc = efx_mcdi_check_supported(efx, cmd, inlen);
  589. if (rc)
  590. return rc;
  591. if (efx->mc_bist_for_other_fn)
  592. return -ENETDOWN;
  593. async = kmalloc(sizeof(*async) + ALIGN(max(inlen, outlen), 4),
  594. GFP_ATOMIC);
  595. if (!async)
  596. return -ENOMEM;
  597. async->cmd = cmd;
  598. async->inlen = inlen;
  599. async->outlen = outlen;
  600. async->quiet = quiet;
  601. async->complete = complete;
  602. async->cookie = cookie;
  603. memcpy(async + 1, inbuf, inlen);
  604. spin_lock_bh(&mcdi->async_lock);
  605. if (mcdi->mode == MCDI_MODE_EVENTS) {
  606. list_add_tail(&async->list, &mcdi->async_list);
  607. /* If this is at the front of the queue, try to start it
  608. * immediately
  609. */
  610. if (mcdi->async_list.next == &async->list &&
  611. efx_mcdi_acquire_async(mcdi)) {
  612. efx_mcdi_send_request(efx, cmd, inbuf, inlen);
  613. mod_timer(&mcdi->async_timer,
  614. jiffies + MCDI_RPC_TIMEOUT);
  615. }
  616. } else {
  617. kfree(async);
  618. rc = -ENETDOWN;
  619. }
  620. spin_unlock_bh(&mcdi->async_lock);
  621. return rc;
  622. }
  623. /**
  624. * efx_mcdi_rpc_async - Schedule an MCDI command to run asynchronously
  625. * @efx: NIC through which to issue the command
  626. * @cmd: Command type number
  627. * @inbuf: Command parameters
  628. * @inlen: Length of command parameters, in bytes
  629. * @outlen: Length to allocate for response buffer, in bytes
  630. * @complete: Function to be called on completion or cancellation.
  631. * @cookie: Arbitrary value to be passed to @complete.
  632. *
  633. * This function does not sleep and therefore may be called in atomic
  634. * context. It will fail if event queues are disabled or if MCDI
  635. * event completions have been disabled due to an error.
  636. *
  637. * If it succeeds, the @complete function will be called exactly once
  638. * in atomic context, when one of the following occurs:
  639. * (a) the completion event is received (in NAPI context)
  640. * (b) event queues are disabled (in the process that disables them)
  641. * (c) the request times-out (in timer context)
  642. */
  643. int
  644. efx_mcdi_rpc_async(struct efx_nic *efx, unsigned int cmd,
  645. const efx_dword_t *inbuf, size_t inlen, size_t outlen,
  646. efx_mcdi_async_completer *complete, unsigned long cookie)
  647. {
  648. return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete,
  649. cookie, false);
  650. }
  651. int efx_mcdi_rpc_async_quiet(struct efx_nic *efx, unsigned int cmd,
  652. const efx_dword_t *inbuf, size_t inlen,
  653. size_t outlen, efx_mcdi_async_completer *complete,
  654. unsigned long cookie)
  655. {
  656. return _efx_mcdi_rpc_async(efx, cmd, inbuf, inlen, outlen, complete,
  657. cookie, true);
  658. }
  659. int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
  660. efx_dword_t *outbuf, size_t outlen,
  661. size_t *outlen_actual)
  662. {
  663. return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
  664. outlen_actual, false);
  665. }
  666. int efx_mcdi_rpc_finish_quiet(struct efx_nic *efx, unsigned cmd, size_t inlen,
  667. efx_dword_t *outbuf, size_t outlen,
  668. size_t *outlen_actual)
  669. {
  670. return _efx_mcdi_rpc_finish(efx, cmd, inlen, outbuf, outlen,
  671. outlen_actual, true);
  672. }
  673. void efx_mcdi_display_error(struct efx_nic *efx, unsigned cmd,
  674. size_t inlen, efx_dword_t *outbuf,
  675. size_t outlen, int rc)
  676. {
  677. int code = 0, err_arg = 0;
  678. if (outlen >= MC_CMD_ERR_CODE_OFST + 4)
  679. code = MCDI_DWORD(outbuf, ERR_CODE);
  680. if (outlen >= MC_CMD_ERR_ARG_OFST + 4)
  681. err_arg = MCDI_DWORD(outbuf, ERR_ARG);
  682. netif_err(efx, hw, efx->net_dev,
  683. "MC command 0x%x inlen %d failed rc=%d (raw=%d) arg=%d\n",
  684. cmd, (int)inlen, rc, code, err_arg);
  685. }
  686. /* Switch to polled MCDI completions. This can be called in various
  687. * error conditions with various locks held, so it must be lockless.
  688. * Caller is responsible for flushing asynchronous requests later.
  689. */
  690. void efx_mcdi_mode_poll(struct efx_nic *efx)
  691. {
  692. struct efx_mcdi_iface *mcdi;
  693. if (!efx->mcdi)
  694. return;
  695. mcdi = efx_mcdi(efx);
  696. /* If already in polling mode, nothing to do.
  697. * If in fail-fast state, don't switch to polled completion.
  698. * FLR recovery will do that later.
  699. */
  700. if (mcdi->mode == MCDI_MODE_POLL || mcdi->mode == MCDI_MODE_FAIL)
  701. return;
  702. /* We can switch from event completion to polled completion, because
  703. * mcdi requests are always completed in shared memory. We do this by
  704. * switching the mode to POLL'd then completing the request.
  705. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  706. *
  707. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  708. * which efx_mcdi_complete_sync() provides for us.
  709. */
  710. mcdi->mode = MCDI_MODE_POLL;
  711. efx_mcdi_complete_sync(mcdi);
  712. }
  713. /* Flush any running or queued asynchronous requests, after event processing
  714. * is stopped
  715. */
  716. void efx_mcdi_flush_async(struct efx_nic *efx)
  717. {
  718. struct efx_mcdi_async_param *async, *next;
  719. struct efx_mcdi_iface *mcdi;
  720. if (!efx->mcdi)
  721. return;
  722. mcdi = efx_mcdi(efx);
  723. /* We must be in poll or fail mode so no more requests can be queued */
  724. BUG_ON(mcdi->mode == MCDI_MODE_EVENTS);
  725. del_timer_sync(&mcdi->async_timer);
  726. /* If a request is still running, make sure we give the MC
  727. * time to complete it so that the response won't overwrite our
  728. * next request.
  729. */
  730. if (mcdi->state == MCDI_STATE_RUNNING_ASYNC) {
  731. efx_mcdi_poll(efx);
  732. mcdi->state = MCDI_STATE_QUIESCENT;
  733. }
  734. /* Nothing else will access the async list now, so it is safe
  735. * to walk it without holding async_lock. If we hold it while
  736. * calling a completer then lockdep may warn that we have
  737. * acquired locks in the wrong order.
  738. */
  739. list_for_each_entry_safe(async, next, &mcdi->async_list, list) {
  740. async->complete(efx, async->cookie, -ENETDOWN, NULL, 0);
  741. list_del(&async->list);
  742. kfree(async);
  743. }
  744. }
  745. void efx_mcdi_mode_event(struct efx_nic *efx)
  746. {
  747. struct efx_mcdi_iface *mcdi;
  748. if (!efx->mcdi)
  749. return;
  750. mcdi = efx_mcdi(efx);
  751. /* If already in event completion mode, nothing to do.
  752. * If in fail-fast state, don't switch to event completion. FLR
  753. * recovery will do that later.
  754. */
  755. if (mcdi->mode == MCDI_MODE_EVENTS || mcdi->mode == MCDI_MODE_FAIL)
  756. return;
  757. /* We can't switch from polled to event completion in the middle of a
  758. * request, because the completion method is specified in the request.
  759. * So acquire the interface to serialise the requestors. We don't need
  760. * to acquire the iface_lock to change the mode here, but we do need a
  761. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  762. * efx_mcdi_acquire() provides.
  763. */
  764. efx_mcdi_acquire_sync(mcdi);
  765. mcdi->mode = MCDI_MODE_EVENTS;
  766. efx_mcdi_release(mcdi);
  767. }
  768. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  769. {
  770. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  771. /* If there is an outstanding MCDI request, it has been terminated
  772. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  773. * in polled mode, then do nothing because the MC reboot handler will
  774. * set the header correctly. However, if the mcdi interface is waiting
  775. * for a CMDDONE event it won't receive it [and since all MCDI events
  776. * are sent to the same queue, we can't be racing with
  777. * efx_mcdi_ev_cpl()]
  778. *
  779. * If there is an outstanding asynchronous request, we can't
  780. * complete it now (efx_mcdi_complete() would deadlock). The
  781. * reset process will take care of this.
  782. *
  783. * There's a race here with efx_mcdi_send_request(), because
  784. * we might receive a REBOOT event *before* the request has
  785. * been copied out. In polled mode (during startup) this is
  786. * irrelevant, because efx_mcdi_complete_sync() is ignored. In
  787. * event mode, this condition is just an edge-case of
  788. * receiving a REBOOT event after posting the MCDI
  789. * request. Did the mc reboot before or after the copyout? The
  790. * best we can do always is just return failure.
  791. */
  792. spin_lock(&mcdi->iface_lock);
  793. if (efx_mcdi_complete_sync(mcdi)) {
  794. if (mcdi->mode == MCDI_MODE_EVENTS) {
  795. mcdi->resprc = rc;
  796. mcdi->resp_hdr_len = 0;
  797. mcdi->resp_data_len = 0;
  798. ++mcdi->credits;
  799. }
  800. } else {
  801. int count;
  802. /* Consume the status word since efx_mcdi_rpc_finish() won't */
  803. for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
  804. if (efx_mcdi_poll_reboot(efx))
  805. break;
  806. udelay(MCDI_STATUS_DELAY_US);
  807. }
  808. mcdi->new_epoch = true;
  809. /* Nobody was waiting for an MCDI request, so trigger a reset */
  810. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  811. }
  812. spin_unlock(&mcdi->iface_lock);
  813. }
  814. /* The MC is going down in to BIST mode. set the BIST flag to block
  815. * new MCDI, cancel any outstanding MCDI and and schedule a BIST-type reset
  816. * (which doesn't actually execute a reset, it waits for the controlling
  817. * function to reset it).
  818. */
  819. static void efx_mcdi_ev_bist(struct efx_nic *efx)
  820. {
  821. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  822. spin_lock(&mcdi->iface_lock);
  823. efx->mc_bist_for_other_fn = true;
  824. if (efx_mcdi_complete_sync(mcdi)) {
  825. if (mcdi->mode == MCDI_MODE_EVENTS) {
  826. mcdi->resprc = -EIO;
  827. mcdi->resp_hdr_len = 0;
  828. mcdi->resp_data_len = 0;
  829. ++mcdi->credits;
  830. }
  831. }
  832. mcdi->new_epoch = true;
  833. efx_schedule_reset(efx, RESET_TYPE_MC_BIST);
  834. spin_unlock(&mcdi->iface_lock);
  835. }
  836. /* MCDI timeouts seen, so make all MCDI calls fail-fast and issue an FLR to try
  837. * to recover.
  838. */
  839. static void efx_mcdi_abandon(struct efx_nic *efx)
  840. {
  841. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  842. if (xchg(&mcdi->mode, MCDI_MODE_FAIL) == MCDI_MODE_FAIL)
  843. return; /* it had already been done */
  844. netif_dbg(efx, hw, efx->net_dev, "MCDI is timing out; trying to recover\n");
  845. efx_schedule_reset(efx, RESET_TYPE_MCDI_TIMEOUT);
  846. }
  847. /* Called from falcon_process_eventq for MCDI events */
  848. void efx_mcdi_process_event(struct efx_channel *channel,
  849. efx_qword_t *event)
  850. {
  851. struct efx_nic *efx = channel->efx;
  852. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  853. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  854. switch (code) {
  855. case MCDI_EVENT_CODE_BADSSERT:
  856. netif_err(efx, hw, efx->net_dev,
  857. "MC watchdog or assertion failure at 0x%x\n", data);
  858. efx_mcdi_ev_death(efx, -EINTR);
  859. break;
  860. case MCDI_EVENT_CODE_PMNOTICE:
  861. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  862. break;
  863. case MCDI_EVENT_CODE_CMDDONE:
  864. efx_mcdi_ev_cpl(efx,
  865. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  866. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  867. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  868. break;
  869. case MCDI_EVENT_CODE_LINKCHANGE:
  870. efx_mcdi_process_link_change(efx, event);
  871. break;
  872. case MCDI_EVENT_CODE_SENSOREVT:
  873. efx_mcdi_sensor_event(efx, event);
  874. break;
  875. case MCDI_EVENT_CODE_SCHEDERR:
  876. netif_dbg(efx, hw, efx->net_dev,
  877. "MC Scheduler alert (0x%x)\n", data);
  878. break;
  879. case MCDI_EVENT_CODE_REBOOT:
  880. case MCDI_EVENT_CODE_MC_REBOOT:
  881. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  882. efx_mcdi_ev_death(efx, -EIO);
  883. break;
  884. case MCDI_EVENT_CODE_MC_BIST:
  885. netif_info(efx, hw, efx->net_dev, "MC entered BIST mode\n");
  886. efx_mcdi_ev_bist(efx);
  887. break;
  888. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  889. /* MAC stats are gather lazily. We can ignore this. */
  890. break;
  891. case MCDI_EVENT_CODE_FLR:
  892. if (efx->type->sriov_flr)
  893. efx->type->sriov_flr(efx,
  894. MCDI_EVENT_FIELD(*event, FLR_VF));
  895. break;
  896. case MCDI_EVENT_CODE_PTP_RX:
  897. case MCDI_EVENT_CODE_PTP_FAULT:
  898. case MCDI_EVENT_CODE_PTP_PPS:
  899. efx_ptp_event(efx, event);
  900. break;
  901. case MCDI_EVENT_CODE_PTP_TIME:
  902. efx_time_sync_event(channel, event);
  903. break;
  904. case MCDI_EVENT_CODE_TX_FLUSH:
  905. case MCDI_EVENT_CODE_RX_FLUSH:
  906. /* Two flush events will be sent: one to the same event
  907. * queue as completions, and one to event queue 0.
  908. * In the latter case the {RX,TX}_FLUSH_TO_DRIVER
  909. * flag will be set, and we should ignore the event
  910. * because we want to wait for all completions.
  911. */
  912. BUILD_BUG_ON(MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN !=
  913. MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN);
  914. if (!MCDI_EVENT_FIELD(*event, TX_FLUSH_TO_DRIVER))
  915. efx_ef10_handle_drain_event(efx);
  916. break;
  917. case MCDI_EVENT_CODE_TX_ERR:
  918. case MCDI_EVENT_CODE_RX_ERR:
  919. netif_err(efx, hw, efx->net_dev,
  920. "%s DMA error (event: "EFX_QWORD_FMT")\n",
  921. code == MCDI_EVENT_CODE_TX_ERR ? "TX" : "RX",
  922. EFX_QWORD_VAL(*event));
  923. efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
  924. break;
  925. default:
  926. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  927. code);
  928. }
  929. }
  930. /**************************************************************************
  931. *
  932. * Specific request functions
  933. *
  934. **************************************************************************
  935. */
  936. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  937. {
  938. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_VERSION_OUT_LEN);
  939. size_t outlength;
  940. const __le16 *ver_words;
  941. size_t offset;
  942. int rc;
  943. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  944. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  945. outbuf, sizeof(outbuf), &outlength);
  946. if (rc)
  947. goto fail;
  948. if (outlength < MC_CMD_GET_VERSION_OUT_LEN) {
  949. rc = -EIO;
  950. goto fail;
  951. }
  952. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  953. offset = snprintf(buf, len, "%u.%u.%u.%u",
  954. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  955. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  956. /* EF10 may have multiple datapath firmware variants within a
  957. * single version. Report which variants are running.
  958. */
  959. if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) {
  960. struct efx_ef10_nic_data *nic_data = efx->nic_data;
  961. offset += snprintf(buf + offset, len - offset, " rx%x tx%x",
  962. nic_data->rx_dpcpu_fw_id,
  963. nic_data->tx_dpcpu_fw_id);
  964. /* It's theoretically possible for the string to exceed 31
  965. * characters, though in practice the first three version
  966. * components are short enough that this doesn't happen.
  967. */
  968. if (WARN_ON(offset >= len))
  969. buf[0] = 0;
  970. }
  971. return;
  972. fail:
  973. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  974. buf[0] = 0;
  975. }
  976. static int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  977. bool *was_attached)
  978. {
  979. MCDI_DECLARE_BUF(inbuf, MC_CMD_DRV_ATTACH_IN_LEN);
  980. MCDI_DECLARE_BUF(outbuf, MC_CMD_DRV_ATTACH_EXT_OUT_LEN);
  981. size_t outlen;
  982. int rc;
  983. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  984. driver_operating ? 1 : 0);
  985. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  986. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_LOW_LATENCY);
  987. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  988. outbuf, sizeof(outbuf), &outlen);
  989. if (rc)
  990. goto fail;
  991. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  992. rc = -EIO;
  993. goto fail;
  994. }
  995. if (driver_operating) {
  996. if (outlen >= MC_CMD_DRV_ATTACH_EXT_OUT_LEN) {
  997. efx->mcdi->fn_flags =
  998. MCDI_DWORD(outbuf,
  999. DRV_ATTACH_EXT_OUT_FUNC_FLAGS);
  1000. } else {
  1001. /* Synthesise flags for Siena */
  1002. efx->mcdi->fn_flags =
  1003. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
  1004. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED |
  1005. (efx_port_num(efx) == 0) <<
  1006. MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY;
  1007. }
  1008. }
  1009. /* We currently assume we have control of the external link
  1010. * and are completely trusted by firmware. Abort probing
  1011. * if that's not true for this function.
  1012. */
  1013. if (driver_operating &&
  1014. (efx->mcdi->fn_flags &
  1015. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
  1016. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) !=
  1017. (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL |
  1018. 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) {
  1019. netif_err(efx, probe, efx->net_dev,
  1020. "This driver version only supports one function per port\n");
  1021. return -ENODEV;
  1022. }
  1023. if (was_attached != NULL)
  1024. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  1025. return 0;
  1026. fail:
  1027. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1028. return rc;
  1029. }
  1030. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  1031. u16 *fw_subtype_list, u32 *capabilities)
  1032. {
  1033. MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_BOARD_CFG_OUT_LENMAX);
  1034. size_t outlen, i;
  1035. int port_num = efx_port_num(efx);
  1036. int rc;
  1037. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  1038. /* we need __aligned(2) for ether_addr_copy */
  1039. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST & 1);
  1040. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST & 1);
  1041. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  1042. outbuf, sizeof(outbuf), &outlen);
  1043. if (rc)
  1044. goto fail;
  1045. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
  1046. rc = -EIO;
  1047. goto fail;
  1048. }
  1049. if (mac_address)
  1050. ether_addr_copy(mac_address,
  1051. port_num ?
  1052. MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1) :
  1053. MCDI_PTR(outbuf, GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0));
  1054. if (fw_subtype_list) {
  1055. for (i = 0;
  1056. i < MCDI_VAR_ARRAY_LEN(outlen,
  1057. GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST);
  1058. i++)
  1059. fw_subtype_list[i] = MCDI_ARRAY_WORD(
  1060. outbuf, GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST, i);
  1061. for (; i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM; i++)
  1062. fw_subtype_list[i] = 0;
  1063. }
  1064. if (capabilities) {
  1065. if (port_num)
  1066. *capabilities = MCDI_DWORD(outbuf,
  1067. GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
  1068. else
  1069. *capabilities = MCDI_DWORD(outbuf,
  1070. GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
  1071. }
  1072. return 0;
  1073. fail:
  1074. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  1075. __func__, rc, (int)outlen);
  1076. return rc;
  1077. }
  1078. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  1079. {
  1080. MCDI_DECLARE_BUF(inbuf, MC_CMD_LOG_CTRL_IN_LEN);
  1081. u32 dest = 0;
  1082. int rc;
  1083. if (uart)
  1084. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  1085. if (evq)
  1086. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  1087. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  1088. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  1089. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  1090. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  1091. NULL, 0, NULL);
  1092. return rc;
  1093. }
  1094. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  1095. {
  1096. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TYPES_OUT_LEN);
  1097. size_t outlen;
  1098. int rc;
  1099. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  1100. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  1101. outbuf, sizeof(outbuf), &outlen);
  1102. if (rc)
  1103. goto fail;
  1104. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  1105. rc = -EIO;
  1106. goto fail;
  1107. }
  1108. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  1109. return 0;
  1110. fail:
  1111. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  1112. __func__, rc);
  1113. return rc;
  1114. }
  1115. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  1116. size_t *size_out, size_t *erase_size_out,
  1117. bool *protected_out)
  1118. {
  1119. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_INFO_IN_LEN);
  1120. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_INFO_OUT_LEN);
  1121. size_t outlen;
  1122. int rc;
  1123. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  1124. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  1125. outbuf, sizeof(outbuf), &outlen);
  1126. if (rc)
  1127. goto fail;
  1128. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  1129. rc = -EIO;
  1130. goto fail;
  1131. }
  1132. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  1133. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  1134. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  1135. (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN));
  1136. return 0;
  1137. fail:
  1138. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1139. return rc;
  1140. }
  1141. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  1142. {
  1143. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_TEST_IN_LEN);
  1144. MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_TEST_OUT_LEN);
  1145. int rc;
  1146. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  1147. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  1148. outbuf, sizeof(outbuf), NULL);
  1149. if (rc)
  1150. return rc;
  1151. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  1152. case MC_CMD_NVRAM_TEST_PASS:
  1153. case MC_CMD_NVRAM_TEST_NOTSUPP:
  1154. return 0;
  1155. default:
  1156. return -EIO;
  1157. }
  1158. }
  1159. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  1160. {
  1161. u32 nvram_types;
  1162. unsigned int type;
  1163. int rc;
  1164. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  1165. if (rc)
  1166. goto fail1;
  1167. type = 0;
  1168. while (nvram_types != 0) {
  1169. if (nvram_types & 1) {
  1170. rc = efx_mcdi_nvram_test(efx, type);
  1171. if (rc)
  1172. goto fail2;
  1173. }
  1174. type++;
  1175. nvram_types >>= 1;
  1176. }
  1177. return 0;
  1178. fail2:
  1179. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  1180. __func__, type);
  1181. fail1:
  1182. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1183. return rc;
  1184. }
  1185. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  1186. {
  1187. MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_ASSERTS_IN_LEN);
  1188. MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, MC_CMD_GET_ASSERTS_OUT_LEN);
  1189. unsigned int flags, index;
  1190. const char *reason;
  1191. size_t outlen;
  1192. int retry;
  1193. int rc;
  1194. /* Attempt to read any stored assertion state before we reboot
  1195. * the mcfw out of the assertion handler. Retry twice, once
  1196. * because a boot-time assertion might cause this command to fail
  1197. * with EINTR. And once again because GET_ASSERTS can race with
  1198. * MC_CMD_REBOOT running on the other port. */
  1199. retry = 2;
  1200. do {
  1201. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  1202. rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_ASSERTS,
  1203. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  1204. outbuf, sizeof(outbuf), &outlen);
  1205. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  1206. if (rc) {
  1207. efx_mcdi_display_error(efx, MC_CMD_GET_ASSERTS,
  1208. MC_CMD_GET_ASSERTS_IN_LEN, outbuf,
  1209. outlen, rc);
  1210. return rc;
  1211. }
  1212. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  1213. return -EIO;
  1214. /* Print out any recorded assertion state */
  1215. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  1216. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  1217. return 0;
  1218. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  1219. ? "system-level assertion"
  1220. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  1221. ? "thread-level assertion"
  1222. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  1223. ? "watchdog reset"
  1224. : "unknown assertion";
  1225. netif_err(efx, hw, efx->net_dev,
  1226. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  1227. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  1228. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  1229. /* Print out the registers */
  1230. for (index = 0;
  1231. index < MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM;
  1232. index++)
  1233. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n",
  1234. 1 + index,
  1235. MCDI_ARRAY_DWORD(outbuf, GET_ASSERTS_OUT_GP_REGS_OFFS,
  1236. index));
  1237. return 0;
  1238. }
  1239. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  1240. {
  1241. MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
  1242. /* If the MC is running debug firmware, it might now be
  1243. * waiting for a debugger to attach, but we just want it to
  1244. * reboot. We set a flag that makes the command a no-op if it
  1245. * has already done so. We don't know what return code to
  1246. * expect (0 or -EIO), so ignore it.
  1247. */
  1248. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  1249. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  1250. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  1251. (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  1252. NULL, 0, NULL);
  1253. }
  1254. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  1255. {
  1256. int rc;
  1257. rc = efx_mcdi_read_assertion(efx);
  1258. if (rc)
  1259. return rc;
  1260. efx_mcdi_exit_assertion(efx);
  1261. return 0;
  1262. }
  1263. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  1264. {
  1265. MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_ID_LED_IN_LEN);
  1266. int rc;
  1267. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  1268. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  1269. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  1270. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  1271. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  1272. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  1273. NULL, 0, NULL);
  1274. }
  1275. static int efx_mcdi_reset_func(struct efx_nic *efx)
  1276. {
  1277. MCDI_DECLARE_BUF(inbuf, MC_CMD_ENTITY_RESET_IN_LEN);
  1278. int rc;
  1279. BUILD_BUG_ON(MC_CMD_ENTITY_RESET_OUT_LEN != 0);
  1280. MCDI_POPULATE_DWORD_1(inbuf, ENTITY_RESET_IN_FLAG,
  1281. ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
  1282. rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, inbuf, sizeof(inbuf),
  1283. NULL, 0, NULL);
  1284. return rc;
  1285. }
  1286. static int efx_mcdi_reset_mc(struct efx_nic *efx)
  1287. {
  1288. MCDI_DECLARE_BUF(inbuf, MC_CMD_REBOOT_IN_LEN);
  1289. int rc;
  1290. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  1291. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  1292. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  1293. NULL, 0, NULL);
  1294. /* White is black, and up is down */
  1295. if (rc == -EIO)
  1296. return 0;
  1297. if (rc == 0)
  1298. rc = -EIO;
  1299. return rc;
  1300. }
  1301. enum reset_type efx_mcdi_map_reset_reason(enum reset_type reason)
  1302. {
  1303. return RESET_TYPE_RECOVER_OR_ALL;
  1304. }
  1305. int efx_mcdi_reset(struct efx_nic *efx, enum reset_type method)
  1306. {
  1307. int rc;
  1308. /* If MCDI is down, we can't handle_assertion */
  1309. if (method == RESET_TYPE_MCDI_TIMEOUT) {
  1310. rc = pci_reset_function(efx->pci_dev);
  1311. if (rc)
  1312. return rc;
  1313. /* Re-enable polled MCDI completion */
  1314. if (efx->mcdi) {
  1315. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  1316. mcdi->mode = MCDI_MODE_POLL;
  1317. }
  1318. return 0;
  1319. }
  1320. /* Recover from a failed assertion pre-reset */
  1321. rc = efx_mcdi_handle_assertion(efx);
  1322. if (rc)
  1323. return rc;
  1324. if (method == RESET_TYPE_WORLD)
  1325. return efx_mcdi_reset_mc(efx);
  1326. else
  1327. return efx_mcdi_reset_func(efx);
  1328. }
  1329. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  1330. const u8 *mac, int *id_out)
  1331. {
  1332. MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_SET_IN_LEN);
  1333. MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_SET_OUT_LEN);
  1334. size_t outlen;
  1335. int rc;
  1336. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  1337. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  1338. MC_CMD_FILTER_MODE_SIMPLE);
  1339. ether_addr_copy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac);
  1340. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  1341. outbuf, sizeof(outbuf), &outlen);
  1342. if (rc)
  1343. goto fail;
  1344. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  1345. rc = -EIO;
  1346. goto fail;
  1347. }
  1348. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  1349. return 0;
  1350. fail:
  1351. *id_out = -1;
  1352. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1353. return rc;
  1354. }
  1355. int
  1356. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  1357. {
  1358. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  1359. }
  1360. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  1361. {
  1362. MCDI_DECLARE_BUF(outbuf, MC_CMD_WOL_FILTER_GET_OUT_LEN);
  1363. size_t outlen;
  1364. int rc;
  1365. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  1366. outbuf, sizeof(outbuf), &outlen);
  1367. if (rc)
  1368. goto fail;
  1369. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  1370. rc = -EIO;
  1371. goto fail;
  1372. }
  1373. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  1374. return 0;
  1375. fail:
  1376. *id_out = -1;
  1377. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1378. return rc;
  1379. }
  1380. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  1381. {
  1382. MCDI_DECLARE_BUF(inbuf, MC_CMD_WOL_FILTER_REMOVE_IN_LEN);
  1383. int rc;
  1384. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  1385. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  1386. NULL, 0, NULL);
  1387. return rc;
  1388. }
  1389. int efx_mcdi_flush_rxqs(struct efx_nic *efx)
  1390. {
  1391. struct efx_channel *channel;
  1392. struct efx_rx_queue *rx_queue;
  1393. MCDI_DECLARE_BUF(inbuf,
  1394. MC_CMD_FLUSH_RX_QUEUES_IN_LEN(EFX_MAX_CHANNELS));
  1395. int rc, count;
  1396. BUILD_BUG_ON(EFX_MAX_CHANNELS >
  1397. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  1398. count = 0;
  1399. efx_for_each_channel(channel, efx) {
  1400. efx_for_each_channel_rx_queue(rx_queue, channel) {
  1401. if (rx_queue->flush_pending) {
  1402. rx_queue->flush_pending = false;
  1403. atomic_dec(&efx->rxq_flush_pending);
  1404. MCDI_SET_ARRAY_DWORD(
  1405. inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
  1406. count, efx_rx_queue_index(rx_queue));
  1407. count++;
  1408. }
  1409. }
  1410. }
  1411. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf,
  1412. MC_CMD_FLUSH_RX_QUEUES_IN_LEN(count), NULL, 0, NULL);
  1413. WARN_ON(rc < 0);
  1414. return rc;
  1415. }
  1416. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  1417. {
  1418. int rc;
  1419. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  1420. return rc;
  1421. }
  1422. int efx_mcdi_set_workaround(struct efx_nic *efx, u32 type, bool enabled)
  1423. {
  1424. MCDI_DECLARE_BUF(inbuf, MC_CMD_WORKAROUND_IN_LEN);
  1425. BUILD_BUG_ON(MC_CMD_WORKAROUND_OUT_LEN != 0);
  1426. MCDI_SET_DWORD(inbuf, WORKAROUND_IN_TYPE, type);
  1427. MCDI_SET_DWORD(inbuf, WORKAROUND_IN_ENABLED, enabled);
  1428. return efx_mcdi_rpc(efx, MC_CMD_WORKAROUND, inbuf, sizeof(inbuf),
  1429. NULL, 0, NULL);
  1430. }
  1431. #ifdef CONFIG_SFC_MTD
  1432. #define EFX_MCDI_NVRAM_LEN_MAX 128
  1433. static int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  1434. {
  1435. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_START_IN_LEN);
  1436. int rc;
  1437. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  1438. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  1439. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  1440. NULL, 0, NULL);
  1441. return rc;
  1442. }
  1443. static int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  1444. loff_t offset, u8 *buffer, size_t length)
  1445. {
  1446. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_READ_IN_LEN);
  1447. MCDI_DECLARE_BUF(outbuf,
  1448. MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX));
  1449. size_t outlen;
  1450. int rc;
  1451. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  1452. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  1453. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  1454. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  1455. outbuf, sizeof(outbuf), &outlen);
  1456. if (rc)
  1457. return rc;
  1458. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  1459. return 0;
  1460. }
  1461. static int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  1462. loff_t offset, const u8 *buffer, size_t length)
  1463. {
  1464. MCDI_DECLARE_BUF(inbuf,
  1465. MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX));
  1466. int rc;
  1467. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  1468. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  1469. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  1470. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  1471. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  1472. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  1473. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  1474. NULL, 0, NULL);
  1475. return rc;
  1476. }
  1477. static int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  1478. loff_t offset, size_t length)
  1479. {
  1480. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_ERASE_IN_LEN);
  1481. int rc;
  1482. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  1483. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  1484. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  1485. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  1486. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  1487. NULL, 0, NULL);
  1488. return rc;
  1489. }
  1490. static int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  1491. {
  1492. MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN);
  1493. int rc;
  1494. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  1495. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  1496. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  1497. NULL, 0, NULL);
  1498. return rc;
  1499. }
  1500. int efx_mcdi_mtd_read(struct mtd_info *mtd, loff_t start,
  1501. size_t len, size_t *retlen, u8 *buffer)
  1502. {
  1503. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1504. struct efx_nic *efx = mtd->priv;
  1505. loff_t offset = start;
  1506. loff_t end = min_t(loff_t, start + len, mtd->size);
  1507. size_t chunk;
  1508. int rc = 0;
  1509. while (offset < end) {
  1510. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  1511. rc = efx_mcdi_nvram_read(efx, part->nvram_type, offset,
  1512. buffer, chunk);
  1513. if (rc)
  1514. goto out;
  1515. offset += chunk;
  1516. buffer += chunk;
  1517. }
  1518. out:
  1519. *retlen = offset - start;
  1520. return rc;
  1521. }
  1522. int efx_mcdi_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
  1523. {
  1524. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1525. struct efx_nic *efx = mtd->priv;
  1526. loff_t offset = start & ~((loff_t)(mtd->erasesize - 1));
  1527. loff_t end = min_t(loff_t, start + len, mtd->size);
  1528. size_t chunk = part->common.mtd.erasesize;
  1529. int rc = 0;
  1530. if (!part->updating) {
  1531. rc = efx_mcdi_nvram_update_start(efx, part->nvram_type);
  1532. if (rc)
  1533. goto out;
  1534. part->updating = true;
  1535. }
  1536. /* The MCDI interface can in fact do multiple erase blocks at once;
  1537. * but erasing may be slow, so we make multiple calls here to avoid
  1538. * tripping the MCDI RPC timeout. */
  1539. while (offset < end) {
  1540. rc = efx_mcdi_nvram_erase(efx, part->nvram_type, offset,
  1541. chunk);
  1542. if (rc)
  1543. goto out;
  1544. offset += chunk;
  1545. }
  1546. out:
  1547. return rc;
  1548. }
  1549. int efx_mcdi_mtd_write(struct mtd_info *mtd, loff_t start,
  1550. size_t len, size_t *retlen, const u8 *buffer)
  1551. {
  1552. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1553. struct efx_nic *efx = mtd->priv;
  1554. loff_t offset = start;
  1555. loff_t end = min_t(loff_t, start + len, mtd->size);
  1556. size_t chunk;
  1557. int rc = 0;
  1558. if (!part->updating) {
  1559. rc = efx_mcdi_nvram_update_start(efx, part->nvram_type);
  1560. if (rc)
  1561. goto out;
  1562. part->updating = true;
  1563. }
  1564. while (offset < end) {
  1565. chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
  1566. rc = efx_mcdi_nvram_write(efx, part->nvram_type, offset,
  1567. buffer, chunk);
  1568. if (rc)
  1569. goto out;
  1570. offset += chunk;
  1571. buffer += chunk;
  1572. }
  1573. out:
  1574. *retlen = offset - start;
  1575. return rc;
  1576. }
  1577. int efx_mcdi_mtd_sync(struct mtd_info *mtd)
  1578. {
  1579. struct efx_mcdi_mtd_partition *part = to_efx_mcdi_mtd_partition(mtd);
  1580. struct efx_nic *efx = mtd->priv;
  1581. int rc = 0;
  1582. if (part->updating) {
  1583. part->updating = false;
  1584. rc = efx_mcdi_nvram_update_finish(efx, part->nvram_type);
  1585. }
  1586. return rc;
  1587. }
  1588. void efx_mcdi_mtd_rename(struct efx_mtd_partition *part)
  1589. {
  1590. struct efx_mcdi_mtd_partition *mcdi_part =
  1591. container_of(part, struct efx_mcdi_mtd_partition, common);
  1592. struct efx_nic *efx = part->mtd.priv;
  1593. snprintf(part->name, sizeof(part->name), "%s %s:%02x",
  1594. efx->name, part->type_name, mcdi_part->fw_subtype);
  1595. }
  1596. #endif /* CONFIG_SFC_MTD */