gpio-pca953x.c 22 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #include <asm/unaligned.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/acpi.h>
  23. #define PCA953X_INPUT 0
  24. #define PCA953X_OUTPUT 1
  25. #define PCA953X_INVERT 2
  26. #define PCA953X_DIRECTION 3
  27. #define REG_ADDR_AI 0x80
  28. #define PCA957X_IN 0
  29. #define PCA957X_INVRT 1
  30. #define PCA957X_BKEN 2
  31. #define PCA957X_PUPD 3
  32. #define PCA957X_CFG 4
  33. #define PCA957X_OUT 5
  34. #define PCA957X_MSK 6
  35. #define PCA957X_INTS 7
  36. #define PCAL953X_IN_LATCH 34
  37. #define PCAL953X_INT_MASK 37
  38. #define PCAL953X_INT_STAT 38
  39. #define PCA_GPIO_MASK 0x00FF
  40. #define PCA_INT 0x0100
  41. #define PCA_PCAL 0x0200
  42. #define PCA953X_TYPE 0x1000
  43. #define PCA957X_TYPE 0x2000
  44. #define PCA_TYPE_MASK 0xF000
  45. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  46. static const struct i2c_device_id pca953x_id[] = {
  47. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9536", 4 | PCA953X_TYPE, },
  51. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  53. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  54. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  55. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  56. { "pca9556", 8 | PCA953X_TYPE, },
  57. { "pca9557", 8 | PCA953X_TYPE, },
  58. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  59. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  60. { "pca9698", 40 | PCA953X_TYPE, },
  61. { "max7310", 8 | PCA953X_TYPE, },
  62. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  63. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  64. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  65. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  66. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  67. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  68. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  69. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  70. { "xra1202", 8 | PCA953X_TYPE },
  71. { }
  72. };
  73. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  74. static const struct acpi_device_id pca953x_acpi_ids[] = {
  75. { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  76. { }
  77. };
  78. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  79. #define MAX_BANK 5
  80. #define BANK_SZ 8
  81. #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
  82. struct pca953x_chip {
  83. unsigned gpio_start;
  84. u8 reg_output[MAX_BANK];
  85. u8 reg_direction[MAX_BANK];
  86. struct mutex i2c_lock;
  87. #ifdef CONFIG_GPIO_PCA953X_IRQ
  88. struct mutex irq_lock;
  89. u8 irq_mask[MAX_BANK];
  90. u8 irq_stat[MAX_BANK];
  91. u8 irq_trig_raise[MAX_BANK];
  92. u8 irq_trig_fall[MAX_BANK];
  93. #endif
  94. struct i2c_client *client;
  95. struct gpio_chip gpio_chip;
  96. const char *const *names;
  97. int chip_type;
  98. unsigned long driver_data;
  99. };
  100. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  101. int off)
  102. {
  103. int ret;
  104. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  105. int offset = off / BANK_SZ;
  106. ret = i2c_smbus_read_byte_data(chip->client,
  107. (reg << bank_shift) + offset);
  108. *val = ret;
  109. if (ret < 0) {
  110. dev_err(&chip->client->dev, "failed reading register\n");
  111. return ret;
  112. }
  113. return 0;
  114. }
  115. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  116. int off)
  117. {
  118. int ret;
  119. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  120. int offset = off / BANK_SZ;
  121. ret = i2c_smbus_write_byte_data(chip->client,
  122. (reg << bank_shift) + offset, val);
  123. if (ret < 0) {
  124. dev_err(&chip->client->dev, "failed writing register\n");
  125. return ret;
  126. }
  127. return 0;
  128. }
  129. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  130. {
  131. int ret = 0;
  132. if (chip->gpio_chip.ngpio <= 8)
  133. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  134. else if (chip->gpio_chip.ngpio >= 24) {
  135. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  136. ret = i2c_smbus_write_i2c_block_data(chip->client,
  137. (reg << bank_shift) | REG_ADDR_AI,
  138. NBANK(chip), val);
  139. } else {
  140. switch (chip->chip_type) {
  141. case PCA953X_TYPE:
  142. ret = i2c_smbus_write_word_data(chip->client,
  143. reg << 1, cpu_to_le16(get_unaligned((u16 *)val)));
  144. break;
  145. case PCA957X_TYPE:
  146. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  147. val[0]);
  148. if (ret < 0)
  149. break;
  150. ret = i2c_smbus_write_byte_data(chip->client,
  151. (reg << 1) + 1,
  152. val[1]);
  153. break;
  154. }
  155. }
  156. if (ret < 0) {
  157. dev_err(&chip->client->dev, "failed writing register\n");
  158. return ret;
  159. }
  160. return 0;
  161. }
  162. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  163. {
  164. int ret;
  165. if (chip->gpio_chip.ngpio <= 8) {
  166. ret = i2c_smbus_read_byte_data(chip->client, reg);
  167. *val = ret;
  168. } else if (chip->gpio_chip.ngpio >= 24) {
  169. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  170. ret = i2c_smbus_read_i2c_block_data(chip->client,
  171. (reg << bank_shift) | REG_ADDR_AI,
  172. NBANK(chip), val);
  173. } else {
  174. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  175. val[0] = (u16)ret & 0xFF;
  176. val[1] = (u16)ret >> 8;
  177. }
  178. if (ret < 0) {
  179. dev_err(&chip->client->dev, "failed reading register\n");
  180. return ret;
  181. }
  182. return 0;
  183. }
  184. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  185. {
  186. struct pca953x_chip *chip = gpiochip_get_data(gc);
  187. u8 reg_val;
  188. int ret, offset = 0;
  189. mutex_lock(&chip->i2c_lock);
  190. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  191. switch (chip->chip_type) {
  192. case PCA953X_TYPE:
  193. offset = PCA953X_DIRECTION;
  194. break;
  195. case PCA957X_TYPE:
  196. offset = PCA957X_CFG;
  197. break;
  198. }
  199. ret = pca953x_write_single(chip, offset, reg_val, off);
  200. if (ret)
  201. goto exit;
  202. chip->reg_direction[off / BANK_SZ] = reg_val;
  203. exit:
  204. mutex_unlock(&chip->i2c_lock);
  205. return ret;
  206. }
  207. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  208. unsigned off, int val)
  209. {
  210. struct pca953x_chip *chip = gpiochip_get_data(gc);
  211. u8 reg_val;
  212. int ret, offset = 0;
  213. mutex_lock(&chip->i2c_lock);
  214. /* set output level */
  215. if (val)
  216. reg_val = chip->reg_output[off / BANK_SZ]
  217. | (1u << (off % BANK_SZ));
  218. else
  219. reg_val = chip->reg_output[off / BANK_SZ]
  220. & ~(1u << (off % BANK_SZ));
  221. switch (chip->chip_type) {
  222. case PCA953X_TYPE:
  223. offset = PCA953X_OUTPUT;
  224. break;
  225. case PCA957X_TYPE:
  226. offset = PCA957X_OUT;
  227. break;
  228. }
  229. ret = pca953x_write_single(chip, offset, reg_val, off);
  230. if (ret)
  231. goto exit;
  232. chip->reg_output[off / BANK_SZ] = reg_val;
  233. /* then direction */
  234. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  235. switch (chip->chip_type) {
  236. case PCA953X_TYPE:
  237. offset = PCA953X_DIRECTION;
  238. break;
  239. case PCA957X_TYPE:
  240. offset = PCA957X_CFG;
  241. break;
  242. }
  243. ret = pca953x_write_single(chip, offset, reg_val, off);
  244. if (ret)
  245. goto exit;
  246. chip->reg_direction[off / BANK_SZ] = reg_val;
  247. exit:
  248. mutex_unlock(&chip->i2c_lock);
  249. return ret;
  250. }
  251. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  252. {
  253. struct pca953x_chip *chip = gpiochip_get_data(gc);
  254. u32 reg_val;
  255. int ret, offset = 0;
  256. mutex_lock(&chip->i2c_lock);
  257. switch (chip->chip_type) {
  258. case PCA953X_TYPE:
  259. offset = PCA953X_INPUT;
  260. break;
  261. case PCA957X_TYPE:
  262. offset = PCA957X_IN;
  263. break;
  264. }
  265. ret = pca953x_read_single(chip, offset, &reg_val, off);
  266. mutex_unlock(&chip->i2c_lock);
  267. if (ret < 0) {
  268. /* NOTE: diagnostic already emitted; that's all we should
  269. * do unless gpio_*_value_cansleep() calls become different
  270. * from their nonsleeping siblings (and report faults).
  271. */
  272. return 0;
  273. }
  274. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  275. }
  276. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  277. {
  278. struct pca953x_chip *chip = gpiochip_get_data(gc);
  279. u8 reg_val;
  280. int ret, offset = 0;
  281. mutex_lock(&chip->i2c_lock);
  282. if (val)
  283. reg_val = chip->reg_output[off / BANK_SZ]
  284. | (1u << (off % BANK_SZ));
  285. else
  286. reg_val = chip->reg_output[off / BANK_SZ]
  287. & ~(1u << (off % BANK_SZ));
  288. switch (chip->chip_type) {
  289. case PCA953X_TYPE:
  290. offset = PCA953X_OUTPUT;
  291. break;
  292. case PCA957X_TYPE:
  293. offset = PCA957X_OUT;
  294. break;
  295. }
  296. ret = pca953x_write_single(chip, offset, reg_val, off);
  297. if (ret)
  298. goto exit;
  299. chip->reg_output[off / BANK_SZ] = reg_val;
  300. exit:
  301. mutex_unlock(&chip->i2c_lock);
  302. }
  303. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  304. unsigned long *mask, unsigned long *bits)
  305. {
  306. struct pca953x_chip *chip = gpiochip_get_data(gc);
  307. u8 reg_val[MAX_BANK];
  308. int ret, offset = 0;
  309. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  310. int bank;
  311. switch (chip->chip_type) {
  312. case PCA953X_TYPE:
  313. offset = PCA953X_OUTPUT;
  314. break;
  315. case PCA957X_TYPE:
  316. offset = PCA957X_OUT;
  317. break;
  318. }
  319. memcpy(reg_val, chip->reg_output, NBANK(chip));
  320. mutex_lock(&chip->i2c_lock);
  321. for(bank=0; bank<NBANK(chip); bank++) {
  322. unsigned bankmask = mask[bank / sizeof(*mask)] >>
  323. ((bank % sizeof(*mask)) * 8);
  324. if(bankmask) {
  325. unsigned bankval = bits[bank / sizeof(*bits)] >>
  326. ((bank % sizeof(*bits)) * 8);
  327. reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
  328. }
  329. }
  330. ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
  331. if (ret)
  332. goto exit;
  333. memcpy(chip->reg_output, reg_val, NBANK(chip));
  334. exit:
  335. mutex_unlock(&chip->i2c_lock);
  336. }
  337. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  338. {
  339. struct gpio_chip *gc;
  340. gc = &chip->gpio_chip;
  341. gc->direction_input = pca953x_gpio_direction_input;
  342. gc->direction_output = pca953x_gpio_direction_output;
  343. gc->get = pca953x_gpio_get_value;
  344. gc->set = pca953x_gpio_set_value;
  345. gc->set_multiple = pca953x_gpio_set_multiple;
  346. gc->can_sleep = true;
  347. gc->base = chip->gpio_start;
  348. gc->ngpio = gpios;
  349. gc->label = chip->client->name;
  350. gc->parent = &chip->client->dev;
  351. gc->owner = THIS_MODULE;
  352. gc->names = chip->names;
  353. }
  354. #ifdef CONFIG_GPIO_PCA953X_IRQ
  355. static void pca953x_irq_mask(struct irq_data *d)
  356. {
  357. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  358. struct pca953x_chip *chip = gpiochip_get_data(gc);
  359. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  360. }
  361. static void pca953x_irq_unmask(struct irq_data *d)
  362. {
  363. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  364. struct pca953x_chip *chip = gpiochip_get_data(gc);
  365. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  366. }
  367. static void pca953x_irq_bus_lock(struct irq_data *d)
  368. {
  369. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  370. struct pca953x_chip *chip = gpiochip_get_data(gc);
  371. mutex_lock(&chip->irq_lock);
  372. }
  373. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  374. {
  375. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  376. struct pca953x_chip *chip = gpiochip_get_data(gc);
  377. u8 new_irqs;
  378. int level, i;
  379. u8 invert_irq_mask[MAX_BANK];
  380. if (chip->driver_data & PCA_PCAL) {
  381. /* Enable latch on interrupt-enabled inputs */
  382. pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
  383. for (i = 0; i < NBANK(chip); i++)
  384. invert_irq_mask[i] = ~chip->irq_mask[i];
  385. /* Unmask enabled interrupts */
  386. pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
  387. }
  388. /* Look for any newly setup interrupt */
  389. for (i = 0; i < NBANK(chip); i++) {
  390. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  391. new_irqs &= ~chip->reg_direction[i];
  392. while (new_irqs) {
  393. level = __ffs(new_irqs);
  394. pca953x_gpio_direction_input(&chip->gpio_chip,
  395. level + (BANK_SZ * i));
  396. new_irqs &= ~(1 << level);
  397. }
  398. }
  399. mutex_unlock(&chip->irq_lock);
  400. }
  401. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  402. {
  403. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  404. struct pca953x_chip *chip = gpiochip_get_data(gc);
  405. int bank_nb = d->hwirq / BANK_SZ;
  406. u8 mask = 1 << (d->hwirq % BANK_SZ);
  407. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  408. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  409. d->irq, type);
  410. return -EINVAL;
  411. }
  412. if (type & IRQ_TYPE_EDGE_FALLING)
  413. chip->irq_trig_fall[bank_nb] |= mask;
  414. else
  415. chip->irq_trig_fall[bank_nb] &= ~mask;
  416. if (type & IRQ_TYPE_EDGE_RISING)
  417. chip->irq_trig_raise[bank_nb] |= mask;
  418. else
  419. chip->irq_trig_raise[bank_nb] &= ~mask;
  420. return 0;
  421. }
  422. static struct irq_chip pca953x_irq_chip = {
  423. .name = "pca953x",
  424. .irq_mask = pca953x_irq_mask,
  425. .irq_unmask = pca953x_irq_unmask,
  426. .irq_bus_lock = pca953x_irq_bus_lock,
  427. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  428. .irq_set_type = pca953x_irq_set_type,
  429. };
  430. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  431. {
  432. u8 cur_stat[MAX_BANK];
  433. u8 old_stat[MAX_BANK];
  434. bool pending_seen = false;
  435. bool trigger_seen = false;
  436. u8 trigger[MAX_BANK];
  437. int ret, i, offset = 0;
  438. if (chip->driver_data & PCA_PCAL) {
  439. /* Read the current interrupt status from the device */
  440. ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
  441. if (ret)
  442. return false;
  443. /* Check latched inputs and clear interrupt status */
  444. ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
  445. if (ret)
  446. return false;
  447. for (i = 0; i < NBANK(chip); i++) {
  448. /* Apply filter for rising/falling edge selection */
  449. pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
  450. (cur_stat[i] & chip->irq_trig_raise[i]);
  451. pending[i] &= trigger[i];
  452. if (pending[i])
  453. pending_seen = true;
  454. }
  455. return pending_seen;
  456. }
  457. switch (chip->chip_type) {
  458. case PCA953X_TYPE:
  459. offset = PCA953X_INPUT;
  460. break;
  461. case PCA957X_TYPE:
  462. offset = PCA957X_IN;
  463. break;
  464. }
  465. ret = pca953x_read_regs(chip, offset, cur_stat);
  466. if (ret)
  467. return false;
  468. /* Remove output pins from the equation */
  469. for (i = 0; i < NBANK(chip); i++)
  470. cur_stat[i] &= chip->reg_direction[i];
  471. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  472. for (i = 0; i < NBANK(chip); i++) {
  473. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  474. if (trigger[i])
  475. trigger_seen = true;
  476. }
  477. if (!trigger_seen)
  478. return false;
  479. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  480. for (i = 0; i < NBANK(chip); i++) {
  481. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  482. (cur_stat[i] & chip->irq_trig_raise[i]);
  483. pending[i] &= trigger[i];
  484. if (pending[i])
  485. pending_seen = true;
  486. }
  487. return pending_seen;
  488. }
  489. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  490. {
  491. struct pca953x_chip *chip = devid;
  492. u8 pending[MAX_BANK];
  493. u8 level;
  494. unsigned nhandled = 0;
  495. int i;
  496. if (!pca953x_irq_pending(chip, pending))
  497. return IRQ_NONE;
  498. for (i = 0; i < NBANK(chip); i++) {
  499. while (pending[i]) {
  500. level = __ffs(pending[i]);
  501. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  502. level + (BANK_SZ * i)));
  503. pending[i] &= ~(1 << level);
  504. nhandled++;
  505. }
  506. }
  507. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  508. }
  509. static int pca953x_irq_setup(struct pca953x_chip *chip,
  510. int irq_base)
  511. {
  512. struct i2c_client *client = chip->client;
  513. int ret, i, offset = 0;
  514. if (client->irq && irq_base != -1
  515. && (chip->driver_data & PCA_INT)) {
  516. switch (chip->chip_type) {
  517. case PCA953X_TYPE:
  518. offset = PCA953X_INPUT;
  519. break;
  520. case PCA957X_TYPE:
  521. offset = PCA957X_IN;
  522. break;
  523. }
  524. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  525. if (ret)
  526. return ret;
  527. /*
  528. * There is no way to know which GPIO line generated the
  529. * interrupt. We have to rely on the previous read for
  530. * this purpose.
  531. */
  532. for (i = 0; i < NBANK(chip); i++)
  533. chip->irq_stat[i] &= chip->reg_direction[i];
  534. mutex_init(&chip->irq_lock);
  535. ret = devm_request_threaded_irq(&client->dev,
  536. client->irq,
  537. NULL,
  538. pca953x_irq_handler,
  539. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  540. IRQF_SHARED,
  541. dev_name(&client->dev), chip);
  542. if (ret) {
  543. dev_err(&client->dev, "failed to request irq %d\n",
  544. client->irq);
  545. return ret;
  546. }
  547. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  548. &pca953x_irq_chip,
  549. irq_base,
  550. handle_simple_irq,
  551. IRQ_TYPE_NONE);
  552. if (ret) {
  553. dev_err(&client->dev,
  554. "could not connect irqchip to gpiochip\n");
  555. return ret;
  556. }
  557. gpiochip_set_chained_irqchip(&chip->gpio_chip,
  558. &pca953x_irq_chip,
  559. client->irq, NULL);
  560. }
  561. return 0;
  562. }
  563. #else /* CONFIG_GPIO_PCA953X_IRQ */
  564. static int pca953x_irq_setup(struct pca953x_chip *chip,
  565. int irq_base)
  566. {
  567. struct i2c_client *client = chip->client;
  568. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  569. dev_warn(&client->dev, "interrupt support not compiled in\n");
  570. return 0;
  571. }
  572. #endif
  573. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  574. {
  575. int ret;
  576. u8 val[MAX_BANK];
  577. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  578. if (ret)
  579. goto out;
  580. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  581. chip->reg_direction);
  582. if (ret)
  583. goto out;
  584. /* set platform specific polarity inversion */
  585. if (invert)
  586. memset(val, 0xFF, NBANK(chip));
  587. else
  588. memset(val, 0, NBANK(chip));
  589. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  590. out:
  591. return ret;
  592. }
  593. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  594. {
  595. int ret;
  596. u8 val[MAX_BANK];
  597. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  598. if (ret)
  599. goto out;
  600. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  601. if (ret)
  602. goto out;
  603. /* set platform specific polarity inversion */
  604. if (invert)
  605. memset(val, 0xFF, NBANK(chip));
  606. else
  607. memset(val, 0, NBANK(chip));
  608. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  609. if (ret)
  610. goto out;
  611. /* To enable register 6, 7 to control pull up and pull down */
  612. memset(val, 0x02, NBANK(chip));
  613. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  614. if (ret)
  615. goto out;
  616. return 0;
  617. out:
  618. return ret;
  619. }
  620. static const struct of_device_id pca953x_dt_ids[];
  621. static int pca953x_probe(struct i2c_client *client,
  622. const struct i2c_device_id *id)
  623. {
  624. struct pca953x_platform_data *pdata;
  625. struct pca953x_chip *chip;
  626. int irq_base = 0;
  627. int ret;
  628. u32 invert = 0;
  629. chip = devm_kzalloc(&client->dev,
  630. sizeof(struct pca953x_chip), GFP_KERNEL);
  631. if (chip == NULL)
  632. return -ENOMEM;
  633. pdata = dev_get_platdata(&client->dev);
  634. if (pdata) {
  635. irq_base = pdata->irq_base;
  636. chip->gpio_start = pdata->gpio_base;
  637. invert = pdata->invert;
  638. chip->names = pdata->names;
  639. } else {
  640. chip->gpio_start = -1;
  641. irq_base = 0;
  642. }
  643. chip->client = client;
  644. if (id) {
  645. chip->driver_data = id->driver_data;
  646. } else {
  647. const struct acpi_device_id *id;
  648. const struct of_device_id *match;
  649. match = of_match_device(pca953x_dt_ids, &client->dev);
  650. if (match) {
  651. chip->driver_data = (int)(uintptr_t)match->data;
  652. } else {
  653. id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  654. if (!id)
  655. return -ENODEV;
  656. chip->driver_data = id->driver_data;
  657. }
  658. }
  659. chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
  660. mutex_init(&chip->i2c_lock);
  661. /* initialize cached registers from their original values.
  662. * we can't share this chip with another i2c master.
  663. */
  664. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  665. if (chip->chip_type == PCA953X_TYPE)
  666. ret = device_pca953x_init(chip, invert);
  667. else
  668. ret = device_pca957x_init(chip, invert);
  669. if (ret)
  670. return ret;
  671. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  672. if (ret)
  673. return ret;
  674. ret = pca953x_irq_setup(chip, irq_base);
  675. if (ret)
  676. return ret;
  677. if (pdata && pdata->setup) {
  678. ret = pdata->setup(client, chip->gpio_chip.base,
  679. chip->gpio_chip.ngpio, pdata->context);
  680. if (ret < 0)
  681. dev_warn(&client->dev, "setup failed, %d\n", ret);
  682. }
  683. i2c_set_clientdata(client, chip);
  684. return 0;
  685. }
  686. static int pca953x_remove(struct i2c_client *client)
  687. {
  688. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  689. struct pca953x_chip *chip = i2c_get_clientdata(client);
  690. int ret;
  691. if (pdata && pdata->teardown) {
  692. ret = pdata->teardown(client, chip->gpio_chip.base,
  693. chip->gpio_chip.ngpio, pdata->context);
  694. if (ret < 0) {
  695. dev_err(&client->dev, "%s failed, %d\n",
  696. "teardown", ret);
  697. return ret;
  698. }
  699. }
  700. return 0;
  701. }
  702. /* convenience to stop overlong match-table lines */
  703. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  704. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  705. static const struct of_device_id pca953x_dt_ids[] = {
  706. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  707. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  708. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  709. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  710. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  711. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  712. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  713. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  714. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  715. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  716. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  717. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  718. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  719. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  720. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  721. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  722. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  723. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  724. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  725. { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
  726. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  727. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  728. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  729. { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
  730. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  731. { }
  732. };
  733. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  734. static struct i2c_driver pca953x_driver = {
  735. .driver = {
  736. .name = "pca953x",
  737. .of_match_table = pca953x_dt_ids,
  738. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  739. },
  740. .probe = pca953x_probe,
  741. .remove = pca953x_remove,
  742. .id_table = pca953x_id,
  743. };
  744. static int __init pca953x_init(void)
  745. {
  746. return i2c_add_driver(&pca953x_driver);
  747. }
  748. /* register after i2c postcore initcall and before
  749. * subsys initcalls that may rely on these GPIOs
  750. */
  751. subsys_initcall(pca953x_init);
  752. static void __exit pca953x_exit(void)
  753. {
  754. i2c_del_driver(&pca953x_driver);
  755. }
  756. module_exit(pca953x_exit);
  757. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  758. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  759. MODULE_LICENSE("GPL");