tilcdc_drv.c 18 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include <linux/component.h>
  19. #include <linux/pinctrl/consumer.h>
  20. #include <linux/suspend.h>
  21. #include "tilcdc_drv.h"
  22. #include "tilcdc_regs.h"
  23. #include "tilcdc_tfp410.h"
  24. #include "tilcdc_panel.h"
  25. #include "tilcdc_external.h"
  26. #include "drm_fb_helper.h"
  27. static LIST_HEAD(module_list);
  28. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  29. const struct tilcdc_module_ops *funcs)
  30. {
  31. mod->name = name;
  32. mod->funcs = funcs;
  33. INIT_LIST_HEAD(&mod->list);
  34. list_add(&mod->list, &module_list);
  35. }
  36. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  37. {
  38. list_del(&mod->list);
  39. }
  40. static struct of_device_id tilcdc_of_match[];
  41. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  42. struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  43. {
  44. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  45. }
  46. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  47. {
  48. struct tilcdc_drm_private *priv = dev->dev_private;
  49. drm_fbdev_cma_hotplug_event(priv->fbdev);
  50. }
  51. static const struct drm_mode_config_funcs mode_config_funcs = {
  52. .fb_create = tilcdc_fb_create,
  53. .output_poll_changed = tilcdc_fb_output_poll_changed,
  54. };
  55. static int modeset_init(struct drm_device *dev)
  56. {
  57. struct tilcdc_drm_private *priv = dev->dev_private;
  58. struct tilcdc_module *mod;
  59. drm_mode_config_init(dev);
  60. priv->crtc = tilcdc_crtc_create(dev);
  61. list_for_each_entry(mod, &module_list, list) {
  62. DBG("loading module: %s", mod->name);
  63. mod->funcs->modeset_init(mod, dev);
  64. }
  65. dev->mode_config.min_width = 0;
  66. dev->mode_config.min_height = 0;
  67. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  68. dev->mode_config.max_height = 2048;
  69. dev->mode_config.funcs = &mode_config_funcs;
  70. return 0;
  71. }
  72. #ifdef CONFIG_CPU_FREQ
  73. static int cpufreq_transition(struct notifier_block *nb,
  74. unsigned long val, void *data)
  75. {
  76. struct tilcdc_drm_private *priv = container_of(nb,
  77. struct tilcdc_drm_private, freq_transition);
  78. if (val == CPUFREQ_POSTCHANGE) {
  79. if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
  80. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  81. tilcdc_crtc_update_clk(priv->crtc);
  82. }
  83. }
  84. return 0;
  85. }
  86. #endif
  87. /*
  88. * DRM operations:
  89. */
  90. static int tilcdc_unload(struct drm_device *dev)
  91. {
  92. struct tilcdc_drm_private *priv = dev->dev_private;
  93. tilcdc_remove_external_encoders(dev);
  94. drm_fbdev_cma_fini(priv->fbdev);
  95. drm_kms_helper_poll_fini(dev);
  96. drm_mode_config_cleanup(dev);
  97. drm_vblank_cleanup(dev);
  98. pm_runtime_get_sync(dev->dev);
  99. drm_irq_uninstall(dev);
  100. pm_runtime_put_sync(dev->dev);
  101. #ifdef CONFIG_CPU_FREQ
  102. cpufreq_unregister_notifier(&priv->freq_transition,
  103. CPUFREQ_TRANSITION_NOTIFIER);
  104. #endif
  105. if (priv->clk)
  106. clk_put(priv->clk);
  107. if (priv->mmio)
  108. iounmap(priv->mmio);
  109. flush_workqueue(priv->wq);
  110. destroy_workqueue(priv->wq);
  111. dev->dev_private = NULL;
  112. pm_runtime_disable(dev->dev);
  113. kfree(priv);
  114. return 0;
  115. }
  116. static int tilcdc_load(struct drm_device *dev, unsigned long flags)
  117. {
  118. struct platform_device *pdev = dev->platformdev;
  119. struct device_node *node = pdev->dev.of_node;
  120. struct tilcdc_drm_private *priv;
  121. struct tilcdc_module *mod;
  122. struct resource *res;
  123. u32 bpp = 0;
  124. int ret;
  125. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  126. if (!priv) {
  127. dev_err(dev->dev, "failed to allocate private data\n");
  128. return -ENOMEM;
  129. }
  130. dev->dev_private = priv;
  131. priv->is_componentized =
  132. tilcdc_get_external_components(dev->dev, NULL) > 0;
  133. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  134. if (!priv->wq) {
  135. ret = -ENOMEM;
  136. goto fail_free_priv;
  137. }
  138. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  139. if (!res) {
  140. dev_err(dev->dev, "failed to get memory resource\n");
  141. ret = -EINVAL;
  142. goto fail_free_wq;
  143. }
  144. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  145. if (!priv->mmio) {
  146. dev_err(dev->dev, "failed to ioremap\n");
  147. ret = -ENOMEM;
  148. goto fail_free_wq;
  149. }
  150. priv->clk = clk_get(dev->dev, "fck");
  151. if (IS_ERR(priv->clk)) {
  152. dev_err(dev->dev, "failed to get functional clock\n");
  153. ret = -ENODEV;
  154. goto fail_iounmap;
  155. }
  156. #ifdef CONFIG_CPU_FREQ
  157. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  158. priv->freq_transition.notifier_call = cpufreq_transition;
  159. ret = cpufreq_register_notifier(&priv->freq_transition,
  160. CPUFREQ_TRANSITION_NOTIFIER);
  161. if (ret) {
  162. dev_err(dev->dev, "failed to register cpufreq notifier\n");
  163. goto fail_put_clk;
  164. }
  165. #endif
  166. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  167. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  168. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  169. if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
  170. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
  171. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  172. if (of_property_read_u32(node, "ti,max-pixelclock",
  173. &priv->max_pixelclock))
  174. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  175. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  176. pm_runtime_enable(dev->dev);
  177. pm_runtime_irq_safe(dev->dev);
  178. /* Determine LCD IP Version */
  179. pm_runtime_get_sync(dev->dev);
  180. switch (tilcdc_read(dev, LCDC_PID_REG)) {
  181. case 0x4c100102:
  182. priv->rev = 1;
  183. break;
  184. case 0x4f200800:
  185. case 0x4f201000:
  186. priv->rev = 2;
  187. break;
  188. default:
  189. dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
  190. "defaulting to LCD revision 1\n",
  191. tilcdc_read(dev, LCDC_PID_REG));
  192. priv->rev = 1;
  193. break;
  194. }
  195. pm_runtime_put_sync(dev->dev);
  196. ret = modeset_init(dev);
  197. if (ret < 0) {
  198. dev_err(dev->dev, "failed to initialize mode setting\n");
  199. goto fail_cpufreq_unregister;
  200. }
  201. platform_set_drvdata(pdev, dev);
  202. if (priv->is_componentized) {
  203. ret = component_bind_all(dev->dev, dev);
  204. if (ret < 0)
  205. goto fail_mode_config_cleanup;
  206. ret = tilcdc_add_external_encoders(dev, &bpp);
  207. if (ret < 0)
  208. goto fail_component_cleanup;
  209. }
  210. if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
  211. dev_err(dev->dev, "no encoders/connectors found\n");
  212. ret = -ENXIO;
  213. goto fail_external_cleanup;
  214. }
  215. ret = drm_vblank_init(dev, 1);
  216. if (ret < 0) {
  217. dev_err(dev->dev, "failed to initialize vblank\n");
  218. goto fail_external_cleanup;
  219. }
  220. pm_runtime_get_sync(dev->dev);
  221. ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
  222. pm_runtime_put_sync(dev->dev);
  223. if (ret < 0) {
  224. dev_err(dev->dev, "failed to install IRQ handler\n");
  225. goto fail_vblank_cleanup;
  226. }
  227. list_for_each_entry(mod, &module_list, list) {
  228. DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
  229. bpp = mod->preferred_bpp;
  230. if (bpp > 0)
  231. break;
  232. }
  233. drm_helper_disable_unused_functions(dev);
  234. priv->fbdev = drm_fbdev_cma_init(dev, bpp,
  235. dev->mode_config.num_crtc,
  236. dev->mode_config.num_connector);
  237. if (IS_ERR(priv->fbdev)) {
  238. ret = PTR_ERR(priv->fbdev);
  239. goto fail_irq_uninstall;
  240. }
  241. drm_kms_helper_poll_init(dev);
  242. return 0;
  243. fail_irq_uninstall:
  244. pm_runtime_get_sync(dev->dev);
  245. drm_irq_uninstall(dev);
  246. pm_runtime_put_sync(dev->dev);
  247. fail_vblank_cleanup:
  248. drm_vblank_cleanup(dev);
  249. fail_mode_config_cleanup:
  250. drm_mode_config_cleanup(dev);
  251. fail_component_cleanup:
  252. if (priv->is_componentized)
  253. component_unbind_all(dev->dev, dev);
  254. fail_external_cleanup:
  255. tilcdc_remove_external_encoders(dev);
  256. fail_cpufreq_unregister:
  257. pm_runtime_disable(dev->dev);
  258. #ifdef CONFIG_CPU_FREQ
  259. cpufreq_unregister_notifier(&priv->freq_transition,
  260. CPUFREQ_TRANSITION_NOTIFIER);
  261. #endif
  262. fail_put_clk:
  263. clk_put(priv->clk);
  264. fail_iounmap:
  265. iounmap(priv->mmio);
  266. fail_free_wq:
  267. flush_workqueue(priv->wq);
  268. destroy_workqueue(priv->wq);
  269. fail_free_priv:
  270. dev->dev_private = NULL;
  271. kfree(priv);
  272. return ret;
  273. }
  274. static void tilcdc_lastclose(struct drm_device *dev)
  275. {
  276. struct tilcdc_drm_private *priv = dev->dev_private;
  277. drm_fbdev_cma_restore_mode(priv->fbdev);
  278. }
  279. static irqreturn_t tilcdc_irq(int irq, void *arg)
  280. {
  281. struct drm_device *dev = arg;
  282. struct tilcdc_drm_private *priv = dev->dev_private;
  283. return tilcdc_crtc_irq(priv->crtc);
  284. }
  285. static void tilcdc_irq_preinstall(struct drm_device *dev)
  286. {
  287. tilcdc_clear_irqstatus(dev, 0xffffffff);
  288. }
  289. static int tilcdc_irq_postinstall(struct drm_device *dev)
  290. {
  291. struct tilcdc_drm_private *priv = dev->dev_private;
  292. /* enable FIFO underflow irq: */
  293. if (priv->rev == 1)
  294. tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
  295. else
  296. tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA);
  297. return 0;
  298. }
  299. static void tilcdc_irq_uninstall(struct drm_device *dev)
  300. {
  301. struct tilcdc_drm_private *priv = dev->dev_private;
  302. /* disable irqs that we might have enabled: */
  303. if (priv->rev == 1) {
  304. tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
  305. LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
  306. tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
  307. } else {
  308. tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
  309. LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
  310. LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
  311. LCDC_FRAME_DONE);
  312. }
  313. }
  314. static void enable_vblank(struct drm_device *dev, bool enable)
  315. {
  316. struct tilcdc_drm_private *priv = dev->dev_private;
  317. u32 reg, mask;
  318. if (priv->rev == 1) {
  319. reg = LCDC_DMA_CTRL_REG;
  320. mask = LCDC_V1_END_OF_FRAME_INT_ENA;
  321. } else {
  322. reg = LCDC_INT_ENABLE_SET_REG;
  323. mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
  324. LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
  325. }
  326. if (enable)
  327. tilcdc_set(dev, reg, mask);
  328. else
  329. tilcdc_clear(dev, reg, mask);
  330. }
  331. static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
  332. {
  333. enable_vblank(dev, true);
  334. return 0;
  335. }
  336. static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
  337. {
  338. enable_vblank(dev, false);
  339. }
  340. #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
  341. static const struct {
  342. const char *name;
  343. uint8_t rev;
  344. uint8_t save;
  345. uint32_t reg;
  346. } registers[] = {
  347. #define REG(rev, save, reg) { #reg, rev, save, reg }
  348. /* exists in revision 1: */
  349. REG(1, false, LCDC_PID_REG),
  350. REG(1, true, LCDC_CTRL_REG),
  351. REG(1, false, LCDC_STAT_REG),
  352. REG(1, true, LCDC_RASTER_CTRL_REG),
  353. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  354. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  355. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  356. REG(1, true, LCDC_DMA_CTRL_REG),
  357. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  358. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  359. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  360. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  361. /* new in revision 2: */
  362. REG(2, false, LCDC_RAW_STAT_REG),
  363. REG(2, false, LCDC_MASKED_STAT_REG),
  364. REG(2, false, LCDC_INT_ENABLE_SET_REG),
  365. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  366. REG(2, false, LCDC_END_OF_INT_IND_REG),
  367. REG(2, true, LCDC_CLK_ENABLE_REG),
  368. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  369. #undef REG
  370. };
  371. #endif
  372. #ifdef CONFIG_DEBUG_FS
  373. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  374. {
  375. struct drm_info_node *node = (struct drm_info_node *) m->private;
  376. struct drm_device *dev = node->minor->dev;
  377. struct tilcdc_drm_private *priv = dev->dev_private;
  378. unsigned i;
  379. pm_runtime_get_sync(dev->dev);
  380. seq_printf(m, "revision: %d\n", priv->rev);
  381. for (i = 0; i < ARRAY_SIZE(registers); i++)
  382. if (priv->rev >= registers[i].rev)
  383. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  384. tilcdc_read(dev, registers[i].reg));
  385. pm_runtime_put_sync(dev->dev);
  386. return 0;
  387. }
  388. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  389. {
  390. struct drm_info_node *node = (struct drm_info_node *) m->private;
  391. struct drm_device *dev = node->minor->dev;
  392. return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
  393. }
  394. static struct drm_info_list tilcdc_debugfs_list[] = {
  395. { "regs", tilcdc_regs_show, 0 },
  396. { "mm", tilcdc_mm_show, 0 },
  397. { "fb", drm_fb_cma_debugfs_show, 0 },
  398. };
  399. static int tilcdc_debugfs_init(struct drm_minor *minor)
  400. {
  401. struct drm_device *dev = minor->dev;
  402. struct tilcdc_module *mod;
  403. int ret;
  404. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  405. ARRAY_SIZE(tilcdc_debugfs_list),
  406. minor->debugfs_root, minor);
  407. list_for_each_entry(mod, &module_list, list)
  408. if (mod->funcs->debugfs_init)
  409. mod->funcs->debugfs_init(mod, minor);
  410. if (ret) {
  411. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  412. return ret;
  413. }
  414. return ret;
  415. }
  416. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  417. {
  418. struct tilcdc_module *mod;
  419. drm_debugfs_remove_files(tilcdc_debugfs_list,
  420. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  421. list_for_each_entry(mod, &module_list, list)
  422. if (mod->funcs->debugfs_cleanup)
  423. mod->funcs->debugfs_cleanup(mod, minor);
  424. }
  425. #endif
  426. static const struct file_operations fops = {
  427. .owner = THIS_MODULE,
  428. .open = drm_open,
  429. .release = drm_release,
  430. .unlocked_ioctl = drm_ioctl,
  431. #ifdef CONFIG_COMPAT
  432. .compat_ioctl = drm_compat_ioctl,
  433. #endif
  434. .poll = drm_poll,
  435. .read = drm_read,
  436. .llseek = no_llseek,
  437. .mmap = drm_gem_cma_mmap,
  438. };
  439. static struct drm_driver tilcdc_driver = {
  440. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  441. .load = tilcdc_load,
  442. .unload = tilcdc_unload,
  443. .lastclose = tilcdc_lastclose,
  444. .set_busid = drm_platform_set_busid,
  445. .irq_handler = tilcdc_irq,
  446. .irq_preinstall = tilcdc_irq_preinstall,
  447. .irq_postinstall = tilcdc_irq_postinstall,
  448. .irq_uninstall = tilcdc_irq_uninstall,
  449. .get_vblank_counter = drm_vblank_no_hw_counter,
  450. .enable_vblank = tilcdc_enable_vblank,
  451. .disable_vblank = tilcdc_disable_vblank,
  452. .gem_free_object = drm_gem_cma_free_object,
  453. .gem_vm_ops = &drm_gem_cma_vm_ops,
  454. .dumb_create = drm_gem_cma_dumb_create,
  455. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  456. .dumb_destroy = drm_gem_dumb_destroy,
  457. #ifdef CONFIG_DEBUG_FS
  458. .debugfs_init = tilcdc_debugfs_init,
  459. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  460. #endif
  461. .fops = &fops,
  462. .name = "tilcdc",
  463. .desc = "TI LCD Controller DRM",
  464. .date = "20121205",
  465. .major = 1,
  466. .minor = 0,
  467. };
  468. /*
  469. * Power management:
  470. */
  471. #ifdef CONFIG_PM_SLEEP
  472. static int tilcdc_pm_suspend(struct device *dev)
  473. {
  474. struct drm_device *ddev = dev_get_drvdata(dev);
  475. struct tilcdc_drm_private *priv = ddev->dev_private;
  476. unsigned i, n = 0;
  477. drm_kms_helper_poll_disable(ddev);
  478. /* Select sleep pin state */
  479. pinctrl_pm_select_sleep_state(dev);
  480. if (pm_runtime_suspended(dev)) {
  481. priv->ctx_valid = false;
  482. return 0;
  483. }
  484. /* Save register state: */
  485. for (i = 0; i < ARRAY_SIZE(registers); i++)
  486. if (registers[i].save && (priv->rev >= registers[i].rev))
  487. priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
  488. priv->ctx_valid = true;
  489. return 0;
  490. }
  491. static int tilcdc_pm_resume(struct device *dev)
  492. {
  493. struct drm_device *ddev = dev_get_drvdata(dev);
  494. struct tilcdc_drm_private *priv = ddev->dev_private;
  495. unsigned i, n = 0;
  496. /* Select default pin state */
  497. pinctrl_pm_select_default_state(dev);
  498. if (priv->ctx_valid == true) {
  499. /* Restore register state: */
  500. for (i = 0; i < ARRAY_SIZE(registers); i++)
  501. if (registers[i].save &&
  502. (priv->rev >= registers[i].rev))
  503. tilcdc_write(ddev, registers[i].reg,
  504. priv->saved_register[n++]);
  505. }
  506. drm_kms_helper_poll_enable(ddev);
  507. return 0;
  508. }
  509. #endif
  510. static const struct dev_pm_ops tilcdc_pm_ops = {
  511. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  512. };
  513. /*
  514. * Platform driver:
  515. */
  516. static int tilcdc_bind(struct device *dev)
  517. {
  518. return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
  519. }
  520. static void tilcdc_unbind(struct device *dev)
  521. {
  522. drm_put_dev(dev_get_drvdata(dev));
  523. }
  524. static const struct component_master_ops tilcdc_comp_ops = {
  525. .bind = tilcdc_bind,
  526. .unbind = tilcdc_unbind,
  527. };
  528. static int tilcdc_pdev_probe(struct platform_device *pdev)
  529. {
  530. struct component_match *match = NULL;
  531. int ret;
  532. /* bail out early if no DT data: */
  533. if (!pdev->dev.of_node) {
  534. dev_err(&pdev->dev, "device-tree data is missing\n");
  535. return -ENXIO;
  536. }
  537. ret = tilcdc_get_external_components(&pdev->dev, &match);
  538. if (ret < 0)
  539. return ret;
  540. else if (ret == 0)
  541. return drm_platform_init(&tilcdc_driver, pdev);
  542. else
  543. return component_master_add_with_match(&pdev->dev,
  544. &tilcdc_comp_ops,
  545. match);
  546. }
  547. static int tilcdc_pdev_remove(struct platform_device *pdev)
  548. {
  549. struct drm_device *ddev = dev_get_drvdata(&pdev->dev);
  550. struct tilcdc_drm_private *priv = ddev->dev_private;
  551. /* Check if a subcomponent has already triggered the unloading. */
  552. if (!priv)
  553. return 0;
  554. if (priv->is_componentized)
  555. component_master_del(&pdev->dev, &tilcdc_comp_ops);
  556. else
  557. drm_put_dev(platform_get_drvdata(pdev));
  558. return 0;
  559. }
  560. static struct of_device_id tilcdc_of_match[] = {
  561. { .compatible = "ti,am33xx-tilcdc", },
  562. { },
  563. };
  564. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  565. static struct platform_driver tilcdc_platform_driver = {
  566. .probe = tilcdc_pdev_probe,
  567. .remove = tilcdc_pdev_remove,
  568. .driver = {
  569. .name = "tilcdc",
  570. .pm = &tilcdc_pm_ops,
  571. .of_match_table = tilcdc_of_match,
  572. },
  573. };
  574. static int __init tilcdc_drm_init(void)
  575. {
  576. DBG("init");
  577. tilcdc_tfp410_init();
  578. tilcdc_panel_init();
  579. return platform_driver_register(&tilcdc_platform_driver);
  580. }
  581. static void __exit tilcdc_drm_fini(void)
  582. {
  583. DBG("fini");
  584. platform_driver_unregister(&tilcdc_platform_driver);
  585. tilcdc_panel_fini();
  586. tilcdc_tfp410_fini();
  587. }
  588. module_init(tilcdc_drm_init);
  589. module_exit(tilcdc_drm_fini);
  590. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  591. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  592. MODULE_LICENSE("GPL");