gpio-mvebu.txt 2.7 KB

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  1. * Marvell EBU GPIO controller
  2. Required properties:
  3. - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
  4. or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
  5. Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
  6. 370. "marvell,mv78200-gpio" should be used for the Discovery
  7. MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
  8. SoCs (MV78230, MV78260, MV78460).
  9. - reg: Address and length of the register set for the device. Only one
  10. entry is expected, except for the "marvell,armadaxp-gpio" variant
  11. for which two entries are expected: one for the general registers,
  12. one for the per-cpu registers.
  13. - interrupts: The list of interrupts that are used for all the pins
  14. managed by this GPIO bank. There can be more than one interrupt
  15. (example: 1 interrupt per 8 pins on Armada XP, which means 4
  16. interrupts per bank of 32 GPIOs).
  17. - interrupt-controller: identifies the node as an interrupt controller
  18. - #interrupt-cells: specifies the number of cells needed to encode an
  19. interrupt source. Should be two.
  20. The first cell is the GPIO number.
  21. The second cell is used to specify flags:
  22. bits[3:0] trigger type and level flags:
  23. 1 = low-to-high edge triggered.
  24. 2 = high-to-low edge triggered.
  25. 4 = active high level-sensitive.
  26. 8 = active low level-sensitive.
  27. - gpio-controller: marks the device node as a gpio controller
  28. - ngpios: number of GPIOs this controller has
  29. - #gpio-cells: Should be two. The first cell is the pin number. The
  30. second cell is reserved for flags, unused at the moment.
  31. Optional properties:
  32. In order to use the GPIO lines in PWM mode, some additional optional
  33. properties are required.
  34. - compatible: Must contain "marvell,armada-370-gpio"
  35. - reg: an additional register set is needed, for the GPIO Blink
  36. Counter on/off registers.
  37. - reg-names: Must contain an entry "pwm" corresponding to the
  38. additional register range needed for PWM operation.
  39. - #pwm-cells: Should be two. The first cell is the GPIO line number. The
  40. second cell is the period in nanoseconds.
  41. - clocks: Must be a phandle to the clock for the GPIO controller.
  42. Example:
  43. gpio0: gpio@d0018100 {
  44. compatible = "marvell,armadaxp-gpio";
  45. reg = <0xd0018100 0x40>,
  46. <0xd0018800 0x30>;
  47. ngpios = <32>;
  48. gpio-controller;
  49. #gpio-cells = <2>;
  50. interrupt-controller;
  51. #interrupt-cells = <2>;
  52. interrupts = <16>, <17>, <18>, <19>;
  53. };
  54. gpio1: gpio@18140 {
  55. compatible = "marvell,armada-370-gpio";
  56. reg = <0x18140 0x40>, <0x181c8 0x08>;
  57. reg-names = "gpio", "pwm";
  58. ngpios = <17>;
  59. gpio-controller;
  60. #gpio-cells = <2>;
  61. #pwm-cells = <2>;
  62. interrupt-controller;
  63. #interrupt-cells = <2>;
  64. interrupts = <87>, <88>, <89>;
  65. clocks = <&coreclk 0>;
  66. };