dm816x.dtsi 12 KB

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  1. /*
  2. * This file is licensed under the terms of the GNU General Public License
  3. * version 2. This program is licensed "as is" without any warranty of any
  4. * kind, whether express or implied.
  5. */
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/pinctrl/omap.h>
  8. / {
  9. compatible = "ti,dm816";
  10. interrupt-parent = <&intc>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. chosen { };
  14. aliases {
  15. i2c0 = &i2c1;
  16. i2c1 = &i2c2;
  17. serial0 = &uart1;
  18. serial1 = &uart2;
  19. serial2 = &uart3;
  20. ethernet0 = &eth0;
  21. ethernet1 = &eth1;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. cpu@0 {
  27. compatible = "arm,cortex-a8";
  28. device_type = "cpu";
  29. reg = <0>;
  30. };
  31. };
  32. pmu {
  33. compatible = "arm,cortex-a8-pmu";
  34. interrupts = <3>;
  35. };
  36. /*
  37. * The soc node represents the soc top level view. It is used for IPs
  38. * that are not memory mapped in the MPU view or for the MPU itself.
  39. */
  40. soc {
  41. compatible = "ti,omap-infra";
  42. mpu {
  43. compatible = "ti,omap3-mpu";
  44. ti,hwmods = "mpu";
  45. };
  46. };
  47. /*
  48. * XXX: Use a flat representation of the dm816x interconnect.
  49. * The real dm816x interconnect network is quite complex. Since
  50. * it will not bring real advantage to represent that in DT
  51. * for the moment, just use a fake OCP bus entry to represent
  52. * the whole bus hierarchy.
  53. */
  54. ocp {
  55. compatible = "simple-bus";
  56. reg = <0x44000000 0x10000>;
  57. interrupts = <9 10>;
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. ranges;
  61. prcm: prcm@48180000 {
  62. compatible = "ti,dm816-prcm";
  63. reg = <0x48180000 0x4000>;
  64. prcm_clocks: clocks {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. };
  68. prcm_clockdomains: clockdomains {
  69. };
  70. };
  71. scrm: scrm@48140000 {
  72. compatible = "ti,dm816-scrm", "simple-bus";
  73. reg = <0x48140000 0x21000>;
  74. #address-cells = <1>;
  75. #size-cells = <1>;
  76. #pinctrl-cells = <1>;
  77. ranges = <0 0x48140000 0x21000>;
  78. dm816x_pinmux: pinmux@800 {
  79. compatible = "pinctrl-single";
  80. reg = <0x800 0x50a>;
  81. #address-cells = <1>;
  82. #size-cells = <0>;
  83. #pinctrl-cells = <1>;
  84. pinctrl-single,register-width = <16>;
  85. pinctrl-single,function-mask = <0xf>;
  86. };
  87. /* Device Configuration Registers */
  88. scm_conf: syscon@600 {
  89. compatible = "syscon", "simple-bus";
  90. reg = <0x600 0x110>;
  91. #address-cells = <1>;
  92. #size-cells = <1>;
  93. ranges = <0 0x600 0x110>;
  94. usb_phy0: usb-phy@20 {
  95. compatible = "ti,dm8168-usb-phy";
  96. reg = <0x20 0x8>;
  97. reg-names = "phy";
  98. clocks = <&main_fapll 6>;
  99. clock-names = "refclk";
  100. #phy-cells = <0>;
  101. syscon = <&scm_conf>;
  102. };
  103. usb_phy1: usb-phy@28 {
  104. compatible = "ti,dm8168-usb-phy";
  105. reg = <0x28 0x8>;
  106. reg-names = "phy";
  107. clocks = <&main_fapll 6>;
  108. clock-names = "refclk";
  109. #phy-cells = <0>;
  110. syscon = <&scm_conf>;
  111. };
  112. };
  113. scrm_clocks: clocks {
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. };
  117. scrm_clockdomains: clockdomains {
  118. };
  119. };
  120. edma: edma@49000000 {
  121. compatible = "ti,edma3";
  122. ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
  123. reg = <0x49000000 0x10000>,
  124. <0x44e10f90 0x40>;
  125. interrupts = <12 13 14>;
  126. #dma-cells = <1>;
  127. };
  128. elm: elm@48080000 {
  129. compatible = "ti,816-elm";
  130. ti,hwmods = "elm";
  131. reg = <0x48080000 0x2000>;
  132. interrupts = <4>;
  133. };
  134. gpio1: gpio@48032000 {
  135. compatible = "ti,omap4-gpio";
  136. ti,hwmods = "gpio1";
  137. ti,gpio-always-on;
  138. reg = <0x48032000 0x1000>;
  139. interrupts = <96>;
  140. gpio-controller;
  141. #gpio-cells = <2>;
  142. interrupt-controller;
  143. #interrupt-cells = <2>;
  144. };
  145. gpio2: gpio@4804c000 {
  146. compatible = "ti,omap4-gpio";
  147. ti,hwmods = "gpio2";
  148. ti,gpio-always-on;
  149. reg = <0x4804c000 0x1000>;
  150. interrupts = <98>;
  151. gpio-controller;
  152. #gpio-cells = <2>;
  153. interrupt-controller;
  154. #interrupt-cells = <2>;
  155. };
  156. gpmc: gpmc@50000000 {
  157. compatible = "ti,am3352-gpmc";
  158. ti,hwmods = "gpmc";
  159. reg = <0x50000000 0x2000>;
  160. #address-cells = <2>;
  161. #size-cells = <1>;
  162. interrupts = <100>;
  163. dmas = <&edma 52>;
  164. dma-names = "rxtx";
  165. gpmc,num-cs = <6>;
  166. gpmc,num-waitpins = <2>;
  167. interrupt-controller;
  168. #interrupt-cells = <2>;
  169. gpio-controller;
  170. #gpio-cells = <2>;
  171. };
  172. i2c1: i2c@48028000 {
  173. compatible = "ti,omap4-i2c";
  174. ti,hwmods = "i2c1";
  175. reg = <0x48028000 0x1000>;
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. interrupts = <70>;
  179. dmas = <&edma 58 &edma 59>;
  180. dma-names = "tx", "rx";
  181. };
  182. i2c2: i2c@4802a000 {
  183. compatible = "ti,omap4-i2c";
  184. ti,hwmods = "i2c2";
  185. reg = <0x4802a000 0x1000>;
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. interrupts = <71>;
  189. dmas = <&edma 60 &edma 61>;
  190. dma-names = "tx", "rx";
  191. };
  192. intc: interrupt-controller@48200000 {
  193. compatible = "ti,dm816-intc";
  194. interrupt-controller;
  195. #interrupt-cells = <1>;
  196. reg = <0x48200000 0x1000>;
  197. };
  198. rtc: rtc@480c0000 {
  199. compatible = "ti,am3352-rtc", "ti,da830-rtc";
  200. reg = <0x480c0000 0x1000>;
  201. interrupts = <75 76>;
  202. ti,hwmods = "rtc";
  203. };
  204. mailbox: mailbox@480c8000 {
  205. compatible = "ti,omap4-mailbox";
  206. reg = <0x480c8000 0x2000>;
  207. interrupts = <77>;
  208. ti,hwmods = "mailbox";
  209. #mbox-cells = <1>;
  210. ti,mbox-num-users = <4>;
  211. ti,mbox-num-fifos = <12>;
  212. mbox_dsp: mbox_dsp {
  213. ti,mbox-tx = <3 0 0>;
  214. ti,mbox-rx = <0 0 0>;
  215. };
  216. };
  217. spinbox: spinbox@480ca000 {
  218. compatible = "ti,omap4-hwspinlock";
  219. reg = <0x480ca000 0x2000>;
  220. ti,hwmods = "spinbox";
  221. #hwlock-cells = <1>;
  222. };
  223. mdio: mdio@4a100800 {
  224. compatible = "ti,davinci_mdio";
  225. #address-cells = <1>;
  226. #size-cells = <0>;
  227. reg = <0x4a100800 0x100>;
  228. ti,hwmods = "davinci_mdio";
  229. bus_freq = <1000000>;
  230. phy0: ethernet-phy@0 {
  231. reg = <1>;
  232. };
  233. phy1: ethernet-phy@1 {
  234. reg = <2>;
  235. };
  236. };
  237. eth0: ethernet@4a100000 {
  238. compatible = "ti,dm816-emac";
  239. ti,hwmods = "emac0";
  240. reg = <0x4a100000 0x800
  241. 0x4a100900 0x3700>;
  242. clocks = <&sysclk24_ck>;
  243. syscon = <&scm_conf>;
  244. ti,davinci-ctrl-reg-offset = <0>;
  245. ti,davinci-ctrl-mod-reg-offset = <0x900>;
  246. ti,davinci-ctrl-ram-offset = <0x2000>;
  247. ti,davinci-ctrl-ram-size = <0x2000>;
  248. interrupts = <40 41 42 43>;
  249. phy-handle = <&phy0>;
  250. };
  251. eth1: ethernet@4a120000 {
  252. compatible = "ti,dm816-emac";
  253. ti,hwmods = "emac1";
  254. reg = <0x4a120000 0x4000>;
  255. clocks = <&sysclk24_ck>;
  256. syscon = <&scm_conf>;
  257. ti,davinci-ctrl-reg-offset = <0>;
  258. ti,davinci-ctrl-mod-reg-offset = <0x900>;
  259. ti,davinci-ctrl-ram-offset = <0x2000>;
  260. ti,davinci-ctrl-ram-size = <0x2000>;
  261. interrupts = <44 45 46 47>;
  262. phy-handle = <&phy1>;
  263. };
  264. mcspi1: spi@48030000 {
  265. compatible = "ti,omap4-mcspi";
  266. reg = <0x48030000 0x1000>;
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. interrupts = <65>;
  270. ti,spi-num-cs = <4>;
  271. ti,hwmods = "mcspi1";
  272. dmas = <&edma 16 &edma 17
  273. &edma 18 &edma 19
  274. &edma 20 &edma 21
  275. &edma 22 &edma 23>;
  276. dma-names = "tx0", "rx0", "tx1", "rx1",
  277. "tx2", "rx2", "tx3", "rx3";
  278. };
  279. mmc1: mmc@48060000 {
  280. compatible = "ti,omap4-hsmmc";
  281. reg = <0x48060000 0x11000>;
  282. ti,hwmods = "mmc1";
  283. interrupts = <64>;
  284. dmas = <&edma 24 &edma 25>;
  285. dma-names = "tx", "rx";
  286. };
  287. timer1: timer@4802e000 {
  288. compatible = "ti,dm816-timer";
  289. reg = <0x4802e000 0x2000>;
  290. interrupts = <67>;
  291. ti,hwmods = "timer1";
  292. ti,timer-alwon;
  293. };
  294. timer2: timer@48040000 {
  295. compatible = "ti,dm816-timer";
  296. reg = <0x48040000 0x2000>;
  297. interrupts = <68>;
  298. ti,hwmods = "timer2";
  299. };
  300. timer3: timer@48042000 {
  301. compatible = "ti,dm816-timer";
  302. reg = <0x48042000 0x2000>;
  303. interrupts = <69>;
  304. ti,hwmods = "timer3";
  305. };
  306. timer4: timer@48044000 {
  307. compatible = "ti,dm816-timer";
  308. reg = <0x48044000 0x2000>;
  309. interrupts = <92>;
  310. ti,hwmods = "timer4";
  311. ti,timer-pwm;
  312. };
  313. timer5: timer@48046000 {
  314. compatible = "ti,dm816-timer";
  315. reg = <0x48046000 0x2000>;
  316. interrupts = <93>;
  317. ti,hwmods = "timer5";
  318. ti,timer-pwm;
  319. };
  320. timer6: timer@48048000 {
  321. compatible = "ti,dm816-timer";
  322. reg = <0x48048000 0x2000>;
  323. interrupts = <94>;
  324. ti,hwmods = "timer6";
  325. ti,timer-pwm;
  326. };
  327. timer7: timer@4804a000 {
  328. compatible = "ti,dm816-timer";
  329. reg = <0x4804a000 0x2000>;
  330. interrupts = <95>;
  331. ti,hwmods = "timer7";
  332. ti,timer-pwm;
  333. };
  334. uart1: uart@48020000 {
  335. compatible = "ti,omap3-uart";
  336. ti,hwmods = "uart1";
  337. reg = <0x48020000 0x2000>;
  338. clock-frequency = <48000000>;
  339. interrupts = <72>;
  340. dmas = <&edma 26 &edma 27>;
  341. dma-names = "tx", "rx";
  342. };
  343. uart2: uart@48022000 {
  344. compatible = "ti,omap3-uart";
  345. ti,hwmods = "uart2";
  346. reg = <0x48022000 0x2000>;
  347. clock-frequency = <48000000>;
  348. interrupts = <73>;
  349. dmas = <&edma 28 &edma 29>;
  350. dma-names = "tx", "rx";
  351. };
  352. uart3: uart@48024000 {
  353. compatible = "ti,omap3-uart";
  354. ti,hwmods = "uart3";
  355. reg = <0x48024000 0x2000>;
  356. clock-frequency = <48000000>;
  357. interrupts = <74>;
  358. dmas = <&edma 30 &edma 31>;
  359. dma-names = "tx", "rx";
  360. };
  361. /* NOTE: USB needs a transceiver driver for phys to work */
  362. usb: usb_otg_hs@47401000 {
  363. compatible = "ti,am33xx-usb";
  364. reg = <0x47401000 0x400000>;
  365. ranges;
  366. #address-cells = <1>;
  367. #size-cells = <1>;
  368. ti,hwmods = "usb_otg_hs";
  369. usb0: usb@47401000 {
  370. compatible = "ti,musb-dm816";
  371. reg = <0x47401400 0x400
  372. 0x47401000 0x200>;
  373. reg-names = "mc", "control";
  374. interrupts = <18>;
  375. interrupt-names = "mc";
  376. dr_mode = "host";
  377. interface-type = <0>;
  378. phys = <&usb_phy0>;
  379. phy-names = "usb2-phy";
  380. mentor,multipoint = <1>;
  381. mentor,num-eps = <16>;
  382. mentor,ram-bits = <12>;
  383. mentor,power = <500>;
  384. dmas = <&cppi41dma 0 0 &cppi41dma 1 0
  385. &cppi41dma 2 0 &cppi41dma 3 0
  386. &cppi41dma 4 0 &cppi41dma 5 0
  387. &cppi41dma 6 0 &cppi41dma 7 0
  388. &cppi41dma 8 0 &cppi41dma 9 0
  389. &cppi41dma 10 0 &cppi41dma 11 0
  390. &cppi41dma 12 0 &cppi41dma 13 0
  391. &cppi41dma 14 0 &cppi41dma 0 1
  392. &cppi41dma 1 1 &cppi41dma 2 1
  393. &cppi41dma 3 1 &cppi41dma 4 1
  394. &cppi41dma 5 1 &cppi41dma 6 1
  395. &cppi41dma 7 1 &cppi41dma 8 1
  396. &cppi41dma 9 1 &cppi41dma 10 1
  397. &cppi41dma 11 1 &cppi41dma 12 1
  398. &cppi41dma 13 1 &cppi41dma 14 1>;
  399. dma-names =
  400. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  401. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  402. "rx14", "rx15",
  403. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  404. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  405. "tx14", "tx15";
  406. };
  407. usb1: usb@47401800 {
  408. compatible = "ti,musb-dm816";
  409. reg = <0x47401c00 0x400
  410. 0x47401800 0x200>;
  411. reg-names = "mc", "control";
  412. interrupts = <19>;
  413. interrupt-names = "mc";
  414. dr_mode = "host";
  415. interface-type = <0>;
  416. phys = <&usb_phy1>;
  417. phy-names = "usb2-phy";
  418. mentor,multipoint = <1>;
  419. mentor,num-eps = <16>;
  420. mentor,ram-bits = <12>;
  421. mentor,power = <500>;
  422. dmas = <&cppi41dma 15 0 &cppi41dma 16 0
  423. &cppi41dma 17 0 &cppi41dma 18 0
  424. &cppi41dma 19 0 &cppi41dma 20 0
  425. &cppi41dma 21 0 &cppi41dma 22 0
  426. &cppi41dma 23 0 &cppi41dma 24 0
  427. &cppi41dma 25 0 &cppi41dma 26 0
  428. &cppi41dma 27 0 &cppi41dma 28 0
  429. &cppi41dma 29 0 &cppi41dma 15 1
  430. &cppi41dma 16 1 &cppi41dma 17 1
  431. &cppi41dma 18 1 &cppi41dma 19 1
  432. &cppi41dma 20 1 &cppi41dma 21 1
  433. &cppi41dma 22 1 &cppi41dma 23 1
  434. &cppi41dma 24 1 &cppi41dma 25 1
  435. &cppi41dma 26 1 &cppi41dma 27 1
  436. &cppi41dma 28 1 &cppi41dma 29 1>;
  437. dma-names =
  438. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  439. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  440. "rx14", "rx15",
  441. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  442. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  443. "tx14", "tx15";
  444. };
  445. cppi41dma: dma-controller@47402000 {
  446. compatible = "ti,am3359-cppi41";
  447. reg = <0x47400000 0x1000
  448. 0x47402000 0x1000
  449. 0x47403000 0x1000
  450. 0x47404000 0x4000>;
  451. reg-names = "glue", "controller", "scheduler", "queuemgr";
  452. interrupts = <17>;
  453. interrupt-names = "glue";
  454. #dma-cells = <2>;
  455. #dma-channels = <30>;
  456. #dma-requests = <256>;
  457. };
  458. };
  459. wd_timer2: wd_timer@480c2000 {
  460. compatible = "ti,omap3-wdt";
  461. ti,hwmods = "wd_timer";
  462. reg = <0x480c2000 0x1000>;
  463. interrupts = <0>;
  464. };
  465. };
  466. };
  467. #include "dm816x-clocks.dtsi"