am33xx.dtsi 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950
  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. #include <dt-bindings/gpio/gpio.h>
  11. #include <dt-bindings/pinctrl/am33xx.h>
  12. / {
  13. compatible = "ti,am33xx";
  14. interrupt-parent = <&intc>;
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. chosen { };
  18. aliases {
  19. i2c0 = &i2c0;
  20. i2c1 = &i2c1;
  21. i2c2 = &i2c2;
  22. serial0 = &uart0;
  23. serial1 = &uart1;
  24. serial2 = &uart2;
  25. serial3 = &uart3;
  26. serial4 = &uart4;
  27. serial5 = &uart5;
  28. d_can0 = &dcan0;
  29. d_can1 = &dcan1;
  30. usb0 = &usb0;
  31. usb1 = &usb1;
  32. phy0 = &usb0_phy;
  33. phy1 = &usb1_phy;
  34. ethernet0 = &cpsw_emac0;
  35. ethernet1 = &cpsw_emac1;
  36. };
  37. cpus {
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. cpu@0 {
  41. compatible = "arm,cortex-a8";
  42. device_type = "cpu";
  43. reg = <0>;
  44. /*
  45. * To consider voltage drop between PMIC and SoC,
  46. * tolerance value is reduced to 2% from 4% and
  47. * voltage value is increased as a precaution.
  48. */
  49. operating-points = <
  50. /* kHz uV */
  51. 720000 1285000
  52. 600000 1225000
  53. 500000 1125000
  54. 275000 1125000
  55. >;
  56. voltage-tolerance = <2>; /* 2 percentage */
  57. clocks = <&dpll_mpu_ck>;
  58. clock-names = "cpu";
  59. clock-latency = <300000>; /* From omap-cpufreq driver */
  60. };
  61. };
  62. pmu {
  63. compatible = "arm,cortex-a8-pmu";
  64. interrupts = <3>;
  65. };
  66. /*
  67. * The soc node represents the soc top level view. It is used for IPs
  68. * that are not memory mapped in the MPU view or for the MPU itself.
  69. */
  70. soc {
  71. compatible = "ti,omap-infra";
  72. mpu {
  73. compatible = "ti,omap3-mpu";
  74. ti,hwmods = "mpu";
  75. };
  76. };
  77. /*
  78. * XXX: Use a flat representation of the AM33XX interconnect.
  79. * The real AM33XX interconnect network is quite complex. Since
  80. * it will not bring real advantage to represent that in DT
  81. * for the moment, just use a fake OCP bus entry to represent
  82. * the whole bus hierarchy.
  83. */
  84. ocp {
  85. compatible = "simple-bus";
  86. #address-cells = <1>;
  87. #size-cells = <1>;
  88. ranges;
  89. ti,hwmods = "l3_main";
  90. l4_wkup: l4_wkup@44c00000 {
  91. compatible = "ti,am3-l4-wkup", "simple-bus";
  92. #address-cells = <1>;
  93. #size-cells = <1>;
  94. ranges = <0 0x44c00000 0x280000>;
  95. wkup_m3: wkup_m3@100000 {
  96. compatible = "ti,am3352-wkup-m3";
  97. reg = <0x100000 0x4000>,
  98. <0x180000 0x2000>;
  99. reg-names = "umem", "dmem";
  100. ti,hwmods = "wkup_m3";
  101. ti,pm-firmware = "am335x-pm-firmware.elf";
  102. };
  103. prcm: prcm@200000 {
  104. compatible = "ti,am3-prcm";
  105. reg = <0x200000 0x4000>;
  106. prcm_clocks: clocks {
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. };
  110. prcm_clockdomains: clockdomains {
  111. };
  112. };
  113. scm: scm@210000 {
  114. compatible = "ti,am3-scm", "simple-bus";
  115. reg = <0x210000 0x2000>;
  116. #address-cells = <1>;
  117. #size-cells = <1>;
  118. #pinctrl-cells = <1>;
  119. ranges = <0 0x210000 0x2000>;
  120. am33xx_pinmux: pinmux@800 {
  121. compatible = "pinctrl-single";
  122. reg = <0x800 0x238>;
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. #pinctrl-cells = <1>;
  126. pinctrl-single,register-width = <32>;
  127. pinctrl-single,function-mask = <0x7f>;
  128. };
  129. scm_conf: scm_conf@0 {
  130. compatible = "syscon";
  131. reg = <0x0 0x800>;
  132. #address-cells = <1>;
  133. #size-cells = <1>;
  134. scm_clocks: clocks {
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. };
  138. };
  139. wkup_m3_ipc: wkup_m3_ipc@1324 {
  140. compatible = "ti,am3352-wkup-m3-ipc";
  141. reg = <0x1324 0x24>;
  142. interrupts = <78>;
  143. ti,rproc = <&wkup_m3>;
  144. mboxes = <&mailbox &mbox_wkupm3>;
  145. };
  146. edma_xbar: dma-router@f90 {
  147. compatible = "ti,am335x-edma-crossbar";
  148. reg = <0xf90 0x40>;
  149. #dma-cells = <3>;
  150. dma-requests = <32>;
  151. dma-masters = <&edma>;
  152. };
  153. scm_clockdomains: clockdomains {
  154. };
  155. };
  156. };
  157. intc: interrupt-controller@48200000 {
  158. compatible = "ti,am33xx-intc";
  159. interrupt-controller;
  160. #interrupt-cells = <1>;
  161. reg = <0x48200000 0x1000>;
  162. };
  163. edma: edma@49000000 {
  164. compatible = "ti,edma3-tpcc";
  165. ti,hwmods = "tpcc";
  166. reg = <0x49000000 0x10000>;
  167. reg-names = "edma3_cc";
  168. interrupts = <12 13 14>;
  169. interrupt-names = "edma3_ccint", "edma3_mperr",
  170. "edma3_ccerrint";
  171. dma-requests = <64>;
  172. #dma-cells = <2>;
  173. ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
  174. <&edma_tptc2 0>;
  175. ti,edma-memcpy-channels = <20 21>;
  176. };
  177. edma_tptc0: tptc@49800000 {
  178. compatible = "ti,edma3-tptc";
  179. ti,hwmods = "tptc0";
  180. reg = <0x49800000 0x100000>;
  181. interrupts = <112>;
  182. interrupt-names = "edma3_tcerrint";
  183. };
  184. edma_tptc1: tptc@49900000 {
  185. compatible = "ti,edma3-tptc";
  186. ti,hwmods = "tptc1";
  187. reg = <0x49900000 0x100000>;
  188. interrupts = <113>;
  189. interrupt-names = "edma3_tcerrint";
  190. };
  191. edma_tptc2: tptc@49a00000 {
  192. compatible = "ti,edma3-tptc";
  193. ti,hwmods = "tptc2";
  194. reg = <0x49a00000 0x100000>;
  195. interrupts = <114>;
  196. interrupt-names = "edma3_tcerrint";
  197. };
  198. gpio0: gpio@44e07000 {
  199. compatible = "ti,omap4-gpio";
  200. ti,hwmods = "gpio1";
  201. gpio-controller;
  202. #gpio-cells = <2>;
  203. interrupt-controller;
  204. #interrupt-cells = <2>;
  205. reg = <0x44e07000 0x1000>;
  206. interrupts = <96>;
  207. };
  208. gpio1: gpio@4804c000 {
  209. compatible = "ti,omap4-gpio";
  210. ti,hwmods = "gpio2";
  211. gpio-controller;
  212. #gpio-cells = <2>;
  213. interrupt-controller;
  214. #interrupt-cells = <2>;
  215. reg = <0x4804c000 0x1000>;
  216. interrupts = <98>;
  217. };
  218. gpio2: gpio@481ac000 {
  219. compatible = "ti,omap4-gpio";
  220. ti,hwmods = "gpio3";
  221. gpio-controller;
  222. #gpio-cells = <2>;
  223. interrupt-controller;
  224. #interrupt-cells = <2>;
  225. reg = <0x481ac000 0x1000>;
  226. interrupts = <32>;
  227. };
  228. gpio3: gpio@481ae000 {
  229. compatible = "ti,omap4-gpio";
  230. ti,hwmods = "gpio4";
  231. gpio-controller;
  232. #gpio-cells = <2>;
  233. interrupt-controller;
  234. #interrupt-cells = <2>;
  235. reg = <0x481ae000 0x1000>;
  236. interrupts = <62>;
  237. };
  238. uart0: serial@44e09000 {
  239. compatible = "ti,am3352-uart", "ti,omap3-uart";
  240. ti,hwmods = "uart1";
  241. clock-frequency = <48000000>;
  242. reg = <0x44e09000 0x2000>;
  243. interrupts = <72>;
  244. status = "disabled";
  245. dmas = <&edma 26 0>, <&edma 27 0>;
  246. dma-names = "tx", "rx";
  247. };
  248. uart1: serial@48022000 {
  249. compatible = "ti,am3352-uart", "ti,omap3-uart";
  250. ti,hwmods = "uart2";
  251. clock-frequency = <48000000>;
  252. reg = <0x48022000 0x2000>;
  253. interrupts = <73>;
  254. status = "disabled";
  255. dmas = <&edma 28 0>, <&edma 29 0>;
  256. dma-names = "tx", "rx";
  257. };
  258. uart2: serial@48024000 {
  259. compatible = "ti,am3352-uart", "ti,omap3-uart";
  260. ti,hwmods = "uart3";
  261. clock-frequency = <48000000>;
  262. reg = <0x48024000 0x2000>;
  263. interrupts = <74>;
  264. status = "disabled";
  265. dmas = <&edma 30 0>, <&edma 31 0>;
  266. dma-names = "tx", "rx";
  267. };
  268. uart3: serial@481a6000 {
  269. compatible = "ti,am3352-uart", "ti,omap3-uart";
  270. ti,hwmods = "uart4";
  271. clock-frequency = <48000000>;
  272. reg = <0x481a6000 0x2000>;
  273. interrupts = <44>;
  274. status = "disabled";
  275. };
  276. uart4: serial@481a8000 {
  277. compatible = "ti,am3352-uart", "ti,omap3-uart";
  278. ti,hwmods = "uart5";
  279. clock-frequency = <48000000>;
  280. reg = <0x481a8000 0x2000>;
  281. interrupts = <45>;
  282. status = "disabled";
  283. };
  284. uart5: serial@481aa000 {
  285. compatible = "ti,am3352-uart", "ti,omap3-uart";
  286. ti,hwmods = "uart6";
  287. clock-frequency = <48000000>;
  288. reg = <0x481aa000 0x2000>;
  289. interrupts = <46>;
  290. status = "disabled";
  291. };
  292. i2c0: i2c@44e0b000 {
  293. compatible = "ti,omap4-i2c";
  294. #address-cells = <1>;
  295. #size-cells = <0>;
  296. ti,hwmods = "i2c1";
  297. reg = <0x44e0b000 0x1000>;
  298. interrupts = <70>;
  299. status = "disabled";
  300. };
  301. i2c1: i2c@4802a000 {
  302. compatible = "ti,omap4-i2c";
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. ti,hwmods = "i2c2";
  306. reg = <0x4802a000 0x1000>;
  307. interrupts = <71>;
  308. status = "disabled";
  309. };
  310. i2c2: i2c@4819c000 {
  311. compatible = "ti,omap4-i2c";
  312. #address-cells = <1>;
  313. #size-cells = <0>;
  314. ti,hwmods = "i2c3";
  315. reg = <0x4819c000 0x1000>;
  316. interrupts = <30>;
  317. status = "disabled";
  318. };
  319. mmc1: mmc@48060000 {
  320. compatible = "ti,omap4-hsmmc";
  321. ti,hwmods = "mmc1";
  322. ti,dual-volt;
  323. ti,needs-special-reset;
  324. ti,needs-special-hs-handling;
  325. dmas = <&edma_xbar 24 0 0
  326. &edma_xbar 25 0 0>;
  327. dma-names = "tx", "rx";
  328. interrupts = <64>;
  329. interrupt-parent = <&intc>;
  330. reg = <0x48060000 0x1000>;
  331. status = "disabled";
  332. };
  333. mmc2: mmc@481d8000 {
  334. compatible = "ti,omap4-hsmmc";
  335. ti,hwmods = "mmc2";
  336. ti,needs-special-reset;
  337. dmas = <&edma 2 0
  338. &edma 3 0>;
  339. dma-names = "tx", "rx";
  340. interrupts = <28>;
  341. interrupt-parent = <&intc>;
  342. reg = <0x481d8000 0x1000>;
  343. status = "disabled";
  344. };
  345. mmc3: mmc@47810000 {
  346. compatible = "ti,omap4-hsmmc";
  347. ti,hwmods = "mmc3";
  348. ti,needs-special-reset;
  349. interrupts = <29>;
  350. interrupt-parent = <&intc>;
  351. reg = <0x47810000 0x1000>;
  352. status = "disabled";
  353. };
  354. hwspinlock: spinlock@480ca000 {
  355. compatible = "ti,omap4-hwspinlock";
  356. reg = <0x480ca000 0x1000>;
  357. ti,hwmods = "spinlock";
  358. #hwlock-cells = <1>;
  359. };
  360. wdt2: wdt@44e35000 {
  361. compatible = "ti,omap3-wdt";
  362. ti,hwmods = "wd_timer2";
  363. reg = <0x44e35000 0x1000>;
  364. interrupts = <91>;
  365. };
  366. dcan0: can@481cc000 {
  367. compatible = "ti,am3352-d_can";
  368. ti,hwmods = "d_can0";
  369. reg = <0x481cc000 0x2000>;
  370. clocks = <&dcan0_fck>;
  371. clock-names = "fck";
  372. syscon-raminit = <&scm_conf 0x644 0>;
  373. interrupts = <52>;
  374. status = "disabled";
  375. };
  376. dcan1: can@481d0000 {
  377. compatible = "ti,am3352-d_can";
  378. ti,hwmods = "d_can1";
  379. reg = <0x481d0000 0x2000>;
  380. clocks = <&dcan1_fck>;
  381. clock-names = "fck";
  382. syscon-raminit = <&scm_conf 0x644 1>;
  383. interrupts = <55>;
  384. status = "disabled";
  385. };
  386. mailbox: mailbox@480C8000 {
  387. compatible = "ti,omap4-mailbox";
  388. reg = <0x480C8000 0x200>;
  389. interrupts = <77>;
  390. ti,hwmods = "mailbox";
  391. #mbox-cells = <1>;
  392. ti,mbox-num-users = <4>;
  393. ti,mbox-num-fifos = <8>;
  394. mbox_wkupm3: wkup_m3 {
  395. ti,mbox-send-noirq;
  396. ti,mbox-tx = <0 0 0>;
  397. ti,mbox-rx = <0 0 3>;
  398. };
  399. };
  400. timer1: timer@44e31000 {
  401. compatible = "ti,am335x-timer-1ms";
  402. reg = <0x44e31000 0x400>;
  403. interrupts = <67>;
  404. ti,hwmods = "timer1";
  405. ti,timer-alwon;
  406. };
  407. timer2: timer@48040000 {
  408. compatible = "ti,am335x-timer";
  409. reg = <0x48040000 0x400>;
  410. interrupts = <68>;
  411. ti,hwmods = "timer2";
  412. };
  413. timer3: timer@48042000 {
  414. compatible = "ti,am335x-timer";
  415. reg = <0x48042000 0x400>;
  416. interrupts = <69>;
  417. ti,hwmods = "timer3";
  418. };
  419. timer4: timer@48044000 {
  420. compatible = "ti,am335x-timer";
  421. reg = <0x48044000 0x400>;
  422. interrupts = <92>;
  423. ti,hwmods = "timer4";
  424. ti,timer-pwm;
  425. };
  426. timer5: timer@48046000 {
  427. compatible = "ti,am335x-timer";
  428. reg = <0x48046000 0x400>;
  429. interrupts = <93>;
  430. ti,hwmods = "timer5";
  431. ti,timer-pwm;
  432. };
  433. timer6: timer@48048000 {
  434. compatible = "ti,am335x-timer";
  435. reg = <0x48048000 0x400>;
  436. interrupts = <94>;
  437. ti,hwmods = "timer6";
  438. ti,timer-pwm;
  439. };
  440. timer7: timer@4804a000 {
  441. compatible = "ti,am335x-timer";
  442. reg = <0x4804a000 0x400>;
  443. interrupts = <95>;
  444. ti,hwmods = "timer7";
  445. ti,timer-pwm;
  446. };
  447. rtc: rtc@44e3e000 {
  448. compatible = "ti,am3352-rtc", "ti,da830-rtc";
  449. reg = <0x44e3e000 0x1000>;
  450. interrupts = <75
  451. 76>;
  452. ti,hwmods = "rtc";
  453. clocks = <&clkdiv32k_ick>;
  454. clock-names = "int-clk";
  455. };
  456. spi0: spi@48030000 {
  457. compatible = "ti,omap4-mcspi";
  458. #address-cells = <1>;
  459. #size-cells = <0>;
  460. reg = <0x48030000 0x400>;
  461. interrupts = <65>;
  462. ti,spi-num-cs = <2>;
  463. ti,hwmods = "spi0";
  464. dmas = <&edma 16 0
  465. &edma 17 0
  466. &edma 18 0
  467. &edma 19 0>;
  468. dma-names = "tx0", "rx0", "tx1", "rx1";
  469. status = "disabled";
  470. };
  471. spi1: spi@481a0000 {
  472. compatible = "ti,omap4-mcspi";
  473. #address-cells = <1>;
  474. #size-cells = <0>;
  475. reg = <0x481a0000 0x400>;
  476. interrupts = <125>;
  477. ti,spi-num-cs = <2>;
  478. ti,hwmods = "spi1";
  479. dmas = <&edma 42 0
  480. &edma 43 0
  481. &edma 44 0
  482. &edma 45 0>;
  483. dma-names = "tx0", "rx0", "tx1", "rx1";
  484. status = "disabled";
  485. };
  486. usb: usb@47400000 {
  487. compatible = "ti,am33xx-usb";
  488. reg = <0x47400000 0x1000>;
  489. ranges;
  490. #address-cells = <1>;
  491. #size-cells = <1>;
  492. ti,hwmods = "usb_otg_hs";
  493. status = "disabled";
  494. usb_ctrl_mod: control@44e10620 {
  495. compatible = "ti,am335x-usb-ctrl-module";
  496. reg = <0x44e10620 0x10
  497. 0x44e10648 0x4>;
  498. reg-names = "phy_ctrl", "wakeup";
  499. status = "disabled";
  500. };
  501. usb0_phy: usb-phy@47401300 {
  502. compatible = "ti,am335x-usb-phy";
  503. reg = <0x47401300 0x100>;
  504. reg-names = "phy";
  505. status = "disabled";
  506. ti,ctrl_mod = <&usb_ctrl_mod>;
  507. };
  508. usb0: usb@47401000 {
  509. compatible = "ti,musb-am33xx";
  510. status = "disabled";
  511. reg = <0x47401400 0x400
  512. 0x47401000 0x200>;
  513. reg-names = "mc", "control";
  514. interrupts = <18>;
  515. interrupt-names = "mc";
  516. dr_mode = "otg";
  517. mentor,multipoint = <1>;
  518. mentor,num-eps = <16>;
  519. mentor,ram-bits = <12>;
  520. mentor,power = <500>;
  521. phys = <&usb0_phy>;
  522. dmas = <&cppi41dma 0 0 &cppi41dma 1 0
  523. &cppi41dma 2 0 &cppi41dma 3 0
  524. &cppi41dma 4 0 &cppi41dma 5 0
  525. &cppi41dma 6 0 &cppi41dma 7 0
  526. &cppi41dma 8 0 &cppi41dma 9 0
  527. &cppi41dma 10 0 &cppi41dma 11 0
  528. &cppi41dma 12 0 &cppi41dma 13 0
  529. &cppi41dma 14 0 &cppi41dma 0 1
  530. &cppi41dma 1 1 &cppi41dma 2 1
  531. &cppi41dma 3 1 &cppi41dma 4 1
  532. &cppi41dma 5 1 &cppi41dma 6 1
  533. &cppi41dma 7 1 &cppi41dma 8 1
  534. &cppi41dma 9 1 &cppi41dma 10 1
  535. &cppi41dma 11 1 &cppi41dma 12 1
  536. &cppi41dma 13 1 &cppi41dma 14 1>;
  537. dma-names =
  538. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  539. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  540. "rx14", "rx15",
  541. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  542. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  543. "tx14", "tx15";
  544. };
  545. usb1_phy: usb-phy@47401b00 {
  546. compatible = "ti,am335x-usb-phy";
  547. reg = <0x47401b00 0x100>;
  548. reg-names = "phy";
  549. status = "disabled";
  550. ti,ctrl_mod = <&usb_ctrl_mod>;
  551. };
  552. usb1: usb@47401800 {
  553. compatible = "ti,musb-am33xx";
  554. status = "disabled";
  555. reg = <0x47401c00 0x400
  556. 0x47401800 0x200>;
  557. reg-names = "mc", "control";
  558. interrupts = <19>;
  559. interrupt-names = "mc";
  560. dr_mode = "otg";
  561. mentor,multipoint = <1>;
  562. mentor,num-eps = <16>;
  563. mentor,ram-bits = <12>;
  564. mentor,power = <500>;
  565. phys = <&usb1_phy>;
  566. dmas = <&cppi41dma 15 0 &cppi41dma 16 0
  567. &cppi41dma 17 0 &cppi41dma 18 0
  568. &cppi41dma 19 0 &cppi41dma 20 0
  569. &cppi41dma 21 0 &cppi41dma 22 0
  570. &cppi41dma 23 0 &cppi41dma 24 0
  571. &cppi41dma 25 0 &cppi41dma 26 0
  572. &cppi41dma 27 0 &cppi41dma 28 0
  573. &cppi41dma 29 0 &cppi41dma 15 1
  574. &cppi41dma 16 1 &cppi41dma 17 1
  575. &cppi41dma 18 1 &cppi41dma 19 1
  576. &cppi41dma 20 1 &cppi41dma 21 1
  577. &cppi41dma 22 1 &cppi41dma 23 1
  578. &cppi41dma 24 1 &cppi41dma 25 1
  579. &cppi41dma 26 1 &cppi41dma 27 1
  580. &cppi41dma 28 1 &cppi41dma 29 1>;
  581. dma-names =
  582. "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
  583. "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
  584. "rx14", "rx15",
  585. "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
  586. "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
  587. "tx14", "tx15";
  588. };
  589. cppi41dma: dma-controller@47402000 {
  590. compatible = "ti,am3359-cppi41";
  591. reg = <0x47400000 0x1000
  592. 0x47402000 0x1000
  593. 0x47403000 0x1000
  594. 0x47404000 0x4000>;
  595. reg-names = "glue", "controller", "scheduler", "queuemgr";
  596. interrupts = <17>;
  597. interrupt-names = "glue";
  598. #dma-cells = <2>;
  599. #dma-channels = <30>;
  600. #dma-requests = <256>;
  601. status = "disabled";
  602. };
  603. };
  604. epwmss0: epwmss@48300000 {
  605. compatible = "ti,am33xx-pwmss";
  606. reg = <0x48300000 0x10>;
  607. ti,hwmods = "epwmss0";
  608. #address-cells = <1>;
  609. #size-cells = <1>;
  610. status = "disabled";
  611. ranges = <0x48300100 0x48300100 0x80 /* ECAP */
  612. 0x48300180 0x48300180 0x80 /* EQEP */
  613. 0x48300200 0x48300200 0x80>; /* EHRPWM */
  614. ecap0: ecap@48300100 {
  615. compatible = "ti,am3352-ecap",
  616. "ti,am33xx-ecap";
  617. #pwm-cells = <3>;
  618. reg = <0x48300100 0x80>;
  619. clocks = <&l4ls_gclk>;
  620. clock-names = "fck";
  621. interrupts = <31>;
  622. interrupt-names = "ecap0";
  623. status = "disabled";
  624. };
  625. ehrpwm0: pwm@48300200 {
  626. compatible = "ti,am3352-ehrpwm",
  627. "ti,am33xx-ehrpwm";
  628. #pwm-cells = <3>;
  629. reg = <0x48300200 0x80>;
  630. clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
  631. clock-names = "tbclk", "fck";
  632. status = "disabled";
  633. };
  634. };
  635. epwmss1: epwmss@48302000 {
  636. compatible = "ti,am33xx-pwmss";
  637. reg = <0x48302000 0x10>;
  638. ti,hwmods = "epwmss1";
  639. #address-cells = <1>;
  640. #size-cells = <1>;
  641. status = "disabled";
  642. ranges = <0x48302100 0x48302100 0x80 /* ECAP */
  643. 0x48302180 0x48302180 0x80 /* EQEP */
  644. 0x48302200 0x48302200 0x80>; /* EHRPWM */
  645. ecap1: ecap@48302100 {
  646. compatible = "ti,am3352-ecap",
  647. "ti,am33xx-ecap";
  648. #pwm-cells = <3>;
  649. reg = <0x48302100 0x80>;
  650. clocks = <&l4ls_gclk>;
  651. clock-names = "fck";
  652. interrupts = <47>;
  653. interrupt-names = "ecap1";
  654. status = "disabled";
  655. };
  656. ehrpwm1: pwm@48302200 {
  657. compatible = "ti,am3352-ehrpwm",
  658. "ti,am33xx-ehrpwm";
  659. #pwm-cells = <3>;
  660. reg = <0x48302200 0x80>;
  661. clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
  662. clock-names = "tbclk", "fck";
  663. status = "disabled";
  664. };
  665. };
  666. epwmss2: epwmss@48304000 {
  667. compatible = "ti,am33xx-pwmss";
  668. reg = <0x48304000 0x10>;
  669. ti,hwmods = "epwmss2";
  670. #address-cells = <1>;
  671. #size-cells = <1>;
  672. status = "disabled";
  673. ranges = <0x48304100 0x48304100 0x80 /* ECAP */
  674. 0x48304180 0x48304180 0x80 /* EQEP */
  675. 0x48304200 0x48304200 0x80>; /* EHRPWM */
  676. ecap2: ecap@48304100 {
  677. compatible = "ti,am3352-ecap",
  678. "ti,am33xx-ecap";
  679. #pwm-cells = <3>;
  680. reg = <0x48304100 0x80>;
  681. clocks = <&l4ls_gclk>;
  682. clock-names = "fck";
  683. interrupts = <61>;
  684. interrupt-names = "ecap2";
  685. status = "disabled";
  686. };
  687. ehrpwm2: pwm@48304200 {
  688. compatible = "ti,am3352-ehrpwm",
  689. "ti,am33xx-ehrpwm";
  690. #pwm-cells = <3>;
  691. reg = <0x48304200 0x80>;
  692. clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
  693. clock-names = "tbclk", "fck";
  694. status = "disabled";
  695. };
  696. };
  697. mac: ethernet@4a100000 {
  698. compatible = "ti,am335x-cpsw","ti,cpsw";
  699. ti,hwmods = "cpgmac0";
  700. clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
  701. clock-names = "fck", "cpts";
  702. cpdma_channels = <8>;
  703. ale_entries = <1024>;
  704. bd_ram_size = <0x2000>;
  705. no_bd_ram = <0>;
  706. mac_control = <0x20>;
  707. slaves = <2>;
  708. active_slave = <0>;
  709. cpts_clock_mult = <0x80000000>;
  710. cpts_clock_shift = <29>;
  711. reg = <0x4a100000 0x800
  712. 0x4a101200 0x100>;
  713. #address-cells = <1>;
  714. #size-cells = <1>;
  715. interrupt-parent = <&intc>;
  716. /*
  717. * c0_rx_thresh_pend
  718. * c0_rx_pend
  719. * c0_tx_pend
  720. * c0_misc_pend
  721. */
  722. interrupts = <40 41 42 43>;
  723. ranges;
  724. syscon = <&scm_conf>;
  725. status = "disabled";
  726. davinci_mdio: mdio@4a101000 {
  727. compatible = "ti,cpsw-mdio","ti,davinci_mdio";
  728. #address-cells = <1>;
  729. #size-cells = <0>;
  730. ti,hwmods = "davinci_mdio";
  731. bus_freq = <1000000>;
  732. reg = <0x4a101000 0x100>;
  733. status = "disabled";
  734. };
  735. cpsw_emac0: slave@4a100200 {
  736. /* Filled in by U-Boot */
  737. mac-address = [ 00 00 00 00 00 00 ];
  738. };
  739. cpsw_emac1: slave@4a100300 {
  740. /* Filled in by U-Boot */
  741. mac-address = [ 00 00 00 00 00 00 ];
  742. };
  743. phy_sel: cpsw-phy-sel@44e10650 {
  744. compatible = "ti,am3352-cpsw-phy-sel";
  745. reg= <0x44e10650 0x4>;
  746. reg-names = "gmii-sel";
  747. };
  748. };
  749. ocmcram: ocmcram@40300000 {
  750. compatible = "mmio-sram";
  751. reg = <0x40300000 0x10000>; /* 64k */
  752. };
  753. elm: elm@48080000 {
  754. compatible = "ti,am3352-elm";
  755. reg = <0x48080000 0x2000>;
  756. interrupts = <4>;
  757. ti,hwmods = "elm";
  758. status = "disabled";
  759. };
  760. lcdc: lcdc@4830e000 {
  761. compatible = "ti,am33xx-tilcdc";
  762. reg = <0x4830e000 0x1000>;
  763. interrupt-parent = <&intc>;
  764. interrupts = <36>;
  765. ti,hwmods = "lcdc";
  766. status = "disabled";
  767. };
  768. tscadc: tscadc@44e0d000 {
  769. compatible = "ti,am3359-tscadc";
  770. reg = <0x44e0d000 0x1000>;
  771. interrupt-parent = <&intc>;
  772. interrupts = <16>;
  773. ti,hwmods = "adc_tsc";
  774. status = "disabled";
  775. dmas = <&edma 53 0>, <&edma 57 0>;
  776. dma-names = "fifo0", "fifo1";
  777. tsc {
  778. compatible = "ti,am3359-tsc";
  779. };
  780. am335x_adc: adc {
  781. #io-channel-cells = <1>;
  782. compatible = "ti,am3359-adc";
  783. };
  784. };
  785. gpmc: gpmc@50000000 {
  786. compatible = "ti,am3352-gpmc";
  787. ti,hwmods = "gpmc";
  788. ti,no-idle-on-init;
  789. reg = <0x50000000 0x2000>;
  790. interrupts = <100>;
  791. dmas = <&edma 52 0>;
  792. dma-names = "rxtx";
  793. gpmc,num-cs = <7>;
  794. gpmc,num-waitpins = <2>;
  795. #address-cells = <2>;
  796. #size-cells = <1>;
  797. interrupt-controller;
  798. #interrupt-cells = <2>;
  799. gpio-controller;
  800. #gpio-cells = <2>;
  801. status = "disabled";
  802. };
  803. sham: sham@53100000 {
  804. compatible = "ti,omap4-sham";
  805. ti,hwmods = "sham";
  806. reg = <0x53100000 0x200>;
  807. interrupts = <109>;
  808. dmas = <&edma 36 0>;
  809. dma-names = "rx";
  810. };
  811. aes: aes@53500000 {
  812. compatible = "ti,omap4-aes";
  813. ti,hwmods = "aes";
  814. reg = <0x53500000 0xa0>;
  815. interrupts = <103>;
  816. dmas = <&edma 6 0>,
  817. <&edma 5 0>;
  818. dma-names = "tx", "rx";
  819. };
  820. mcasp0: mcasp@48038000 {
  821. compatible = "ti,am33xx-mcasp-audio";
  822. ti,hwmods = "mcasp0";
  823. reg = <0x48038000 0x2000>,
  824. <0x46000000 0x400000>;
  825. reg-names = "mpu", "dat";
  826. interrupts = <80>, <81>;
  827. interrupt-names = "tx", "rx";
  828. status = "disabled";
  829. dmas = <&edma 8 2>,
  830. <&edma 9 2>;
  831. dma-names = "tx", "rx";
  832. };
  833. mcasp1: mcasp@4803C000 {
  834. compatible = "ti,am33xx-mcasp-audio";
  835. ti,hwmods = "mcasp1";
  836. reg = <0x4803C000 0x2000>,
  837. <0x46400000 0x400000>;
  838. reg-names = "mpu", "dat";
  839. interrupts = <82>, <83>;
  840. interrupt-names = "tx", "rx";
  841. status = "disabled";
  842. dmas = <&edma 10 2>,
  843. <&edma 11 2>;
  844. dma-names = "tx", "rx";
  845. };
  846. rng: rng@48310000 {
  847. compatible = "ti,omap4-rng";
  848. ti,hwmods = "rng";
  849. reg = <0x48310000 0x2000>;
  850. interrupts = <111>;
  851. };
  852. };
  853. };
  854. /include/ "am33xx-clocks.dtsi"