main.c 57 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth)
  61. pending = true;
  62. if (txq->mac80211_qnum >= 0) {
  63. struct list_head *list;
  64. list = &sc->cur_chan->acq[txq->mac80211_qnum];
  65. if (!list_empty(list))
  66. pending = true;
  67. }
  68. spin_unlock_bh(&txq->axq_lock);
  69. return pending;
  70. }
  71. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  72. {
  73. unsigned long flags;
  74. bool ret;
  75. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  76. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  77. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  78. return ret;
  79. }
  80. void ath_ps_full_sleep(unsigned long data)
  81. {
  82. struct ath_softc *sc = (struct ath_softc *) data;
  83. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  84. bool reset;
  85. spin_lock(&common->cc_lock);
  86. ath_hw_cycle_counters_update(common);
  87. spin_unlock(&common->cc_lock);
  88. ath9k_hw_setrxabort(sc->sc_ah, 1);
  89. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  90. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  91. }
  92. void ath9k_ps_wakeup(struct ath_softc *sc)
  93. {
  94. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  95. unsigned long flags;
  96. enum ath9k_power_mode power_mode;
  97. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  98. if (++sc->ps_usecount != 1)
  99. goto unlock;
  100. del_timer_sync(&sc->sleep_timer);
  101. power_mode = sc->sc_ah->power_mode;
  102. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  103. /*
  104. * While the hardware is asleep, the cycle counters contain no
  105. * useful data. Better clear them now so that they don't mess up
  106. * survey data results.
  107. */
  108. if (power_mode != ATH9K_PM_AWAKE) {
  109. spin_lock(&common->cc_lock);
  110. ath_hw_cycle_counters_update(common);
  111. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  112. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  113. spin_unlock(&common->cc_lock);
  114. }
  115. unlock:
  116. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  117. }
  118. void ath9k_ps_restore(struct ath_softc *sc)
  119. {
  120. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  121. enum ath9k_power_mode mode;
  122. unsigned long flags;
  123. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  124. if (--sc->ps_usecount != 0)
  125. goto unlock;
  126. if (sc->ps_idle) {
  127. mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
  128. goto unlock;
  129. }
  130. if (sc->ps_enabled &&
  131. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  132. PS_WAIT_FOR_CAB |
  133. PS_WAIT_FOR_PSPOLL_DATA |
  134. PS_WAIT_FOR_TX_ACK |
  135. PS_WAIT_FOR_ANI))) {
  136. mode = ATH9K_PM_NETWORK_SLEEP;
  137. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  138. ath9k_btcoex_stop_gen_timer(sc);
  139. } else {
  140. goto unlock;
  141. }
  142. spin_lock(&common->cc_lock);
  143. ath_hw_cycle_counters_update(common);
  144. spin_unlock(&common->cc_lock);
  145. ath9k_hw_setpower(sc->sc_ah, mode);
  146. unlock:
  147. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  148. }
  149. static void __ath_cancel_work(struct ath_softc *sc)
  150. {
  151. cancel_work_sync(&sc->paprd_work);
  152. cancel_delayed_work_sync(&sc->tx_complete_work);
  153. cancel_delayed_work_sync(&sc->hw_pll_work);
  154. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  155. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  156. cancel_work_sync(&sc->mci_work);
  157. #endif
  158. }
  159. void ath_cancel_work(struct ath_softc *sc)
  160. {
  161. __ath_cancel_work(sc);
  162. cancel_work_sync(&sc->hw_reset_work);
  163. }
  164. void ath_restart_work(struct ath_softc *sc)
  165. {
  166. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  167. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
  168. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  169. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  170. ath_start_ani(sc);
  171. }
  172. static bool ath_prepare_reset(struct ath_softc *sc)
  173. {
  174. struct ath_hw *ah = sc->sc_ah;
  175. bool ret = true;
  176. ieee80211_stop_queues(sc->hw);
  177. ath_stop_ani(sc);
  178. ath9k_hw_disable_interrupts(ah);
  179. if (!ath_drain_all_txq(sc))
  180. ret = false;
  181. if (!ath_stoprecv(sc))
  182. ret = false;
  183. return ret;
  184. }
  185. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  186. {
  187. struct ath_hw *ah = sc->sc_ah;
  188. struct ath_common *common = ath9k_hw_common(ah);
  189. unsigned long flags;
  190. if (ath_startrecv(sc) != 0) {
  191. ath_err(common, "Unable to restart recv logic\n");
  192. return false;
  193. }
  194. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  195. sc->cur_chan->txpower, &sc->curtxpow);
  196. clear_bit(ATH_OP_HW_RESET, &common->op_flags);
  197. ath9k_hw_set_interrupts(ah);
  198. ath9k_hw_enable_interrupts(ah);
  199. if (!sc->cur_chan->offchannel && start) {
  200. if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
  201. goto work;
  202. if (ah->opmode == NL80211_IFTYPE_STATION &&
  203. test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
  204. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  205. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  206. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  207. } else {
  208. ath9k_set_beacon(sc);
  209. }
  210. work:
  211. ath_restart_work(sc);
  212. ath_txq_schedule_all(sc);
  213. }
  214. sc->gtt_cnt = 0;
  215. ieee80211_wake_queues(sc->hw);
  216. ath9k_p2p_ps_timer(sc);
  217. return true;
  218. }
  219. int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  220. {
  221. struct ath_hw *ah = sc->sc_ah;
  222. struct ath_common *common = ath9k_hw_common(ah);
  223. struct ath9k_hw_cal_data *caldata = NULL;
  224. bool fastcc = true;
  225. int r;
  226. __ath_cancel_work(sc);
  227. tasklet_disable(&sc->intr_tq);
  228. spin_lock_bh(&sc->sc_pcu_lock);
  229. if (!sc->cur_chan->offchannel) {
  230. fastcc = false;
  231. caldata = &sc->caldata;
  232. }
  233. if (!hchan) {
  234. fastcc = false;
  235. hchan = ah->curchan;
  236. }
  237. if (!ath_prepare_reset(sc))
  238. fastcc = false;
  239. if (hchan) {
  240. spin_lock_bh(&sc->chan_lock);
  241. sc->cur_chandef = sc->cur_chan->chandef;
  242. spin_unlock_bh(&sc->chan_lock);
  243. }
  244. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  245. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  246. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  247. if (r) {
  248. ath_err(common,
  249. "Unable to reset channel, reset status %d\n", r);
  250. ath9k_hw_enable_interrupts(ah);
  251. ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
  252. goto out;
  253. }
  254. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  255. sc->cur_chan->offchannel)
  256. ath9k_mci_set_txpower(sc, true, false);
  257. if (!ath_complete_reset(sc, true))
  258. r = -EIO;
  259. out:
  260. spin_unlock_bh(&sc->sc_pcu_lock);
  261. tasklet_enable(&sc->intr_tq);
  262. return r;
  263. }
  264. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  265. struct ieee80211_vif *vif)
  266. {
  267. struct ath_node *an;
  268. an = (struct ath_node *)sta->drv_priv;
  269. an->sc = sc;
  270. an->sta = sta;
  271. an->vif = vif;
  272. memset(&an->key_idx, 0, sizeof(an->key_idx));
  273. ath_tx_node_init(sc, an);
  274. }
  275. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  276. {
  277. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  278. ath_tx_node_cleanup(sc, an);
  279. }
  280. void ath9k_tasklet(unsigned long data)
  281. {
  282. struct ath_softc *sc = (struct ath_softc *)data;
  283. struct ath_hw *ah = sc->sc_ah;
  284. struct ath_common *common = ath9k_hw_common(ah);
  285. enum ath_reset_type type;
  286. unsigned long flags;
  287. u32 status = sc->intrstatus;
  288. u32 rxmask;
  289. ath9k_ps_wakeup(sc);
  290. spin_lock(&sc->sc_pcu_lock);
  291. if (status & ATH9K_INT_FATAL) {
  292. type = RESET_TYPE_FATAL_INT;
  293. ath9k_queue_reset(sc, type);
  294. /*
  295. * Increment the ref. counter here so that
  296. * interrupts are enabled in the reset routine.
  297. */
  298. atomic_inc(&ah->intr_ref_cnt);
  299. ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
  300. goto out;
  301. }
  302. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  303. (status & ATH9K_INT_BB_WATCHDOG)) {
  304. spin_lock(&common->cc_lock);
  305. ath_hw_cycle_counters_update(common);
  306. ar9003_hw_bb_watchdog_dbg_info(ah);
  307. spin_unlock(&common->cc_lock);
  308. if (ar9003_hw_bb_watchdog_check(ah)) {
  309. type = RESET_TYPE_BB_WATCHDOG;
  310. ath9k_queue_reset(sc, type);
  311. /*
  312. * Increment the ref. counter here so that
  313. * interrupts are enabled in the reset routine.
  314. */
  315. atomic_inc(&ah->intr_ref_cnt);
  316. ath_dbg(common, RESET,
  317. "BB_WATCHDOG: Skipping interrupts\n");
  318. goto out;
  319. }
  320. }
  321. if (status & ATH9K_INT_GTT) {
  322. sc->gtt_cnt++;
  323. if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
  324. type = RESET_TYPE_TX_GTT;
  325. ath9k_queue_reset(sc, type);
  326. atomic_inc(&ah->intr_ref_cnt);
  327. ath_dbg(common, RESET,
  328. "GTT: Skipping interrupts\n");
  329. goto out;
  330. }
  331. }
  332. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  333. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  334. /*
  335. * TSF sync does not look correct; remain awake to sync with
  336. * the next Beacon.
  337. */
  338. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  339. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  340. }
  341. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  342. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  343. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  344. ATH9K_INT_RXORN);
  345. else
  346. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  347. if (status & rxmask) {
  348. /* Check for high priority Rx first */
  349. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  350. (status & ATH9K_INT_RXHP))
  351. ath_rx_tasklet(sc, 0, true);
  352. ath_rx_tasklet(sc, 0, false);
  353. }
  354. if (status & ATH9K_INT_TX) {
  355. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  356. /*
  357. * For EDMA chips, TX completion is enabled for the
  358. * beacon queue, so if a beacon has been transmitted
  359. * successfully after a GTT interrupt, the GTT counter
  360. * gets reset to zero here.
  361. */
  362. sc->gtt_cnt = 0;
  363. ath_tx_edma_tasklet(sc);
  364. } else {
  365. ath_tx_tasklet(sc);
  366. }
  367. wake_up(&sc->tx_wait);
  368. }
  369. if (status & ATH9K_INT_GENTIMER)
  370. ath_gen_timer_isr(sc->sc_ah);
  371. ath9k_btcoex_handle_interrupt(sc, status);
  372. /* re-enable hardware interrupt */
  373. ath9k_hw_enable_interrupts(ah);
  374. out:
  375. spin_unlock(&sc->sc_pcu_lock);
  376. ath9k_ps_restore(sc);
  377. }
  378. irqreturn_t ath_isr(int irq, void *dev)
  379. {
  380. #define SCHED_INTR ( \
  381. ATH9K_INT_FATAL | \
  382. ATH9K_INT_BB_WATCHDOG | \
  383. ATH9K_INT_RXORN | \
  384. ATH9K_INT_RXEOL | \
  385. ATH9K_INT_RX | \
  386. ATH9K_INT_RXLP | \
  387. ATH9K_INT_RXHP | \
  388. ATH9K_INT_TX | \
  389. ATH9K_INT_BMISS | \
  390. ATH9K_INT_CST | \
  391. ATH9K_INT_GTT | \
  392. ATH9K_INT_TSFOOR | \
  393. ATH9K_INT_GENTIMER | \
  394. ATH9K_INT_MCI)
  395. struct ath_softc *sc = dev;
  396. struct ath_hw *ah = sc->sc_ah;
  397. struct ath_common *common = ath9k_hw_common(ah);
  398. enum ath9k_int status;
  399. u32 sync_cause = 0;
  400. bool sched = false;
  401. /*
  402. * The hardware is not ready/present, don't
  403. * touch anything. Note this can happen early
  404. * on if the IRQ is shared.
  405. */
  406. if (test_bit(ATH_OP_INVALID, &common->op_flags))
  407. return IRQ_NONE;
  408. /* shared irq, not for us */
  409. if (!ath9k_hw_intrpend(ah))
  410. return IRQ_NONE;
  411. if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
  412. ath9k_hw_kill_interrupts(ah);
  413. return IRQ_HANDLED;
  414. }
  415. /*
  416. * Figure out the reason(s) for the interrupt. Note
  417. * that the hal returns a pseudo-ISR that may include
  418. * bits we haven't explicitly enabled so we mask the
  419. * value to insure we only process bits we requested.
  420. */
  421. ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
  422. ath9k_debug_sync_cause(sc, sync_cause);
  423. status &= ah->imask; /* discard unasked-for bits */
  424. /*
  425. * If there are no status bits set, then this interrupt was not
  426. * for me (should have been caught above).
  427. */
  428. if (!status)
  429. return IRQ_NONE;
  430. /* Cache the status */
  431. sc->intrstatus = status;
  432. if (status & SCHED_INTR)
  433. sched = true;
  434. /*
  435. * If a FATAL or RXORN interrupt is received, we have to reset the
  436. * chip immediately.
  437. */
  438. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  439. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  440. goto chip_reset;
  441. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  442. (status & ATH9K_INT_BB_WATCHDOG))
  443. goto chip_reset;
  444. #ifdef CONFIG_ATH9K_WOW
  445. if (status & ATH9K_INT_BMISS) {
  446. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  447. atomic_inc(&sc->wow_got_bmiss_intr);
  448. atomic_dec(&sc->wow_sleep_proc_intr);
  449. }
  450. }
  451. #endif
  452. if (status & ATH9K_INT_SWBA)
  453. tasklet_schedule(&sc->bcon_tasklet);
  454. if (status & ATH9K_INT_TXURN)
  455. ath9k_hw_updatetxtriglevel(ah, true);
  456. if (status & ATH9K_INT_RXEOL) {
  457. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  458. ath9k_hw_set_interrupts(ah);
  459. }
  460. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  461. if (status & ATH9K_INT_TIM_TIMER) {
  462. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  463. goto chip_reset;
  464. /* Clear RxAbort bit so that we can
  465. * receive frames */
  466. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  467. spin_lock(&sc->sc_pm_lock);
  468. ath9k_hw_setrxabort(sc->sc_ah, 0);
  469. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  470. spin_unlock(&sc->sc_pm_lock);
  471. }
  472. chip_reset:
  473. ath_debug_stat_interrupt(sc, status);
  474. if (sched) {
  475. /* turn off every interrupt */
  476. ath9k_hw_disable_interrupts(ah);
  477. tasklet_schedule(&sc->intr_tq);
  478. }
  479. return IRQ_HANDLED;
  480. #undef SCHED_INTR
  481. }
  482. int ath_reset(struct ath_softc *sc)
  483. {
  484. int r;
  485. ath9k_ps_wakeup(sc);
  486. r = ath_reset_internal(sc, NULL);
  487. ath9k_ps_restore(sc);
  488. return r;
  489. }
  490. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  491. {
  492. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  493. #ifdef CONFIG_ATH9K_DEBUGFS
  494. RESET_STAT_INC(sc, type);
  495. #endif
  496. set_bit(ATH_OP_HW_RESET, &common->op_flags);
  497. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  498. }
  499. void ath_reset_work(struct work_struct *work)
  500. {
  501. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  502. ath_reset(sc);
  503. }
  504. /**********************/
  505. /* mac80211 callbacks */
  506. /**********************/
  507. static int ath9k_start(struct ieee80211_hw *hw)
  508. {
  509. struct ath_softc *sc = hw->priv;
  510. struct ath_hw *ah = sc->sc_ah;
  511. struct ath_common *common = ath9k_hw_common(ah);
  512. struct ieee80211_channel *curchan = hw->conf.chandef.chan;
  513. struct ath_chanctx *ctx = sc->cur_chan;
  514. struct ath9k_channel *init_channel;
  515. int r;
  516. ath_dbg(common, CONFIG,
  517. "Starting driver with initial channel: %d MHz\n",
  518. curchan->center_freq);
  519. ath9k_ps_wakeup(sc);
  520. mutex_lock(&sc->mutex);
  521. init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
  522. sc->cur_chandef = hw->conf.chandef;
  523. /* Reset SERDES registers */
  524. ath9k_hw_configpcipowersave(ah, false);
  525. /*
  526. * The basic interface to setting the hardware in a good
  527. * state is ``reset''. On return the hardware is known to
  528. * be powered up and with interrupts disabled. This must
  529. * be followed by initialization of the appropriate bits
  530. * and then setup of the interrupt mask.
  531. */
  532. spin_lock_bh(&sc->sc_pcu_lock);
  533. atomic_set(&ah->intr_ref_cnt, -1);
  534. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  535. if (r) {
  536. ath_err(common,
  537. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  538. r, curchan->center_freq);
  539. ah->reset_power_on = false;
  540. }
  541. /* Setup our intr mask. */
  542. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  543. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  544. ATH9K_INT_GLOBAL;
  545. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  546. ah->imask |= ATH9K_INT_RXHP |
  547. ATH9K_INT_RXLP;
  548. else
  549. ah->imask |= ATH9K_INT_RX;
  550. if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
  551. ah->imask |= ATH9K_INT_BB_WATCHDOG;
  552. /*
  553. * Enable GTT interrupts only for AR9003/AR9004 chips
  554. * for now.
  555. */
  556. if (AR_SREV_9300_20_OR_LATER(ah))
  557. ah->imask |= ATH9K_INT_GTT;
  558. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  559. ah->imask |= ATH9K_INT_CST;
  560. ath_mci_enable(sc);
  561. clear_bit(ATH_OP_INVALID, &common->op_flags);
  562. sc->sc_ah->is_monitoring = false;
  563. if (!ath_complete_reset(sc, false))
  564. ah->reset_power_on = false;
  565. if (ah->led_pin >= 0) {
  566. ath9k_hw_cfg_output(ah, ah->led_pin,
  567. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  568. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  569. }
  570. /*
  571. * Reset key cache to sane defaults (all entries cleared) instead of
  572. * semi-random values after suspend/resume.
  573. */
  574. ath9k_cmn_init_crypto(sc->sc_ah);
  575. ath9k_hw_reset_tsf(ah);
  576. spin_unlock_bh(&sc->sc_pcu_lock);
  577. mutex_unlock(&sc->mutex);
  578. ath9k_ps_restore(sc);
  579. return 0;
  580. }
  581. static void ath9k_tx(struct ieee80211_hw *hw,
  582. struct ieee80211_tx_control *control,
  583. struct sk_buff *skb)
  584. {
  585. struct ath_softc *sc = hw->priv;
  586. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  587. struct ath_tx_control txctl;
  588. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  589. unsigned long flags;
  590. if (sc->ps_enabled) {
  591. /*
  592. * mac80211 does not set PM field for normal data frames, so we
  593. * need to update that based on the current PS mode.
  594. */
  595. if (ieee80211_is_data(hdr->frame_control) &&
  596. !ieee80211_is_nullfunc(hdr->frame_control) &&
  597. !ieee80211_has_pm(hdr->frame_control)) {
  598. ath_dbg(common, PS,
  599. "Add PM=1 for a TX frame while in PS mode\n");
  600. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  601. }
  602. }
  603. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  604. /*
  605. * We are using PS-Poll and mac80211 can request TX while in
  606. * power save mode. Need to wake up hardware for the TX to be
  607. * completed and if needed, also for RX of buffered frames.
  608. */
  609. ath9k_ps_wakeup(sc);
  610. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  611. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  612. ath9k_hw_setrxabort(sc->sc_ah, 0);
  613. if (ieee80211_is_pspoll(hdr->frame_control)) {
  614. ath_dbg(common, PS,
  615. "Sending PS-Poll to pick a buffered frame\n");
  616. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  617. } else {
  618. ath_dbg(common, PS, "Wake up to complete TX\n");
  619. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  620. }
  621. /*
  622. * The actual restore operation will happen only after
  623. * the ps_flags bit is cleared. We are just dropping
  624. * the ps_usecount here.
  625. */
  626. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  627. ath9k_ps_restore(sc);
  628. }
  629. /*
  630. * Cannot tx while the hardware is in full sleep, it first needs a full
  631. * chip reset to recover from that
  632. */
  633. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  634. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  635. goto exit;
  636. }
  637. memset(&txctl, 0, sizeof(struct ath_tx_control));
  638. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  639. txctl.sta = control->sta;
  640. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  641. if (ath_tx_start(hw, skb, &txctl) != 0) {
  642. ath_dbg(common, XMIT, "TX failed\n");
  643. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  644. goto exit;
  645. }
  646. return;
  647. exit:
  648. ieee80211_free_txskb(hw, skb);
  649. }
  650. static void ath9k_stop(struct ieee80211_hw *hw)
  651. {
  652. struct ath_softc *sc = hw->priv;
  653. struct ath_hw *ah = sc->sc_ah;
  654. struct ath_common *common = ath9k_hw_common(ah);
  655. bool prev_idle;
  656. cancel_work_sync(&sc->chanctx_work);
  657. mutex_lock(&sc->mutex);
  658. ath_cancel_work(sc);
  659. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  660. ath_dbg(common, ANY, "Device not present\n");
  661. mutex_unlock(&sc->mutex);
  662. return;
  663. }
  664. /* Ensure HW is awake when we try to shut it down. */
  665. ath9k_ps_wakeup(sc);
  666. spin_lock_bh(&sc->sc_pcu_lock);
  667. /* prevent tasklets to enable interrupts once we disable them */
  668. ah->imask &= ~ATH9K_INT_GLOBAL;
  669. /* make sure h/w will not generate any interrupt
  670. * before setting the invalid flag. */
  671. ath9k_hw_disable_interrupts(ah);
  672. spin_unlock_bh(&sc->sc_pcu_lock);
  673. /* we can now sync irq and kill any running tasklets, since we already
  674. * disabled interrupts and not holding a spin lock */
  675. synchronize_irq(sc->irq);
  676. tasklet_kill(&sc->intr_tq);
  677. tasklet_kill(&sc->bcon_tasklet);
  678. prev_idle = sc->ps_idle;
  679. sc->ps_idle = true;
  680. spin_lock_bh(&sc->sc_pcu_lock);
  681. if (ah->led_pin >= 0) {
  682. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  683. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  684. }
  685. ath_prepare_reset(sc);
  686. if (sc->rx.frag) {
  687. dev_kfree_skb_any(sc->rx.frag);
  688. sc->rx.frag = NULL;
  689. }
  690. if (!ah->curchan)
  691. ah->curchan = ath9k_cmn_get_channel(hw, ah,
  692. &sc->cur_chan->chandef);
  693. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  694. ath9k_hw_phy_disable(ah);
  695. ath9k_hw_configpcipowersave(ah, true);
  696. spin_unlock_bh(&sc->sc_pcu_lock);
  697. ath9k_ps_restore(sc);
  698. set_bit(ATH_OP_INVALID, &common->op_flags);
  699. sc->ps_idle = prev_idle;
  700. mutex_unlock(&sc->mutex);
  701. ath_dbg(common, CONFIG, "Driver halt\n");
  702. }
  703. static bool ath9k_uses_beacons(int type)
  704. {
  705. switch (type) {
  706. case NL80211_IFTYPE_AP:
  707. case NL80211_IFTYPE_ADHOC:
  708. case NL80211_IFTYPE_MESH_POINT:
  709. return true;
  710. default:
  711. return false;
  712. }
  713. }
  714. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  715. {
  716. struct ath9k_vif_iter_data *iter_data = data;
  717. int i;
  718. if (iter_data->has_hw_macaddr) {
  719. for (i = 0; i < ETH_ALEN; i++)
  720. iter_data->mask[i] &=
  721. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  722. } else {
  723. memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
  724. iter_data->has_hw_macaddr = true;
  725. }
  726. switch (vif->type) {
  727. case NL80211_IFTYPE_AP:
  728. iter_data->naps++;
  729. break;
  730. case NL80211_IFTYPE_STATION:
  731. iter_data->nstations++;
  732. break;
  733. case NL80211_IFTYPE_ADHOC:
  734. iter_data->nadhocs++;
  735. break;
  736. case NL80211_IFTYPE_MESH_POINT:
  737. iter_data->nmeshes++;
  738. break;
  739. case NL80211_IFTYPE_WDS:
  740. iter_data->nwds++;
  741. break;
  742. default:
  743. break;
  744. }
  745. }
  746. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  747. {
  748. struct ath_softc *sc = data;
  749. struct ath_vif *avp = (void *)vif->drv_priv;
  750. if (vif->type != NL80211_IFTYPE_STATION)
  751. return;
  752. if (avp->primary_sta_vif)
  753. ath9k_set_assoc_state(sc, vif);
  754. }
  755. /* Called with sc->mutex held. */
  756. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  757. struct ieee80211_vif *vif,
  758. struct ath9k_vif_iter_data *iter_data)
  759. {
  760. struct ath_softc *sc = hw->priv;
  761. struct ath_hw *ah = sc->sc_ah;
  762. struct ath_common *common = ath9k_hw_common(ah);
  763. /*
  764. * Pick the MAC address of the first interface as the new hardware
  765. * MAC address. The hardware will use it together with the BSSID mask
  766. * when matching addresses.
  767. */
  768. memset(iter_data, 0, sizeof(*iter_data));
  769. memset(&iter_data->mask, 0xff, ETH_ALEN);
  770. if (vif)
  771. ath9k_vif_iter(iter_data, vif->addr, vif);
  772. /* Get list of all active MAC addresses */
  773. ieee80211_iterate_active_interfaces_atomic(
  774. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  775. ath9k_vif_iter, iter_data);
  776. memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN);
  777. }
  778. /* Called with sc->mutex held. */
  779. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  780. struct ieee80211_vif *vif)
  781. {
  782. struct ath_softc *sc = hw->priv;
  783. struct ath_hw *ah = sc->sc_ah;
  784. struct ath_common *common = ath9k_hw_common(ah);
  785. struct ath9k_vif_iter_data iter_data;
  786. enum nl80211_iftype old_opmode = ah->opmode;
  787. ath9k_calculate_iter_data(hw, vif, &iter_data);
  788. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  789. ath_hw_setbssidmask(common);
  790. if (iter_data.naps > 0) {
  791. ath9k_hw_set_tsfadjust(ah, true);
  792. ah->opmode = NL80211_IFTYPE_AP;
  793. } else {
  794. ath9k_hw_set_tsfadjust(ah, false);
  795. if (iter_data.nmeshes)
  796. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  797. else if (iter_data.nwds)
  798. ah->opmode = NL80211_IFTYPE_AP;
  799. else if (iter_data.nadhocs)
  800. ah->opmode = NL80211_IFTYPE_ADHOC;
  801. else
  802. ah->opmode = NL80211_IFTYPE_STATION;
  803. }
  804. ath9k_hw_setopmode(ah);
  805. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  806. ah->imask |= ATH9K_INT_TSFOOR;
  807. else
  808. ah->imask &= ~ATH9K_INT_TSFOOR;
  809. ath9k_hw_set_interrupts(ah);
  810. /*
  811. * If we are changing the opmode to STATION,
  812. * a beacon sync needs to be done.
  813. */
  814. if (ah->opmode == NL80211_IFTYPE_STATION &&
  815. old_opmode == NL80211_IFTYPE_AP &&
  816. test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
  817. ieee80211_iterate_active_interfaces_atomic(
  818. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  819. ath9k_sta_vif_iter, sc);
  820. }
  821. }
  822. static int ath9k_add_interface(struct ieee80211_hw *hw,
  823. struct ieee80211_vif *vif)
  824. {
  825. struct ath_softc *sc = hw->priv;
  826. struct ath_hw *ah = sc->sc_ah;
  827. struct ath_common *common = ath9k_hw_common(ah);
  828. struct ath_vif *avp = (void *)vif->drv_priv;
  829. struct ath_node *an = &avp->mcast_node;
  830. mutex_lock(&sc->mutex);
  831. if (config_enabled(CONFIG_ATH9K_TX99)) {
  832. if (sc->nvifs >= 1) {
  833. mutex_unlock(&sc->mutex);
  834. return -EOPNOTSUPP;
  835. }
  836. sc->tx99_vif = vif;
  837. }
  838. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  839. sc->nvifs++;
  840. ath9k_ps_wakeup(sc);
  841. ath9k_calculate_summary_state(hw, vif);
  842. ath9k_ps_restore(sc);
  843. if (ath9k_uses_beacons(vif->type))
  844. ath9k_beacon_assign_slot(sc, vif);
  845. avp->vif = vif;
  846. /* XXX - will be removed once chanctx ops are added */
  847. avp->chanctx = sc->cur_chan;
  848. list_add_tail(&avp->list, &sc->cur_chan->vifs);
  849. ath_chanctx_check_active(sc, avp->chanctx);
  850. an->sc = sc;
  851. an->sta = NULL;
  852. an->vif = vif;
  853. an->no_ps_filter = true;
  854. ath_tx_node_init(sc, an);
  855. mutex_unlock(&sc->mutex);
  856. return 0;
  857. }
  858. static int ath9k_change_interface(struct ieee80211_hw *hw,
  859. struct ieee80211_vif *vif,
  860. enum nl80211_iftype new_type,
  861. bool p2p)
  862. {
  863. struct ath_softc *sc = hw->priv;
  864. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  865. struct ath_vif *avp = (void *)vif->drv_priv;
  866. mutex_lock(&sc->mutex);
  867. if (config_enabled(CONFIG_ATH9K_TX99)) {
  868. mutex_unlock(&sc->mutex);
  869. return -EOPNOTSUPP;
  870. }
  871. ath_dbg(common, CONFIG, "Change Interface\n");
  872. if (ath9k_uses_beacons(vif->type))
  873. ath9k_beacon_remove_slot(sc, vif);
  874. vif->type = new_type;
  875. vif->p2p = p2p;
  876. ath9k_ps_wakeup(sc);
  877. ath9k_calculate_summary_state(hw, vif);
  878. ath9k_ps_restore(sc);
  879. if (ath9k_uses_beacons(vif->type))
  880. ath9k_beacon_assign_slot(sc, vif);
  881. ath_chanctx_check_active(sc, avp->chanctx);
  882. mutex_unlock(&sc->mutex);
  883. return 0;
  884. }
  885. static void
  886. ath9k_update_p2p_ps_timer(struct ath_softc *sc, struct ath_vif *avp)
  887. {
  888. struct ath_hw *ah = sc->sc_ah;
  889. s32 tsf, target_tsf;
  890. if (!avp || !avp->noa.has_next_tsf)
  891. return;
  892. ath9k_hw_gen_timer_stop(ah, sc->p2p_ps_timer);
  893. tsf = ath9k_hw_gettsf32(sc->sc_ah);
  894. target_tsf = avp->noa.next_tsf;
  895. if (!avp->noa.absent)
  896. target_tsf -= ATH_P2P_PS_STOP_TIME;
  897. if (target_tsf - tsf < ATH_P2P_PS_STOP_TIME)
  898. target_tsf = tsf + ATH_P2P_PS_STOP_TIME;
  899. ath9k_hw_gen_timer_start(ah, sc->p2p_ps_timer, (u32) target_tsf, 1000000);
  900. }
  901. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  902. struct ieee80211_vif *vif)
  903. {
  904. struct ath_softc *sc = hw->priv;
  905. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  906. struct ath_vif *avp = (void *)vif->drv_priv;
  907. ath_dbg(common, CONFIG, "Detach Interface\n");
  908. mutex_lock(&sc->mutex);
  909. spin_lock_bh(&sc->sc_pcu_lock);
  910. if (avp == sc->p2p_ps_vif) {
  911. sc->p2p_ps_vif = NULL;
  912. ath9k_update_p2p_ps_timer(sc, NULL);
  913. }
  914. spin_unlock_bh(&sc->sc_pcu_lock);
  915. list_del(&avp->list);
  916. sc->nvifs--;
  917. sc->tx99_vif = NULL;
  918. if (ath9k_uses_beacons(vif->type))
  919. ath9k_beacon_remove_slot(sc, vif);
  920. ath9k_ps_wakeup(sc);
  921. ath9k_calculate_summary_state(hw, NULL);
  922. ath9k_ps_restore(sc);
  923. ath_tx_node_cleanup(sc, &avp->mcast_node);
  924. ath_chanctx_check_active(sc, avp->chanctx);
  925. mutex_unlock(&sc->mutex);
  926. }
  927. static void ath9k_enable_ps(struct ath_softc *sc)
  928. {
  929. struct ath_hw *ah = sc->sc_ah;
  930. struct ath_common *common = ath9k_hw_common(ah);
  931. if (config_enabled(CONFIG_ATH9K_TX99))
  932. return;
  933. sc->ps_enabled = true;
  934. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  935. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  936. ah->imask |= ATH9K_INT_TIM_TIMER;
  937. ath9k_hw_set_interrupts(ah);
  938. }
  939. ath9k_hw_setrxabort(ah, 1);
  940. }
  941. ath_dbg(common, PS, "PowerSave enabled\n");
  942. }
  943. static void ath9k_disable_ps(struct ath_softc *sc)
  944. {
  945. struct ath_hw *ah = sc->sc_ah;
  946. struct ath_common *common = ath9k_hw_common(ah);
  947. if (config_enabled(CONFIG_ATH9K_TX99))
  948. return;
  949. sc->ps_enabled = false;
  950. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  951. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  952. ath9k_hw_setrxabort(ah, 0);
  953. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  954. PS_WAIT_FOR_CAB |
  955. PS_WAIT_FOR_PSPOLL_DATA |
  956. PS_WAIT_FOR_TX_ACK);
  957. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  958. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  959. ath9k_hw_set_interrupts(ah);
  960. }
  961. }
  962. ath_dbg(common, PS, "PowerSave disabled\n");
  963. }
  964. void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
  965. {
  966. struct ath_softc *sc = hw->priv;
  967. struct ath_hw *ah = sc->sc_ah;
  968. struct ath_common *common = ath9k_hw_common(ah);
  969. u32 rxfilter;
  970. if (config_enabled(CONFIG_ATH9K_TX99))
  971. return;
  972. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  973. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  974. return;
  975. }
  976. ath9k_ps_wakeup(sc);
  977. rxfilter = ath9k_hw_getrxfilter(ah);
  978. ath9k_hw_setrxfilter(ah, rxfilter |
  979. ATH9K_RX_FILTER_PHYRADAR |
  980. ATH9K_RX_FILTER_PHYERR);
  981. /* TODO: usually this should not be neccesary, but for some reason
  982. * (or in some mode?) the trigger must be called after the
  983. * configuration, otherwise the register will have its values reset
  984. * (on my ar9220 to value 0x01002310)
  985. */
  986. ath9k_spectral_scan_config(hw, sc->spectral_mode);
  987. ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
  988. ath9k_ps_restore(sc);
  989. }
  990. int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
  991. enum spectral_mode spectral_mode)
  992. {
  993. struct ath_softc *sc = hw->priv;
  994. struct ath_hw *ah = sc->sc_ah;
  995. struct ath_common *common = ath9k_hw_common(ah);
  996. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  997. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  998. return -1;
  999. }
  1000. switch (spectral_mode) {
  1001. case SPECTRAL_DISABLED:
  1002. sc->spec_config.enabled = 0;
  1003. break;
  1004. case SPECTRAL_BACKGROUND:
  1005. /* send endless samples.
  1006. * TODO: is this really useful for "background"?
  1007. */
  1008. sc->spec_config.endless = 1;
  1009. sc->spec_config.enabled = 1;
  1010. break;
  1011. case SPECTRAL_CHANSCAN:
  1012. case SPECTRAL_MANUAL:
  1013. sc->spec_config.endless = 0;
  1014. sc->spec_config.enabled = 1;
  1015. break;
  1016. default:
  1017. return -1;
  1018. }
  1019. ath9k_ps_wakeup(sc);
  1020. ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
  1021. ath9k_ps_restore(sc);
  1022. sc->spectral_mode = spectral_mode;
  1023. return 0;
  1024. }
  1025. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1026. {
  1027. struct ath_softc *sc = hw->priv;
  1028. struct ath_hw *ah = sc->sc_ah;
  1029. struct ath_common *common = ath9k_hw_common(ah);
  1030. struct ieee80211_conf *conf = &hw->conf;
  1031. struct ath_chanctx *ctx = sc->cur_chan;
  1032. bool reset_channel = false;
  1033. ath9k_ps_wakeup(sc);
  1034. mutex_lock(&sc->mutex);
  1035. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1036. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1037. if (sc->ps_idle) {
  1038. ath_cancel_work(sc);
  1039. ath9k_stop_btcoex(sc);
  1040. } else {
  1041. ath9k_start_btcoex(sc);
  1042. /*
  1043. * The chip needs a reset to properly wake up from
  1044. * full sleep
  1045. */
  1046. reset_channel = ah->chip_fullsleep;
  1047. }
  1048. }
  1049. /*
  1050. * We just prepare to enable PS. We have to wait until our AP has
  1051. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1052. * those ACKs and end up retransmitting the same null data frames.
  1053. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1054. */
  1055. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1056. unsigned long flags;
  1057. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1058. if (conf->flags & IEEE80211_CONF_PS)
  1059. ath9k_enable_ps(sc);
  1060. else
  1061. ath9k_disable_ps(sc);
  1062. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1063. }
  1064. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1065. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1066. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1067. sc->sc_ah->is_monitoring = true;
  1068. } else {
  1069. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1070. sc->sc_ah->is_monitoring = false;
  1071. }
  1072. }
  1073. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  1074. ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
  1075. ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
  1076. }
  1077. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1078. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1079. sc->cur_chan->txpower = 2 * conf->power_level;
  1080. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1081. sc->cur_chan->txpower, &sc->curtxpow);
  1082. }
  1083. mutex_unlock(&sc->mutex);
  1084. ath9k_ps_restore(sc);
  1085. return 0;
  1086. }
  1087. #define SUPPORTED_FILTERS \
  1088. (FIF_PROMISC_IN_BSS | \
  1089. FIF_ALLMULTI | \
  1090. FIF_CONTROL | \
  1091. FIF_PSPOLL | \
  1092. FIF_OTHER_BSS | \
  1093. FIF_BCN_PRBRESP_PROMISC | \
  1094. FIF_PROBE_REQ | \
  1095. FIF_FCSFAIL)
  1096. /* FIXME: sc->sc_full_reset ? */
  1097. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1098. unsigned int changed_flags,
  1099. unsigned int *total_flags,
  1100. u64 multicast)
  1101. {
  1102. struct ath_softc *sc = hw->priv;
  1103. u32 rfilt;
  1104. changed_flags &= SUPPORTED_FILTERS;
  1105. *total_flags &= SUPPORTED_FILTERS;
  1106. sc->rx.rxfilter = *total_flags;
  1107. ath9k_ps_wakeup(sc);
  1108. rfilt = ath_calcrxfilter(sc);
  1109. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1110. ath9k_ps_restore(sc);
  1111. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1112. rfilt);
  1113. }
  1114. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1115. struct ieee80211_vif *vif,
  1116. struct ieee80211_sta *sta)
  1117. {
  1118. struct ath_softc *sc = hw->priv;
  1119. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1120. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1121. struct ieee80211_key_conf ps_key = { };
  1122. int key;
  1123. ath_node_attach(sc, sta, vif);
  1124. if (vif->type != NL80211_IFTYPE_AP &&
  1125. vif->type != NL80211_IFTYPE_AP_VLAN)
  1126. return 0;
  1127. key = ath_key_config(common, vif, sta, &ps_key);
  1128. if (key > 0) {
  1129. an->ps_key = key;
  1130. an->key_idx[0] = key;
  1131. }
  1132. return 0;
  1133. }
  1134. static void ath9k_del_ps_key(struct ath_softc *sc,
  1135. struct ieee80211_vif *vif,
  1136. struct ieee80211_sta *sta)
  1137. {
  1138. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1139. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1140. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1141. if (!an->ps_key)
  1142. return;
  1143. ath_key_delete(common, &ps_key);
  1144. an->ps_key = 0;
  1145. an->key_idx[0] = 0;
  1146. }
  1147. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1148. struct ieee80211_vif *vif,
  1149. struct ieee80211_sta *sta)
  1150. {
  1151. struct ath_softc *sc = hw->priv;
  1152. ath9k_del_ps_key(sc, vif, sta);
  1153. ath_node_detach(sc, sta);
  1154. return 0;
  1155. }
  1156. static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
  1157. struct ath_node *an,
  1158. bool set)
  1159. {
  1160. int i;
  1161. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1162. if (!an->key_idx[i])
  1163. continue;
  1164. ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
  1165. }
  1166. }
  1167. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1168. struct ieee80211_vif *vif,
  1169. enum sta_notify_cmd cmd,
  1170. struct ieee80211_sta *sta)
  1171. {
  1172. struct ath_softc *sc = hw->priv;
  1173. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1174. switch (cmd) {
  1175. case STA_NOTIFY_SLEEP:
  1176. an->sleeping = true;
  1177. ath_tx_aggr_sleep(sta, sc, an);
  1178. ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
  1179. break;
  1180. case STA_NOTIFY_AWAKE:
  1181. ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
  1182. an->sleeping = false;
  1183. ath_tx_aggr_wakeup(sc, an);
  1184. break;
  1185. }
  1186. }
  1187. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1188. struct ieee80211_vif *vif, u16 queue,
  1189. const struct ieee80211_tx_queue_params *params)
  1190. {
  1191. struct ath_softc *sc = hw->priv;
  1192. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1193. struct ath_txq *txq;
  1194. struct ath9k_tx_queue_info qi;
  1195. int ret = 0;
  1196. if (queue >= IEEE80211_NUM_ACS)
  1197. return 0;
  1198. txq = sc->tx.txq_map[queue];
  1199. ath9k_ps_wakeup(sc);
  1200. mutex_lock(&sc->mutex);
  1201. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1202. qi.tqi_aifs = params->aifs;
  1203. qi.tqi_cwmin = params->cw_min;
  1204. qi.tqi_cwmax = params->cw_max;
  1205. qi.tqi_burstTime = params->txop * 32;
  1206. ath_dbg(common, CONFIG,
  1207. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1208. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1209. params->cw_max, params->txop);
  1210. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1211. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1212. if (ret)
  1213. ath_err(common, "TXQ Update failed\n");
  1214. mutex_unlock(&sc->mutex);
  1215. ath9k_ps_restore(sc);
  1216. return ret;
  1217. }
  1218. static int ath9k_set_key(struct ieee80211_hw *hw,
  1219. enum set_key_cmd cmd,
  1220. struct ieee80211_vif *vif,
  1221. struct ieee80211_sta *sta,
  1222. struct ieee80211_key_conf *key)
  1223. {
  1224. struct ath_softc *sc = hw->priv;
  1225. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1226. struct ath_node *an = NULL;
  1227. int ret = 0, i;
  1228. if (ath9k_modparam_nohwcrypt)
  1229. return -ENOSPC;
  1230. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1231. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1232. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1233. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1234. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1235. /*
  1236. * For now, disable hw crypto for the RSN IBSS group keys. This
  1237. * could be optimized in the future to use a modified key cache
  1238. * design to support per-STA RX GTK, but until that gets
  1239. * implemented, use of software crypto for group addressed
  1240. * frames is a acceptable to allow RSN IBSS to be used.
  1241. */
  1242. return -EOPNOTSUPP;
  1243. }
  1244. mutex_lock(&sc->mutex);
  1245. ath9k_ps_wakeup(sc);
  1246. ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
  1247. if (sta)
  1248. an = (struct ath_node *)sta->drv_priv;
  1249. switch (cmd) {
  1250. case SET_KEY:
  1251. if (sta)
  1252. ath9k_del_ps_key(sc, vif, sta);
  1253. key->hw_key_idx = 0;
  1254. ret = ath_key_config(common, vif, sta, key);
  1255. if (ret >= 0) {
  1256. key->hw_key_idx = ret;
  1257. /* push IV and Michael MIC generation to stack */
  1258. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1259. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1260. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1261. if (sc->sc_ah->sw_mgmt_crypto &&
  1262. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1263. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1264. ret = 0;
  1265. }
  1266. if (an && key->hw_key_idx) {
  1267. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1268. if (an->key_idx[i])
  1269. continue;
  1270. an->key_idx[i] = key->hw_key_idx;
  1271. break;
  1272. }
  1273. WARN_ON(i == ARRAY_SIZE(an->key_idx));
  1274. }
  1275. break;
  1276. case DISABLE_KEY:
  1277. ath_key_delete(common, key);
  1278. if (an) {
  1279. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1280. if (an->key_idx[i] != key->hw_key_idx)
  1281. continue;
  1282. an->key_idx[i] = 0;
  1283. break;
  1284. }
  1285. }
  1286. key->hw_key_idx = 0;
  1287. break;
  1288. default:
  1289. ret = -EINVAL;
  1290. }
  1291. ath9k_ps_restore(sc);
  1292. mutex_unlock(&sc->mutex);
  1293. return ret;
  1294. }
  1295. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1296. struct ieee80211_vif *vif)
  1297. {
  1298. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1299. struct ath_vif *avp = (void *)vif->drv_priv;
  1300. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1301. unsigned long flags;
  1302. set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  1303. avp->primary_sta_vif = true;
  1304. /*
  1305. * Set the AID, BSSID and do beacon-sync only when
  1306. * the HW opmode is STATION.
  1307. *
  1308. * But the primary bit is set above in any case.
  1309. */
  1310. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1311. return;
  1312. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1313. common->curaid = bss_conf->aid;
  1314. ath9k_hw_write_associd(sc->sc_ah);
  1315. common->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1316. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1317. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1318. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1319. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1320. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1321. ath9k_mci_update_wlan_channels(sc, false);
  1322. ath_dbg(common, CONFIG,
  1323. "Primary Station interface: %pM, BSSID: %pM\n",
  1324. vif->addr, common->curbssid);
  1325. }
  1326. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1327. {
  1328. struct ath_softc *sc = data;
  1329. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1330. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1331. if (test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags))
  1332. return;
  1333. if (bss_conf->assoc)
  1334. ath9k_set_assoc_state(sc, vif);
  1335. }
  1336. void ath9k_p2p_ps_timer(void *priv)
  1337. {
  1338. struct ath_softc *sc = priv;
  1339. struct ath_vif *avp = sc->p2p_ps_vif;
  1340. struct ieee80211_vif *vif;
  1341. struct ieee80211_sta *sta;
  1342. struct ath_node *an;
  1343. u32 tsf;
  1344. if (!avp)
  1345. return;
  1346. tsf = ath9k_hw_gettsf32(sc->sc_ah);
  1347. if (!avp->noa.absent)
  1348. tsf += ATH_P2P_PS_STOP_TIME;
  1349. if (!avp->noa.has_next_tsf ||
  1350. avp->noa.next_tsf - tsf > BIT(31))
  1351. ieee80211_update_p2p_noa(&avp->noa, tsf);
  1352. ath9k_update_p2p_ps_timer(sc, avp);
  1353. rcu_read_lock();
  1354. vif = avp->vif;
  1355. sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
  1356. if (!sta)
  1357. goto out;
  1358. an = (void *) sta->drv_priv;
  1359. if (an->sleeping == !!avp->noa.absent)
  1360. goto out;
  1361. an->sleeping = avp->noa.absent;
  1362. if (an->sleeping)
  1363. ath_tx_aggr_sleep(sta, sc, an);
  1364. else
  1365. ath_tx_aggr_wakeup(sc, an);
  1366. out:
  1367. rcu_read_unlock();
  1368. }
  1369. void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif)
  1370. {
  1371. struct ath_vif *avp = (void *)vif->drv_priv;
  1372. u32 tsf;
  1373. if (!sc->p2p_ps_timer)
  1374. return;
  1375. if (vif->type != NL80211_IFTYPE_STATION || !vif->p2p)
  1376. return;
  1377. sc->p2p_ps_vif = avp;
  1378. tsf = ath9k_hw_gettsf32(sc->sc_ah);
  1379. ieee80211_parse_p2p_noa(&vif->bss_conf.p2p_noa_attr, &avp->noa, tsf);
  1380. ath9k_update_p2p_ps_timer(sc, avp);
  1381. }
  1382. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1383. struct ieee80211_vif *vif,
  1384. struct ieee80211_bss_conf *bss_conf,
  1385. u32 changed)
  1386. {
  1387. #define CHECK_ANI \
  1388. (BSS_CHANGED_ASSOC | \
  1389. BSS_CHANGED_IBSS | \
  1390. BSS_CHANGED_BEACON_ENABLED)
  1391. struct ath_softc *sc = hw->priv;
  1392. struct ath_hw *ah = sc->sc_ah;
  1393. struct ath_common *common = ath9k_hw_common(ah);
  1394. struct ath_vif *avp = (void *)vif->drv_priv;
  1395. unsigned long flags;
  1396. int slottime;
  1397. ath9k_ps_wakeup(sc);
  1398. mutex_lock(&sc->mutex);
  1399. if (changed & BSS_CHANGED_ASSOC) {
  1400. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1401. bss_conf->bssid, bss_conf->assoc);
  1402. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1403. clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  1404. avp->primary_sta_vif = false;
  1405. if (ah->opmode == NL80211_IFTYPE_STATION)
  1406. clear_bit(ATH_OP_BEACONS, &common->op_flags);
  1407. }
  1408. ieee80211_iterate_active_interfaces_atomic(
  1409. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1410. ath9k_bss_assoc_iter, sc);
  1411. if (!test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags) &&
  1412. ah->opmode == NL80211_IFTYPE_STATION) {
  1413. memset(common->curbssid, 0, ETH_ALEN);
  1414. common->curaid = 0;
  1415. ath9k_hw_write_associd(sc->sc_ah);
  1416. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1417. ath9k_mci_update_wlan_channels(sc, true);
  1418. }
  1419. ath_chanctx_check_active(sc, avp->chanctx);
  1420. }
  1421. if (changed & BSS_CHANGED_IBSS) {
  1422. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1423. common->curaid = bss_conf->aid;
  1424. ath9k_hw_write_associd(sc->sc_ah);
  1425. }
  1426. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1427. (changed & BSS_CHANGED_BEACON_INT))
  1428. ath9k_beacon_config(sc, vif, changed);
  1429. if (changed & BSS_CHANGED_ERP_SLOT) {
  1430. if (bss_conf->use_short_slot)
  1431. slottime = 9;
  1432. else
  1433. slottime = 20;
  1434. if (vif->type == NL80211_IFTYPE_AP) {
  1435. /*
  1436. * Defer update, so that connected stations can adjust
  1437. * their settings at the same time.
  1438. * See beacon.c for more details
  1439. */
  1440. sc->beacon.slottime = slottime;
  1441. sc->beacon.updateslot = UPDATE;
  1442. } else {
  1443. ah->slottime = slottime;
  1444. ath9k_hw_init_global_settings(ah);
  1445. }
  1446. }
  1447. if (changed & BSS_CHANGED_P2P_PS) {
  1448. spin_lock_bh(&sc->sc_pcu_lock);
  1449. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1450. if (!(sc->ps_flags & PS_BEACON_SYNC))
  1451. ath9k_update_p2p_ps(sc, vif);
  1452. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1453. spin_unlock_bh(&sc->sc_pcu_lock);
  1454. }
  1455. if (changed & CHECK_ANI)
  1456. ath_check_ani(sc);
  1457. mutex_unlock(&sc->mutex);
  1458. ath9k_ps_restore(sc);
  1459. #undef CHECK_ANI
  1460. }
  1461. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1462. {
  1463. struct ath_softc *sc = hw->priv;
  1464. u64 tsf;
  1465. mutex_lock(&sc->mutex);
  1466. ath9k_ps_wakeup(sc);
  1467. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1468. ath9k_ps_restore(sc);
  1469. mutex_unlock(&sc->mutex);
  1470. return tsf;
  1471. }
  1472. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1473. struct ieee80211_vif *vif,
  1474. u64 tsf)
  1475. {
  1476. struct ath_softc *sc = hw->priv;
  1477. mutex_lock(&sc->mutex);
  1478. ath9k_ps_wakeup(sc);
  1479. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1480. ath9k_ps_restore(sc);
  1481. mutex_unlock(&sc->mutex);
  1482. }
  1483. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1484. {
  1485. struct ath_softc *sc = hw->priv;
  1486. mutex_lock(&sc->mutex);
  1487. ath9k_ps_wakeup(sc);
  1488. ath9k_hw_reset_tsf(sc->sc_ah);
  1489. ath9k_ps_restore(sc);
  1490. mutex_unlock(&sc->mutex);
  1491. }
  1492. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1493. struct ieee80211_vif *vif,
  1494. enum ieee80211_ampdu_mlme_action action,
  1495. struct ieee80211_sta *sta,
  1496. u16 tid, u16 *ssn, u8 buf_size)
  1497. {
  1498. struct ath_softc *sc = hw->priv;
  1499. bool flush = false;
  1500. int ret = 0;
  1501. mutex_lock(&sc->mutex);
  1502. switch (action) {
  1503. case IEEE80211_AMPDU_RX_START:
  1504. break;
  1505. case IEEE80211_AMPDU_RX_STOP:
  1506. break;
  1507. case IEEE80211_AMPDU_TX_START:
  1508. ath9k_ps_wakeup(sc);
  1509. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1510. if (!ret)
  1511. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1512. ath9k_ps_restore(sc);
  1513. break;
  1514. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1515. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1516. flush = true;
  1517. case IEEE80211_AMPDU_TX_STOP_CONT:
  1518. ath9k_ps_wakeup(sc);
  1519. ath_tx_aggr_stop(sc, sta, tid);
  1520. if (!flush)
  1521. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1522. ath9k_ps_restore(sc);
  1523. break;
  1524. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1525. ath9k_ps_wakeup(sc);
  1526. ath_tx_aggr_resume(sc, sta, tid);
  1527. ath9k_ps_restore(sc);
  1528. break;
  1529. default:
  1530. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1531. }
  1532. mutex_unlock(&sc->mutex);
  1533. return ret;
  1534. }
  1535. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1536. struct survey_info *survey)
  1537. {
  1538. struct ath_softc *sc = hw->priv;
  1539. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1540. struct ieee80211_supported_band *sband;
  1541. struct ieee80211_channel *chan;
  1542. int pos;
  1543. if (config_enabled(CONFIG_ATH9K_TX99))
  1544. return -EOPNOTSUPP;
  1545. spin_lock_bh(&common->cc_lock);
  1546. if (idx == 0)
  1547. ath_update_survey_stats(sc);
  1548. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1549. if (sband && idx >= sband->n_channels) {
  1550. idx -= sband->n_channels;
  1551. sband = NULL;
  1552. }
  1553. if (!sband)
  1554. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1555. if (!sband || idx >= sband->n_channels) {
  1556. spin_unlock_bh(&common->cc_lock);
  1557. return -ENOENT;
  1558. }
  1559. chan = &sband->channels[idx];
  1560. pos = chan->hw_value;
  1561. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1562. survey->channel = chan;
  1563. spin_unlock_bh(&common->cc_lock);
  1564. return 0;
  1565. }
  1566. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1567. {
  1568. struct ath_softc *sc = hw->priv;
  1569. struct ath_hw *ah = sc->sc_ah;
  1570. if (config_enabled(CONFIG_ATH9K_TX99))
  1571. return;
  1572. mutex_lock(&sc->mutex);
  1573. ah->coverage_class = coverage_class;
  1574. ath9k_ps_wakeup(sc);
  1575. ath9k_hw_init_global_settings(ah);
  1576. ath9k_ps_restore(sc);
  1577. mutex_unlock(&sc->mutex);
  1578. }
  1579. static bool ath9k_has_tx_pending(struct ath_softc *sc)
  1580. {
  1581. int i, npend = 0;
  1582. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1583. if (!ATH_TXQ_SETUP(sc, i))
  1584. continue;
  1585. if (!sc->tx.txq[i].axq_depth)
  1586. continue;
  1587. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1588. if (npend)
  1589. break;
  1590. }
  1591. return !!npend;
  1592. }
  1593. static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1594. u32 queues, bool drop)
  1595. {
  1596. struct ath_softc *sc = hw->priv;
  1597. mutex_lock(&sc->mutex);
  1598. __ath9k_flush(hw, queues, drop);
  1599. mutex_unlock(&sc->mutex);
  1600. }
  1601. void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
  1602. {
  1603. struct ath_softc *sc = hw->priv;
  1604. struct ath_hw *ah = sc->sc_ah;
  1605. struct ath_common *common = ath9k_hw_common(ah);
  1606. int timeout = HZ / 5; /* 200 ms */
  1607. bool drain_txq;
  1608. cancel_delayed_work_sync(&sc->tx_complete_work);
  1609. if (ah->ah_flags & AH_UNPLUGGED) {
  1610. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1611. return;
  1612. }
  1613. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  1614. ath_dbg(common, ANY, "Device not present\n");
  1615. return;
  1616. }
  1617. if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
  1618. timeout) > 0)
  1619. drop = false;
  1620. if (drop) {
  1621. ath9k_ps_wakeup(sc);
  1622. spin_lock_bh(&sc->sc_pcu_lock);
  1623. drain_txq = ath_drain_all_txq(sc);
  1624. spin_unlock_bh(&sc->sc_pcu_lock);
  1625. if (!drain_txq)
  1626. ath_reset(sc);
  1627. ath9k_ps_restore(sc);
  1628. ieee80211_wake_queues(hw);
  1629. }
  1630. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1631. }
  1632. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1633. {
  1634. struct ath_softc *sc = hw->priv;
  1635. int i;
  1636. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1637. if (!ATH_TXQ_SETUP(sc, i))
  1638. continue;
  1639. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1640. return true;
  1641. }
  1642. return false;
  1643. }
  1644. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1645. {
  1646. struct ath_softc *sc = hw->priv;
  1647. struct ath_hw *ah = sc->sc_ah;
  1648. struct ieee80211_vif *vif;
  1649. struct ath_vif *avp;
  1650. struct ath_buf *bf;
  1651. struct ath_tx_status ts;
  1652. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1653. int status;
  1654. vif = sc->beacon.bslot[0];
  1655. if (!vif)
  1656. return 0;
  1657. if (!vif->bss_conf.enable_beacon)
  1658. return 0;
  1659. avp = (void *)vif->drv_priv;
  1660. if (!sc->beacon.tx_processed && !edma) {
  1661. tasklet_disable(&sc->bcon_tasklet);
  1662. bf = avp->av_bcbuf;
  1663. if (!bf || !bf->bf_mpdu)
  1664. goto skip;
  1665. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1666. if (status == -EINPROGRESS)
  1667. goto skip;
  1668. sc->beacon.tx_processed = true;
  1669. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1670. skip:
  1671. tasklet_enable(&sc->bcon_tasklet);
  1672. }
  1673. return sc->beacon.tx_last;
  1674. }
  1675. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1676. struct ieee80211_low_level_stats *stats)
  1677. {
  1678. struct ath_softc *sc = hw->priv;
  1679. struct ath_hw *ah = sc->sc_ah;
  1680. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1681. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1682. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1683. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1684. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1685. return 0;
  1686. }
  1687. static u32 fill_chainmask(u32 cap, u32 new)
  1688. {
  1689. u32 filled = 0;
  1690. int i;
  1691. for (i = 0; cap && new; i++, cap >>= 1) {
  1692. if (!(cap & BIT(0)))
  1693. continue;
  1694. if (new & BIT(0))
  1695. filled |= BIT(i);
  1696. new >>= 1;
  1697. }
  1698. return filled;
  1699. }
  1700. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1701. {
  1702. if (AR_SREV_9300_20_OR_LATER(ah))
  1703. return true;
  1704. switch (val & 0x7) {
  1705. case 0x1:
  1706. case 0x3:
  1707. case 0x7:
  1708. return true;
  1709. case 0x2:
  1710. return (ah->caps.rx_chainmask == 1);
  1711. default:
  1712. return false;
  1713. }
  1714. }
  1715. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1716. {
  1717. struct ath_softc *sc = hw->priv;
  1718. struct ath_hw *ah = sc->sc_ah;
  1719. if (ah->caps.rx_chainmask != 1)
  1720. rx_ant |= tx_ant;
  1721. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1722. return -EINVAL;
  1723. sc->ant_rx = rx_ant;
  1724. sc->ant_tx = tx_ant;
  1725. if (ah->caps.rx_chainmask == 1)
  1726. return 0;
  1727. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1728. if (AR_SREV_9100(ah))
  1729. ah->rxchainmask = 0x7;
  1730. else
  1731. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1732. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1733. ath9k_cmn_reload_chainmask(ah);
  1734. return 0;
  1735. }
  1736. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1737. {
  1738. struct ath_softc *sc = hw->priv;
  1739. *tx_ant = sc->ant_tx;
  1740. *rx_ant = sc->ant_rx;
  1741. return 0;
  1742. }
  1743. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1744. {
  1745. struct ath_softc *sc = hw->priv;
  1746. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1747. set_bit(ATH_OP_SCANNING, &common->op_flags);
  1748. }
  1749. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1750. {
  1751. struct ath_softc *sc = hw->priv;
  1752. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1753. clear_bit(ATH_OP_SCANNING, &common->op_flags);
  1754. }
  1755. static void
  1756. ath_scan_next_channel(struct ath_softc *sc)
  1757. {
  1758. struct cfg80211_scan_request *req = sc->offchannel.scan_req;
  1759. struct ieee80211_channel *chan;
  1760. if (sc->offchannel.scan_idx >= req->n_channels) {
  1761. sc->offchannel.state = ATH_OFFCHANNEL_IDLE;
  1762. ath_chanctx_switch(sc, ath_chanctx_get_oper_chan(sc), NULL);
  1763. return;
  1764. }
  1765. chan = req->channels[sc->offchannel.scan_idx++];
  1766. sc->offchannel.state = ATH_OFFCHANNEL_PROBE_SEND;
  1767. ath_chanctx_offchan_switch(sc, chan);
  1768. }
  1769. static void ath_scan_complete(struct ath_softc *sc, bool abort)
  1770. {
  1771. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1772. ath_chanctx_switch(sc, ath_chanctx_get_oper_chan(sc), NULL);
  1773. sc->offchannel.scan_req = NULL;
  1774. sc->offchannel.scan_vif = NULL;
  1775. sc->offchannel.state = ATH_OFFCHANNEL_IDLE;
  1776. ieee80211_scan_completed(sc->hw, abort);
  1777. clear_bit(ATH_OP_SCANNING, &common->op_flags);
  1778. ath9k_ps_restore(sc);
  1779. if (!sc->ps_idle)
  1780. return;
  1781. ath_cancel_work(sc);
  1782. }
  1783. static void ath_scan_send_probe(struct ath_softc *sc,
  1784. struct cfg80211_ssid *ssid)
  1785. {
  1786. struct cfg80211_scan_request *req = sc->offchannel.scan_req;
  1787. struct ieee80211_vif *vif = sc->offchannel.scan_vif;
  1788. struct ath_tx_control txctl = {};
  1789. struct sk_buff *skb;
  1790. struct ieee80211_tx_info *info;
  1791. int band = sc->offchannel.chan.chandef.chan->band;
  1792. skb = ieee80211_probereq_get(sc->hw, vif,
  1793. ssid->ssid, ssid->ssid_len, req->ie_len);
  1794. if (!skb)
  1795. return;
  1796. info = IEEE80211_SKB_CB(skb);
  1797. if (req->no_cck)
  1798. info->flags |= IEEE80211_TX_CTL_NO_CCK_RATE;
  1799. if (req->ie_len)
  1800. memcpy(skb_put(skb, req->ie_len), req->ie, req->ie_len);
  1801. skb_set_queue_mapping(skb, IEEE80211_AC_VO);
  1802. if (!ieee80211_tx_prepare_skb(sc->hw, vif, skb, band, NULL))
  1803. goto error;
  1804. txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
  1805. txctl.force_channel = true;
  1806. if (ath_tx_start(sc->hw, skb, &txctl))
  1807. goto error;
  1808. return;
  1809. error:
  1810. ieee80211_free_txskb(sc->hw, skb);
  1811. }
  1812. static void ath_scan_channel_start(struct ath_softc *sc)
  1813. {
  1814. struct cfg80211_scan_request *req = sc->offchannel.scan_req;
  1815. int i, dwell;
  1816. if ((sc->cur_chan->chandef.chan->flags & IEEE80211_CHAN_NO_IR) ||
  1817. !req->n_ssids) {
  1818. dwell = HZ / 9; /* ~110 ms */
  1819. } else {
  1820. dwell = HZ / 16; /* ~60 ms */
  1821. for (i = 0; i < req->n_ssids; i++)
  1822. ath_scan_send_probe(sc, &req->ssids[i]);
  1823. }
  1824. sc->offchannel.state = ATH_OFFCHANNEL_PROBE_WAIT;
  1825. mod_timer(&sc->offchannel.timer, jiffies + dwell);
  1826. }
  1827. void ath_offchannel_channel_change(struct ath_softc *sc)
  1828. {
  1829. if (!sc->offchannel.scan_req)
  1830. return;
  1831. switch (sc->offchannel.state) {
  1832. case ATH_OFFCHANNEL_PROBE_SEND:
  1833. if (sc->cur_chan->chandef.chan !=
  1834. sc->offchannel.chan.chandef.chan)
  1835. return;
  1836. ath_scan_channel_start(sc);
  1837. break;
  1838. case ATH_OFFCHANNEL_IDLE:
  1839. ath_scan_complete(sc, false);
  1840. break;
  1841. default:
  1842. break;
  1843. }
  1844. }
  1845. void ath_offchannel_timer(unsigned long data)
  1846. {
  1847. struct ath_softc *sc = (struct ath_softc *)data;
  1848. struct ath_chanctx *ctx = ath_chanctx_get_oper_chan(sc);
  1849. if (!sc->offchannel.scan_req)
  1850. return;
  1851. switch (sc->offchannel.state) {
  1852. case ATH_OFFCHANNEL_PROBE_WAIT:
  1853. if (ctx->active) {
  1854. sc->offchannel.state = ATH_OFFCHANNEL_SUSPEND;
  1855. ath_chanctx_switch(sc, ctx, NULL);
  1856. mod_timer(&sc->offchannel.timer, jiffies + HZ / 10);
  1857. break;
  1858. }
  1859. /* fall through */
  1860. case ATH_OFFCHANNEL_SUSPEND:
  1861. ath_scan_next_channel(sc);
  1862. break;
  1863. default:
  1864. break;
  1865. }
  1866. }
  1867. static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1868. struct cfg80211_scan_request *req)
  1869. {
  1870. struct ath_softc *sc = hw->priv;
  1871. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1872. int ret = 0;
  1873. mutex_lock(&sc->mutex);
  1874. if (WARN_ON(sc->offchannel.scan_req)) {
  1875. ret = -EBUSY;
  1876. goto out;
  1877. }
  1878. ath9k_ps_wakeup(sc);
  1879. set_bit(ATH_OP_SCANNING, &common->op_flags);
  1880. sc->offchannel.scan_vif = vif;
  1881. sc->offchannel.scan_req = req;
  1882. sc->offchannel.scan_idx = 0;
  1883. sc->offchannel.chan.txpower = vif->bss_conf.txpower;
  1884. ath_scan_next_channel(sc);
  1885. out:
  1886. mutex_unlock(&sc->mutex);
  1887. return ret;
  1888. }
  1889. static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
  1890. struct ieee80211_vif *vif)
  1891. {
  1892. struct ath_softc *sc = hw->priv;
  1893. mutex_lock(&sc->mutex);
  1894. del_timer_sync(&sc->offchannel.timer);
  1895. ath_scan_complete(sc, true);
  1896. mutex_unlock(&sc->mutex);
  1897. }
  1898. void ath9k_fill_chanctx_ops(void)
  1899. {
  1900. if (!ath9k_use_chanctx)
  1901. return;
  1902. ath9k_ops.hw_scan = ath9k_hw_scan;
  1903. ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
  1904. }
  1905. struct ieee80211_ops ath9k_ops = {
  1906. .tx = ath9k_tx,
  1907. .start = ath9k_start,
  1908. .stop = ath9k_stop,
  1909. .add_interface = ath9k_add_interface,
  1910. .change_interface = ath9k_change_interface,
  1911. .remove_interface = ath9k_remove_interface,
  1912. .config = ath9k_config,
  1913. .configure_filter = ath9k_configure_filter,
  1914. .sta_add = ath9k_sta_add,
  1915. .sta_remove = ath9k_sta_remove,
  1916. .sta_notify = ath9k_sta_notify,
  1917. .conf_tx = ath9k_conf_tx,
  1918. .bss_info_changed = ath9k_bss_info_changed,
  1919. .set_key = ath9k_set_key,
  1920. .get_tsf = ath9k_get_tsf,
  1921. .set_tsf = ath9k_set_tsf,
  1922. .reset_tsf = ath9k_reset_tsf,
  1923. .ampdu_action = ath9k_ampdu_action,
  1924. .get_survey = ath9k_get_survey,
  1925. .rfkill_poll = ath9k_rfkill_poll_state,
  1926. .set_coverage_class = ath9k_set_coverage_class,
  1927. .flush = ath9k_flush,
  1928. .tx_frames_pending = ath9k_tx_frames_pending,
  1929. .tx_last_beacon = ath9k_tx_last_beacon,
  1930. .release_buffered_frames = ath9k_release_buffered_frames,
  1931. .get_stats = ath9k_get_stats,
  1932. .set_antenna = ath9k_set_antenna,
  1933. .get_antenna = ath9k_get_antenna,
  1934. #ifdef CONFIG_ATH9K_WOW
  1935. .suspend = ath9k_suspend,
  1936. .resume = ath9k_resume,
  1937. .set_wakeup = ath9k_set_wakeup,
  1938. #endif
  1939. #ifdef CONFIG_ATH9K_DEBUGFS
  1940. .get_et_sset_count = ath9k_get_et_sset_count,
  1941. .get_et_stats = ath9k_get_et_stats,
  1942. .get_et_strings = ath9k_get_et_strings,
  1943. #endif
  1944. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
  1945. .sta_add_debugfs = ath9k_sta_add_debugfs,
  1946. #endif
  1947. .sw_scan_start = ath9k_sw_scan_start,
  1948. .sw_scan_complete = ath9k_sw_scan_complete,
  1949. };