iwl-nvm-parse.c 26 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  23. * USA
  24. *
  25. * The full GNU General Public License is included in this distribution
  26. * in the file called COPYING.
  27. *
  28. * Contact Information:
  29. * Intel Linux Wireless <ilw@linux.intel.com>
  30. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  31. *
  32. * BSD LICENSE
  33. *
  34. * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  35. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  36. * All rights reserved.
  37. *
  38. * Redistribution and use in source and binary forms, with or without
  39. * modification, are permitted provided that the following conditions
  40. * are met:
  41. *
  42. * * Redistributions of source code must retain the above copyright
  43. * notice, this list of conditions and the following disclaimer.
  44. * * Redistributions in binary form must reproduce the above copyright
  45. * notice, this list of conditions and the following disclaimer in
  46. * the documentation and/or other materials provided with the
  47. * distribution.
  48. * * Neither the name Intel Corporation nor the names of its
  49. * contributors may be used to endorse or promote products derived
  50. * from this software without specific prior written permission.
  51. *
  52. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63. *****************************************************************************/
  64. #include <linux/types.h>
  65. #include <linux/slab.h>
  66. #include <linux/export.h>
  67. #include <linux/etherdevice.h>
  68. #include <linux/pci.h>
  69. #include "iwl-drv.h"
  70. #include "iwl-modparams.h"
  71. #include "iwl-nvm-parse.h"
  72. /* NVM offsets (in words) definitions */
  73. enum wkp_nvm_offsets {
  74. /* NVM HW-Section offset (in words) definitions */
  75. HW_ADDR = 0x15,
  76. /* NVM SW-Section offset (in words) definitions */
  77. NVM_SW_SECTION = 0x1C0,
  78. NVM_VERSION = 0,
  79. RADIO_CFG = 1,
  80. SKU = 2,
  81. N_HW_ADDRS = 3,
  82. NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  83. /* NVM calibration section offset (in words) definitions */
  84. NVM_CALIB_SECTION = 0x2B8,
  85. XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
  86. };
  87. enum family_8000_nvm_offsets {
  88. /* NVM HW-Section offset (in words) definitions */
  89. HW_ADDR0_WFPM_FAMILY_8000 = 0x12,
  90. HW_ADDR1_WFPM_FAMILY_8000 = 0x16,
  91. HW_ADDR0_PCIE_FAMILY_8000 = 0x8A,
  92. HW_ADDR1_PCIE_FAMILY_8000 = 0x8E,
  93. MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1,
  94. /* NVM SW-Section offset (in words) definitions */
  95. NVM_SW_SECTION_FAMILY_8000 = 0x1C0,
  96. NVM_VERSION_FAMILY_8000 = 0,
  97. RADIO_CFG_FAMILY_8000 = 2,
  98. SKU_FAMILY_8000 = 4,
  99. N_HW_ADDRS_FAMILY_8000 = 5,
  100. /* NVM REGULATORY -Section offset (in words) definitions */
  101. NVM_CHANNELS_FAMILY_8000 = 0,
  102. /* NVM calibration section offset (in words) definitions */
  103. NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8,
  104. XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000
  105. };
  106. /* SKU Capabilities (actual values from NVM definition) */
  107. enum nvm_sku_bits {
  108. NVM_SKU_CAP_BAND_24GHZ = BIT(0),
  109. NVM_SKU_CAP_BAND_52GHZ = BIT(1),
  110. NVM_SKU_CAP_11N_ENABLE = BIT(2),
  111. NVM_SKU_CAP_11AC_ENABLE = BIT(3),
  112. };
  113. /*
  114. * These are the channel numbers in the order that they are stored in the NVM
  115. */
  116. static const u8 iwl_nvm_channels[] = {
  117. /* 2.4 GHz */
  118. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  119. /* 5 GHz */
  120. 36, 40, 44 , 48, 52, 56, 60, 64,
  121. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  122. 149, 153, 157, 161, 165
  123. };
  124. static const u8 iwl_nvm_channels_family_8000[] = {
  125. /* 2.4 GHz */
  126. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  127. /* 5 GHz */
  128. 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
  129. 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  130. 149, 153, 157, 161, 165, 169, 173, 177, 181
  131. };
  132. #define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
  133. #define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000)
  134. #define NUM_2GHZ_CHANNELS 14
  135. #define NUM_2GHZ_CHANNELS_FAMILY_8000 14
  136. #define FIRST_2GHZ_HT_MINUS 5
  137. #define LAST_2GHZ_HT_PLUS 9
  138. #define LAST_5GHZ_HT 161
  139. /* rate data (static) */
  140. static struct ieee80211_rate iwl_cfg80211_rates[] = {
  141. { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
  142. { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
  143. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  144. { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
  145. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  146. { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
  147. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  148. { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
  149. { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
  150. { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
  151. { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
  152. { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
  153. { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
  154. { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
  155. { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
  156. };
  157. #define RATES_24_OFFS 0
  158. #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
  159. #define RATES_52_OFFS 4
  160. #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
  161. /**
  162. * enum iwl_nvm_channel_flags - channel flags in NVM
  163. * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
  164. * @NVM_CHANNEL_IBSS: usable as an IBSS channel
  165. * @NVM_CHANNEL_ACTIVE: active scanning allowed
  166. * @NVM_CHANNEL_RADAR: radar detection required
  167. * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
  168. * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
  169. * on same channel on 2.4 or same UNII band on 5.2
  170. * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
  171. * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
  172. * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
  173. * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
  174. */
  175. enum iwl_nvm_channel_flags {
  176. NVM_CHANNEL_VALID = BIT(0),
  177. NVM_CHANNEL_IBSS = BIT(1),
  178. NVM_CHANNEL_ACTIVE = BIT(3),
  179. NVM_CHANNEL_RADAR = BIT(4),
  180. NVM_CHANNEL_INDOOR_ONLY = BIT(5),
  181. NVM_CHANNEL_GO_CONCURRENT = BIT(6),
  182. NVM_CHANNEL_WIDE = BIT(8),
  183. NVM_CHANNEL_40MHZ = BIT(9),
  184. NVM_CHANNEL_80MHZ = BIT(10),
  185. NVM_CHANNEL_160MHZ = BIT(11),
  186. };
  187. #define CHECK_AND_PRINT_I(x) \
  188. ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
  189. static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
  190. u16 nvm_flags)
  191. {
  192. u32 flags = IEEE80211_CHAN_NO_HT40;
  193. if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
  194. if (ch_num <= LAST_2GHZ_HT_PLUS)
  195. flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  196. if (ch_num >= FIRST_2GHZ_HT_MINUS)
  197. flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  198. } else if (ch_num <= LAST_5GHZ_HT && (nvm_flags & NVM_CHANNEL_40MHZ)) {
  199. if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
  200. flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  201. else
  202. flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  203. }
  204. if (!(nvm_flags & NVM_CHANNEL_80MHZ))
  205. flags |= IEEE80211_CHAN_NO_80MHZ;
  206. if (!(nvm_flags & NVM_CHANNEL_160MHZ))
  207. flags |= IEEE80211_CHAN_NO_160MHZ;
  208. if (!(nvm_flags & NVM_CHANNEL_IBSS))
  209. flags |= IEEE80211_CHAN_NO_IR;
  210. if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
  211. flags |= IEEE80211_CHAN_NO_IR;
  212. if (nvm_flags & NVM_CHANNEL_RADAR)
  213. flags |= IEEE80211_CHAN_RADAR;
  214. if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
  215. flags |= IEEE80211_CHAN_INDOOR_ONLY;
  216. /* Set the GO concurrent flag only in case that NO_IR is set.
  217. * Otherwise it is meaningless
  218. */
  219. if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  220. (flags & IEEE80211_CHAN_NO_IR))
  221. flags |= IEEE80211_CHAN_GO_CONCURRENT;
  222. return flags;
  223. }
  224. static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
  225. struct iwl_nvm_data *data,
  226. const __le16 * const nvm_ch_flags,
  227. bool lar_supported)
  228. {
  229. int ch_idx;
  230. int n_channels = 0;
  231. struct ieee80211_channel *channel;
  232. u16 ch_flags;
  233. bool is_5ghz;
  234. int num_of_ch, num_2ghz_channels;
  235. const u8 *nvm_chan;
  236. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  237. num_of_ch = IWL_NUM_CHANNELS;
  238. nvm_chan = &iwl_nvm_channels[0];
  239. num_2ghz_channels = NUM_2GHZ_CHANNELS;
  240. } else {
  241. num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000;
  242. nvm_chan = &iwl_nvm_channels_family_8000[0];
  243. num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000;
  244. }
  245. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  246. ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
  247. if (ch_idx >= num_2ghz_channels &&
  248. !data->sku_cap_band_52GHz_enable)
  249. ch_flags &= ~NVM_CHANNEL_VALID;
  250. if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) {
  251. IWL_DEBUG_EEPROM(dev,
  252. "Ch. %d Flags %x [%sGHz] - No traffic\n",
  253. nvm_chan[ch_idx],
  254. ch_flags,
  255. (ch_idx >= num_2ghz_channels) ?
  256. "5.2" : "2.4");
  257. continue;
  258. }
  259. channel = &data->channels[n_channels];
  260. n_channels++;
  261. channel->hw_value = nvm_chan[ch_idx];
  262. channel->band = (ch_idx < num_2ghz_channels) ?
  263. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  264. channel->center_freq =
  265. ieee80211_channel_to_frequency(
  266. channel->hw_value, channel->band);
  267. /* Initialize regulatory-based run-time data */
  268. /*
  269. * Default value - highest tx power value. max_power
  270. * is not used in mvm, and is used for backwards compatibility
  271. */
  272. channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
  273. is_5ghz = channel->band == IEEE80211_BAND_5GHZ;
  274. /* don't put limitations in case we're using LAR */
  275. if (!lar_supported)
  276. channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
  277. ch_idx, is_5ghz,
  278. ch_flags);
  279. else
  280. channel->flags = 0;
  281. IWL_DEBUG_EEPROM(dev,
  282. "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
  283. channel->hw_value,
  284. is_5ghz ? "5.2" : "2.4",
  285. CHECK_AND_PRINT_I(VALID),
  286. CHECK_AND_PRINT_I(IBSS),
  287. CHECK_AND_PRINT_I(ACTIVE),
  288. CHECK_AND_PRINT_I(RADAR),
  289. CHECK_AND_PRINT_I(WIDE),
  290. CHECK_AND_PRINT_I(INDOOR_ONLY),
  291. CHECK_AND_PRINT_I(GO_CONCURRENT),
  292. ch_flags,
  293. channel->max_power,
  294. ((ch_flags & NVM_CHANNEL_IBSS) &&
  295. !(ch_flags & NVM_CHANNEL_RADAR))
  296. ? "" : "not ");
  297. }
  298. return n_channels;
  299. }
  300. static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
  301. struct iwl_nvm_data *data,
  302. struct ieee80211_sta_vht_cap *vht_cap,
  303. u8 tx_chains, u8 rx_chains)
  304. {
  305. int num_rx_ants = num_of_ant(rx_chains);
  306. int num_tx_ants = num_of_ant(tx_chains);
  307. unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
  308. IEEE80211_VHT_MAX_AMPDU_1024K);
  309. vht_cap->vht_supported = true;
  310. vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
  311. IEEE80211_VHT_CAP_RXSTBC_1 |
  312. IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
  313. 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
  314. max_ampdu_exponent <<
  315. IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
  316. if (cfg->ht_params->ldpc)
  317. vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
  318. if (num_tx_ants > 1)
  319. vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
  320. else
  321. vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
  322. if (iwlwifi_mod_params.amsdu_size_8K)
  323. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
  324. vht_cap->vht_mcs.rx_mcs_map =
  325. cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
  326. IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
  327. IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
  328. IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
  329. IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
  330. IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
  331. IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
  332. IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
  333. if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
  334. vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
  335. /* this works because NOT_SUPPORTED == 3 */
  336. vht_cap->vht_mcs.rx_mcs_map |=
  337. cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
  338. }
  339. vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
  340. }
  341. static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
  342. struct iwl_nvm_data *data,
  343. const __le16 *ch_section, bool enable_vht,
  344. u8 tx_chains, u8 rx_chains, bool lar_supported)
  345. {
  346. int n_channels;
  347. int n_used = 0;
  348. struct ieee80211_supported_band *sband;
  349. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  350. n_channels = iwl_init_channel_map(
  351. dev, cfg, data,
  352. &ch_section[NVM_CHANNELS], lar_supported);
  353. else
  354. n_channels = iwl_init_channel_map(
  355. dev, cfg, data,
  356. &ch_section[NVM_CHANNELS_FAMILY_8000],
  357. lar_supported);
  358. sband = &data->bands[IEEE80211_BAND_2GHZ];
  359. sband->band = IEEE80211_BAND_2GHZ;
  360. sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
  361. sband->n_bitrates = N_RATES_24;
  362. n_used += iwl_init_sband_channels(data, sband, n_channels,
  363. IEEE80211_BAND_2GHZ);
  364. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ,
  365. tx_chains, rx_chains);
  366. sband = &data->bands[IEEE80211_BAND_5GHZ];
  367. sband->band = IEEE80211_BAND_5GHZ;
  368. sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
  369. sband->n_bitrates = N_RATES_52;
  370. n_used += iwl_init_sband_channels(data, sband, n_channels,
  371. IEEE80211_BAND_5GHZ);
  372. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ,
  373. tx_chains, rx_chains);
  374. if (enable_vht)
  375. iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
  376. tx_chains, rx_chains);
  377. if (n_channels != n_used)
  378. IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
  379. n_used, n_channels);
  380. }
  381. static int iwl_get_sku(const struct iwl_cfg *cfg,
  382. const __le16 *nvm_sw)
  383. {
  384. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  385. return le16_to_cpup(nvm_sw + SKU);
  386. else
  387. return le32_to_cpup((__le32 *)(nvm_sw + SKU_FAMILY_8000));
  388. }
  389. static int iwl_get_nvm_version(const struct iwl_cfg *cfg,
  390. const __le16 *nvm_sw)
  391. {
  392. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  393. return le16_to_cpup(nvm_sw + NVM_VERSION);
  394. else
  395. return le32_to_cpup((__le32 *)(nvm_sw +
  396. NVM_VERSION_FAMILY_8000));
  397. }
  398. static int iwl_get_radio_cfg(const struct iwl_cfg *cfg,
  399. const __le16 *nvm_sw)
  400. {
  401. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  402. return le16_to_cpup(nvm_sw + RADIO_CFG);
  403. else
  404. return le32_to_cpup((__le32 *)(nvm_sw + RADIO_CFG_FAMILY_8000));
  405. }
  406. #define N_HW_ADDRS_MASK_FAMILY_8000 0xF
  407. static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg,
  408. const __le16 *nvm_sw)
  409. {
  410. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  411. return le16_to_cpup(nvm_sw + N_HW_ADDRS);
  412. else
  413. return le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000))
  414. & N_HW_ADDRS_MASK_FAMILY_8000;
  415. }
  416. static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
  417. struct iwl_nvm_data *data,
  418. u32 radio_cfg)
  419. {
  420. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  421. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
  422. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
  423. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
  424. data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
  425. return;
  426. }
  427. /* set the radio configuration for family 8000 */
  428. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg);
  429. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg);
  430. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg);
  431. data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg);
  432. data->valid_tx_ant = NVM_RF_CFG_TX_ANT_MSK_FAMILY_8000(radio_cfg);
  433. data->valid_rx_ant = NVM_RF_CFG_RX_ANT_MSK_FAMILY_8000(radio_cfg);
  434. }
  435. static void iwl_set_hw_address(const struct iwl_cfg *cfg,
  436. struct iwl_nvm_data *data,
  437. const __le16 *nvm_sec)
  438. {
  439. const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR);
  440. /* The byte order is little endian 16 bit, meaning 214365 */
  441. data->hw_addr[0] = hw_addr[1];
  442. data->hw_addr[1] = hw_addr[0];
  443. data->hw_addr[2] = hw_addr[3];
  444. data->hw_addr[3] = hw_addr[2];
  445. data->hw_addr[4] = hw_addr[5];
  446. data->hw_addr[5] = hw_addr[4];
  447. }
  448. static void iwl_set_hw_address_family_8000(struct device *dev,
  449. const struct iwl_cfg *cfg,
  450. struct iwl_nvm_data *data,
  451. const __le16 *mac_override,
  452. const __le16 *nvm_hw)
  453. {
  454. const u8 *hw_addr;
  455. if (mac_override) {
  456. hw_addr = (const u8 *)(mac_override +
  457. MAC_ADDRESS_OVERRIDE_FAMILY_8000);
  458. /* The byte order is little endian 16 bit, meaning 214365 */
  459. data->hw_addr[0] = hw_addr[1];
  460. data->hw_addr[1] = hw_addr[0];
  461. data->hw_addr[2] = hw_addr[3];
  462. data->hw_addr[3] = hw_addr[2];
  463. data->hw_addr[4] = hw_addr[5];
  464. data->hw_addr[5] = hw_addr[4];
  465. if (is_valid_ether_addr(data->hw_addr))
  466. return;
  467. IWL_ERR_DEV(dev,
  468. "mac address from nvm override section is not valid\n");
  469. }
  470. if (nvm_hw) {
  471. /* read the MAC address from OTP */
  472. if (!dev_is_pci(dev) || (data->nvm_version < 0xE08)) {
  473. /* read the mac address from the WFPM location */
  474. hw_addr = (const u8 *)(nvm_hw +
  475. HW_ADDR0_WFPM_FAMILY_8000);
  476. data->hw_addr[0] = hw_addr[3];
  477. data->hw_addr[1] = hw_addr[2];
  478. data->hw_addr[2] = hw_addr[1];
  479. data->hw_addr[3] = hw_addr[0];
  480. hw_addr = (const u8 *)(nvm_hw +
  481. HW_ADDR1_WFPM_FAMILY_8000);
  482. data->hw_addr[4] = hw_addr[1];
  483. data->hw_addr[5] = hw_addr[0];
  484. } else if ((data->nvm_version >= 0xE08) &&
  485. (data->nvm_version < 0xE0B)) {
  486. /* read "reverse order" from the PCIe location */
  487. hw_addr = (const u8 *)(nvm_hw +
  488. HW_ADDR0_PCIE_FAMILY_8000);
  489. data->hw_addr[5] = hw_addr[2];
  490. data->hw_addr[4] = hw_addr[1];
  491. data->hw_addr[3] = hw_addr[0];
  492. hw_addr = (const u8 *)(nvm_hw +
  493. HW_ADDR1_PCIE_FAMILY_8000);
  494. data->hw_addr[2] = hw_addr[3];
  495. data->hw_addr[1] = hw_addr[2];
  496. data->hw_addr[0] = hw_addr[1];
  497. } else {
  498. /* read from the PCIe location */
  499. hw_addr = (const u8 *)(nvm_hw +
  500. HW_ADDR0_PCIE_FAMILY_8000);
  501. data->hw_addr[5] = hw_addr[0];
  502. data->hw_addr[4] = hw_addr[1];
  503. data->hw_addr[3] = hw_addr[2];
  504. hw_addr = (const u8 *)(nvm_hw +
  505. HW_ADDR1_PCIE_FAMILY_8000);
  506. data->hw_addr[2] = hw_addr[1];
  507. data->hw_addr[1] = hw_addr[2];
  508. data->hw_addr[0] = hw_addr[3];
  509. }
  510. if (!is_valid_ether_addr(data->hw_addr))
  511. IWL_ERR_DEV(dev,
  512. "mac address from hw section is not valid\n");
  513. return;
  514. }
  515. IWL_ERR_DEV(dev, "mac address is not found\n");
  516. }
  517. struct iwl_nvm_data *
  518. iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg,
  519. const __le16 *nvm_hw, const __le16 *nvm_sw,
  520. const __le16 *nvm_calib, const __le16 *regulatory,
  521. const __le16 *mac_override, u8 tx_chains, u8 rx_chains,
  522. bool lar_supported)
  523. {
  524. struct iwl_nvm_data *data;
  525. u32 sku;
  526. u32 radio_cfg;
  527. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  528. data = kzalloc(sizeof(*data) +
  529. sizeof(struct ieee80211_channel) *
  530. IWL_NUM_CHANNELS,
  531. GFP_KERNEL);
  532. else
  533. data = kzalloc(sizeof(*data) +
  534. sizeof(struct ieee80211_channel) *
  535. IWL_NUM_CHANNELS_FAMILY_8000,
  536. GFP_KERNEL);
  537. if (!data)
  538. return NULL;
  539. data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
  540. radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw);
  541. iwl_set_radio_cfg(cfg, data, radio_cfg);
  542. if (data->valid_tx_ant)
  543. tx_chains &= data->valid_tx_ant;
  544. if (data->valid_rx_ant)
  545. rx_chains &= data->valid_rx_ant;
  546. sku = iwl_get_sku(cfg, nvm_sw);
  547. data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
  548. data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
  549. data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
  550. data->sku_cap_11ac_enable = sku & NVM_SKU_CAP_11AC_ENABLE;
  551. if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
  552. data->sku_cap_11n_enable = false;
  553. data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
  554. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  555. /* Checking for required sections */
  556. if (!nvm_calib) {
  557. IWL_ERR_DEV(dev,
  558. "Can't parse empty Calib NVM sections\n");
  559. kfree(data);
  560. return NULL;
  561. }
  562. /* in family 8000 Xtal calibration values moved to OTP */
  563. data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
  564. data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
  565. }
  566. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  567. iwl_set_hw_address(cfg, data, nvm_hw);
  568. iwl_init_sbands(dev, cfg, data, nvm_sw,
  569. sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
  570. rx_chains, lar_supported);
  571. } else {
  572. /* MAC address in family 8000 */
  573. iwl_set_hw_address_family_8000(dev, cfg, data, mac_override,
  574. nvm_hw);
  575. iwl_init_sbands(dev, cfg, data, regulatory,
  576. sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
  577. rx_chains, lar_supported);
  578. }
  579. data->calib_version = 255;
  580. return data;
  581. }
  582. IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
  583. static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
  584. int ch_idx, u16 nvm_flags)
  585. {
  586. u32 flags = NL80211_RRF_NO_HT40;
  587. if (ch_idx < NUM_2GHZ_CHANNELS &&
  588. (nvm_flags & NVM_CHANNEL_40MHZ)) {
  589. if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
  590. flags &= ~NL80211_RRF_NO_HT40PLUS;
  591. if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
  592. flags &= ~NL80211_RRF_NO_HT40MINUS;
  593. } else if (nvm_chan[ch_idx] <= LAST_5GHZ_HT &&
  594. (nvm_flags & NVM_CHANNEL_40MHZ)) {
  595. if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
  596. flags &= ~NL80211_RRF_NO_HT40PLUS;
  597. else
  598. flags &= ~NL80211_RRF_NO_HT40MINUS;
  599. }
  600. if (!(nvm_flags & NVM_CHANNEL_80MHZ))
  601. flags |= NL80211_RRF_NO_80MHZ;
  602. if (!(nvm_flags & NVM_CHANNEL_160MHZ))
  603. flags |= NL80211_RRF_NO_160MHZ;
  604. if (!(nvm_flags & NVM_CHANNEL_IBSS))
  605. flags |= NL80211_RRF_NO_IR;
  606. if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
  607. flags |= NL80211_RRF_NO_IR;
  608. if (nvm_flags & NVM_CHANNEL_RADAR)
  609. flags |= NL80211_RRF_DFS;
  610. if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
  611. flags |= NL80211_RRF_NO_OUTDOOR;
  612. /* Set the GO concurrent flag only in case that NO_IR is set.
  613. * Otherwise it is meaningless
  614. */
  615. if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  616. (flags & NL80211_RRF_NO_IR))
  617. flags |= NL80211_RRF_GO_CONCURRENT;
  618. return flags;
  619. }
  620. struct ieee80211_regdomain *
  621. iwl_parse_nvm_mcc_info(struct device *dev, int num_of_ch, __le32 *channels,
  622. u16 fw_mcc)
  623. {
  624. int ch_idx;
  625. u16 ch_flags, prev_ch_flags = 0;
  626. const u8 *nvm_chan = iwl_nvm_channels; /* TODO: 8000 series differs */
  627. struct ieee80211_regdomain *regd;
  628. int size_of_regd;
  629. struct ieee80211_reg_rule *rule;
  630. enum ieee80211_band band;
  631. int center_freq, prev_center_freq = 0;
  632. int valid_rules = 0;
  633. bool new_rule;
  634. if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
  635. return ERR_PTR(-EINVAL);
  636. IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
  637. num_of_ch);
  638. /* build a regdomain rule for every valid channel */
  639. size_of_regd =
  640. sizeof(struct ieee80211_regdomain) +
  641. num_of_ch * sizeof(struct ieee80211_reg_rule);
  642. regd = kzalloc(size_of_regd, GFP_KERNEL);
  643. if (!regd)
  644. return ERR_PTR(-ENOMEM);
  645. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  646. ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
  647. band = (ch_idx < NUM_2GHZ_CHANNELS) ?
  648. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  649. center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
  650. band);
  651. new_rule = false;
  652. if (!(ch_flags & NVM_CHANNEL_VALID)) {
  653. IWL_DEBUG_DEV(dev, IWL_DL_LAR,
  654. "Ch. %d Flags %x [%sGHz] - No traffic\n",
  655. nvm_chan[ch_idx],
  656. ch_flags,
  657. (ch_idx >= NUM_2GHZ_CHANNELS) ?
  658. "5.2" : "2.4");
  659. continue;
  660. }
  661. /* we can't continue the same rule */
  662. if (ch_idx == 0 || prev_ch_flags != ch_flags ||
  663. center_freq - prev_center_freq > 20) {
  664. valid_rules++;
  665. new_rule = true;
  666. }
  667. rule = &regd->reg_rules[valid_rules - 1];
  668. if (new_rule)
  669. rule->freq_range.start_freq_khz =
  670. MHZ_TO_KHZ(center_freq - 10);
  671. rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
  672. /* this doesn't matter - not used by FW */
  673. rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
  674. rule->power_rule.max_eirp = DBM_TO_MBM(20);
  675. rule->flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
  676. ch_flags);
  677. /* rely on auto-calculation to merge BW of contiguous chans */
  678. rule->flags |= NL80211_RRF_AUTO_BW;
  679. rule->freq_range.max_bandwidth_khz = 0;
  680. prev_ch_flags = ch_flags;
  681. prev_center_freq = center_freq;
  682. IWL_DEBUG_DEV(dev, IWL_DL_LAR,
  683. "Ch. %d [%sGHz] %s%s%s%s%s%s%s%s%s%s(0x%02x): Ad-Hoc %ssupported\n",
  684. center_freq,
  685. band == IEEE80211_BAND_5GHZ ? "5.2" : "2.4",
  686. CHECK_AND_PRINT_I(VALID),
  687. CHECK_AND_PRINT_I(IBSS),
  688. CHECK_AND_PRINT_I(ACTIVE),
  689. CHECK_AND_PRINT_I(RADAR),
  690. CHECK_AND_PRINT_I(WIDE),
  691. CHECK_AND_PRINT_I(40MHZ),
  692. CHECK_AND_PRINT_I(80MHZ),
  693. CHECK_AND_PRINT_I(160MHZ),
  694. CHECK_AND_PRINT_I(INDOOR_ONLY),
  695. CHECK_AND_PRINT_I(GO_CONCURRENT),
  696. ch_flags,
  697. ((ch_flags & NVM_CHANNEL_IBSS) &&
  698. !(ch_flags & NVM_CHANNEL_RADAR))
  699. ? "" : "not ");
  700. }
  701. regd->n_reg_rules = valid_rules;
  702. /* set alpha2 from FW. */
  703. regd->alpha2[0] = fw_mcc >> 8;
  704. regd->alpha2[1] = fw_mcc & 0xff;
  705. return regd;
  706. }
  707. IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);