vdk_axs10x_mb.dtsi 3.0 KB

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  1. /*
  2. * Support for peripherals on the AXS10x mainboard (VDK version)
  3. *
  4. * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. / {
  11. axs10x_mb_vdk {
  12. compatible = "simple-bus";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. ranges = <0x00000000 0xe0000000 0x10000000>;
  16. interrupt-parent = <&mb_intc>;
  17. clocks {
  18. apbclk: apbclk {
  19. compatible = "fixed-clock";
  20. clock-frequency = <50000000>;
  21. #clock-cells = <0>;
  22. };
  23. mmcclk: mmcclk {
  24. compatible = "fixed-clock";
  25. clock-frequency = <50000000>;
  26. #clock-cells = <0>;
  27. };
  28. pguclk: pguclk {
  29. #clock-cells = <0>;
  30. compatible = "fixed-clock";
  31. clock-frequency = <25175000>;
  32. };
  33. };
  34. ethernet@0x18000 {
  35. #interrupt-cells = <1>;
  36. compatible = "snps,dwmac";
  37. reg = < 0x18000 0x2000 >;
  38. interrupts = < 4 >;
  39. interrupt-names = "macirq";
  40. phy-mode = "rgmii";
  41. snps,phy-addr = < 0 >; // VDK model phy address is 0
  42. snps,pbl = < 32 >;
  43. clocks = <&apbclk>;
  44. clock-names = "stmmaceth";
  45. };
  46. ehci@0x40000 {
  47. compatible = "generic-ehci";
  48. reg = < 0x40000 0x100 >;
  49. interrupts = < 8 >;
  50. };
  51. uart@0x20000 {
  52. compatible = "snps,dw-apb-uart";
  53. reg = <0x20000 0x100>;
  54. clock-frequency = <2403200>;
  55. interrupts = <17>;
  56. baud = <115200>;
  57. reg-shift = <2>;
  58. reg-io-width = <4>;
  59. };
  60. uart@0x21000 {
  61. compatible = "snps,dw-apb-uart";
  62. reg = <0x21000 0x100>;
  63. clock-frequency = <2403200>;
  64. interrupts = <18>;
  65. baud = <115200>;
  66. reg-shift = <2>;
  67. reg-io-width = <4>;
  68. };
  69. uart@0x22000 {
  70. compatible = "snps,dw-apb-uart";
  71. reg = <0x22000 0x100>;
  72. clock-frequency = <2403200>;
  73. interrupts = <19>;
  74. baud = <115200>;
  75. reg-shift = <2>;
  76. reg-io-width = <4>;
  77. };
  78. /* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
  79. pgu@17000 {
  80. compatible = "snps,arcpgu";
  81. reg = <0x17000 0x400>;
  82. clocks = <&pguclk>;
  83. clock-names = "pxlclk";
  84. };
  85. /* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
  86. ps2: ps2@e0017400 {
  87. compatible = "snps,arc_ps2";
  88. reg = <0x17400 0x14>;
  89. interrupts = <5>;
  90. interrupt-names = "arc_ps2_irq";
  91. };
  92. mmc@0x15000 {
  93. compatible = "snps,dw-mshc";
  94. reg = <0x15000 0x400>;
  95. num-slots = <1>;
  96. fifo-depth = <1024>;
  97. card-detect-delay = <200>;
  98. clocks = <&apbclk>, <&mmcclk>;
  99. clock-names = "biu", "ciu";
  100. interrupts = <7>;
  101. bus-width = <4>;
  102. };
  103. };
  104. /*
  105. * Embedded Vision subsystem UIO mappings; only relevant for EV VDK
  106. *
  107. * This node is intentionally put outside of MB above becase
  108. * it maps areas outside of MB's 0xEz-0xFz.
  109. */
  110. uio_ev: uio@0xD0000000 {
  111. compatible = "generic-uio";
  112. reg = <0xD0000000 0x2000 0xD1000000 0x2000 0x90000000 0x10000000 0xC0000000 0x10000000>;
  113. reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
  114. interrupt-parent = <&mb_intc>;
  115. interrupts = <23>;
  116. };
  117. };