dra76-evm.dts 13 KB

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  1. /*
  2. * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. /dts-v1/;
  9. #include "dra76x.dtsi"
  10. #include "dra7-evm-common.dtsi"
  11. #include "dra76x-mmc-iodelay.dtsi"
  12. #include <dt-bindings/net/ti-dp83867.h>
  13. / {
  14. model = "TI DRA762 EVM";
  15. compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
  16. aliases {
  17. display0 = &hdmi0;
  18. sound0 = &sound0;
  19. sound1 = &hdmi;
  20. };
  21. memory@0 {
  22. device_type = "memory";
  23. reg = <0x0 0x80000000 0x0 0x80000000>;
  24. };
  25. reserved-memory {
  26. #address-cells = <2>;
  27. #size-cells = <2>;
  28. ranges;
  29. ipu2_memory_region: ipu2-memory@95800000 {
  30. compatible = "shared-dma-pool";
  31. reg = <0x0 0x95800000 0x0 0x3800000>;
  32. reusable;
  33. status = "okay";
  34. };
  35. dsp1_memory_region: dsp1-memory@99000000 {
  36. compatible = "shared-dma-pool";
  37. reg = <0x0 0x99000000 0x0 0x4000000>;
  38. reusable;
  39. status = "okay";
  40. };
  41. ipu1_memory_region: ipu1-memory@9d000000 {
  42. compatible = "shared-dma-pool";
  43. reg = <0x0 0x9d000000 0x0 0x2000000>;
  44. reusable;
  45. status = "okay";
  46. };
  47. dsp2_memory_region: dsp2-memory@9f000000 {
  48. compatible = "shared-dma-pool";
  49. reg = <0x0 0x9f000000 0x0 0x800000>;
  50. reusable;
  51. status = "okay";
  52. };
  53. gpu_memory_region: gpu-memory@c0000000 {
  54. compatible = "shared-dma-pool";
  55. reg = <0x0 0xc0000000 0x0 0x10000000>;
  56. reusable;
  57. status = "okay";
  58. };
  59. };
  60. vsys_12v0: fixedregulator-vsys12v0 {
  61. /* main supply */
  62. compatible = "regulator-fixed";
  63. regulator-name = "vsys_12v0";
  64. regulator-min-microvolt = <12000000>;
  65. regulator-max-microvolt = <12000000>;
  66. regulator-always-on;
  67. regulator-boot-on;
  68. };
  69. vsys_5v0: fixedregulator-vsys5v0 {
  70. /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
  71. compatible = "regulator-fixed";
  72. regulator-name = "vsys_5v0";
  73. regulator-min-microvolt = <5000000>;
  74. regulator-max-microvolt = <5000000>;
  75. vin-supply = <&vsys_12v0>;
  76. regulator-always-on;
  77. regulator-boot-on;
  78. };
  79. vio_3v6: fixedregulator-vio_3v6 {
  80. compatible = "regulator-fixed";
  81. regulator-name = "vio_3v6";
  82. regulator-min-microvolt = <3600000>;
  83. regulator-max-microvolt = <3600000>;
  84. vin-supply = <&vsys_5v0>;
  85. regulator-always-on;
  86. regulator-boot-on;
  87. };
  88. vsys_3v3: fixedregulator-vsys3v3 {
  89. /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
  90. compatible = "regulator-fixed";
  91. regulator-name = "vsys_3v3";
  92. regulator-min-microvolt = <3300000>;
  93. regulator-max-microvolt = <3300000>;
  94. vin-supply = <&vsys_12v0>;
  95. regulator-always-on;
  96. regulator-boot-on;
  97. };
  98. vio_3v3: fixedregulator-vio_3v3 {
  99. compatible = "regulator-fixed";
  100. regulator-name = "vio_3v3";
  101. regulator-min-microvolt = <3300000>;
  102. regulator-max-microvolt = <3300000>;
  103. vin-supply = <&vsys_3v3>;
  104. regulator-always-on;
  105. regulator-boot-on;
  106. };
  107. vio_3v3_sd: fixedregulator-sd {
  108. compatible = "regulator-fixed";
  109. regulator-name = "vio_3v3_sd";
  110. regulator-min-microvolt = <3300000>;
  111. regulator-max-microvolt = <3300000>;
  112. vin-supply = <&vio_3v3>;
  113. enable-active-high;
  114. gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  115. };
  116. vio_1v8: fixedregulator-vio_1v8 {
  117. compatible = "regulator-fixed";
  118. regulator-name = "vio_1v8";
  119. regulator-min-microvolt = <1800000>;
  120. regulator-max-microvolt = <1800000>;
  121. vin-supply = <&smps5_reg>;
  122. };
  123. vmmcwl_fixed: fixedregulator-mmcwl {
  124. compatible = "regulator-fixed";
  125. regulator-name = "vmmcwl_fixed";
  126. regulator-min-microvolt = <1800000>;
  127. regulator-max-microvolt = <1800000>;
  128. gpio = <&gpio5 8 0>; /* gpio5_8 */
  129. startup-delay-us = <70000>;
  130. enable-active-high;
  131. };
  132. vtt_fixed: fixedregulator-vtt {
  133. compatible = "regulator-fixed";
  134. regulator-name = "vtt_fixed";
  135. regulator-min-microvolt = <1350000>;
  136. regulator-max-microvolt = <1350000>;
  137. vin-supply = <&vsys_3v3>;
  138. regulator-always-on;
  139. regulator-boot-on;
  140. };
  141. aic_dvdd: fixedregulator-aic_dvdd {
  142. /* TPS77018DBVT */
  143. compatible = "regulator-fixed";
  144. regulator-name = "aic_dvdd";
  145. vin-supply = <&vio_3v3>;
  146. regulator-min-microvolt = <1800000>;
  147. regulator-max-microvolt = <1800000>;
  148. };
  149. hdmi0: connector {
  150. compatible = "hdmi-connector";
  151. label = "hdmi";
  152. type = "a";
  153. port {
  154. hdmi_connector_in: endpoint {
  155. remote-endpoint = <&tpd12s015_out>;
  156. };
  157. };
  158. };
  159. tpd12s015: encoder {
  160. compatible = "ti,tpd12s015";
  161. gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
  162. <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
  163. <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
  164. ports {
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. port@0 {
  168. reg = <0>;
  169. tpd12s015_in: endpoint {
  170. remote-endpoint = <&hdmi_out>;
  171. };
  172. };
  173. port@1 {
  174. reg = <1>;
  175. tpd12s015_out: endpoint {
  176. remote-endpoint = <&hdmi_connector_in>;
  177. };
  178. };
  179. };
  180. };
  181. };
  182. &i2c1 {
  183. status = "okay";
  184. clock-frequency = <400000>;
  185. tps65917: tps65917@58 {
  186. compatible = "ti,tps65917";
  187. reg = <0x58>;
  188. ti,system-power-controller;
  189. ti,palmas-override-powerhold;
  190. interrupt-controller;
  191. #interrupt-cells = <2>;
  192. tps65917_pmic {
  193. compatible = "ti,tps65917-pmic";
  194. smps12-in-supply = <&vsys_3v3>;
  195. smps3-in-supply = <&vsys_3v3>;
  196. smps4-in-supply = <&vsys_3v3>;
  197. smps5-in-supply = <&vsys_3v3>;
  198. ldo1-in-supply = <&vsys_3v3>;
  199. ldo2-in-supply = <&vsys_3v3>;
  200. ldo3-in-supply = <&vsys_5v0>;
  201. ldo4-in-supply = <&vsys_5v0>;
  202. ldo5-in-supply = <&vsys_3v3>;
  203. tps65917_regulators: regulators {
  204. smps12_reg: smps12 {
  205. /* VDD_DSPEVE */
  206. regulator-name = "smps12";
  207. regulator-min-microvolt = <850000>;
  208. regulator-max-microvolt = <1250000>;
  209. regulator-always-on;
  210. regulator-boot-on;
  211. };
  212. smps3_reg: smps3 {
  213. /* VDD_CORE */
  214. regulator-name = "smps3";
  215. regulator-min-microvolt = <850000>;
  216. regulator-max-microvolt = <1250000>;
  217. regulator-boot-on;
  218. regulator-always-on;
  219. };
  220. smps4_reg: smps4 {
  221. /* VDD_IVA */
  222. regulator-name = "smps4";
  223. regulator-min-microvolt = <850000>;
  224. regulator-max-microvolt = <1250000>;
  225. regulator-always-on;
  226. regulator-boot-on;
  227. };
  228. smps5_reg: smps5 {
  229. /* VDDS1V8 */
  230. regulator-name = "smps5";
  231. regulator-min-microvolt = <1800000>;
  232. regulator-max-microvolt = <1800000>;
  233. regulator-boot-on;
  234. regulator-always-on;
  235. };
  236. ldo1_reg: ldo1 {
  237. /* LDO1_OUT --> VDA_PHY1_1V8 */
  238. regulator-name = "ldo1";
  239. regulator-min-microvolt = <1800000>;
  240. regulator-max-microvolt = <1800000>;
  241. regulator-always-on;
  242. regulator-boot-on;
  243. regulator-allow-bypass;
  244. };
  245. ldo2_reg: ldo2 {
  246. /* LDO2_OUT --> VDA_PHY2_1V8 */
  247. regulator-name = "ldo2";
  248. regulator-min-microvolt = <1800000>;
  249. regulator-max-microvolt = <1800000>;
  250. regulator-allow-bypass;
  251. regulator-always-on;
  252. };
  253. ldo3_reg: ldo3 {
  254. /* VDA_USB_3V3 */
  255. regulator-name = "ldo3";
  256. regulator-min-microvolt = <3300000>;
  257. regulator-max-microvolt = <3300000>;
  258. regulator-boot-on;
  259. regulator-always-on;
  260. };
  261. ldo5_reg: ldo5 {
  262. /* VDDA_1V8_PLL */
  263. regulator-name = "ldo5";
  264. regulator-min-microvolt = <1800000>;
  265. regulator-max-microvolt = <1800000>;
  266. regulator-always-on;
  267. regulator-boot-on;
  268. };
  269. ldo4_reg: ldo4 {
  270. /* VDD_SDIO_DV */
  271. regulator-name = "ldo4";
  272. regulator-min-microvolt = <1800000>;
  273. regulator-max-microvolt = <3300000>;
  274. regulator-boot-on;
  275. regulator-always-on;
  276. };
  277. };
  278. };
  279. tps65917_power_button {
  280. compatible = "ti,palmas-pwrbutton";
  281. interrupt-parent = <&tps65917>;
  282. interrupts = <1 IRQ_TYPE_NONE>;
  283. wakeup-source;
  284. ti,palmas-long-press-seconds = <6>;
  285. };
  286. };
  287. lp87565: lp87565@60 {
  288. compatible = "ti,lp87565-q1";
  289. reg = <0x60>;
  290. buck10-in-supply =<&vsys_3v3>;
  291. buck23-in-supply =<&vsys_3v3>;
  292. regulators: regulators {
  293. buck10_reg: buck10 {
  294. /*VDD_MPU*/
  295. regulator-name = "buck10";
  296. regulator-min-microvolt = <850000>;
  297. regulator-max-microvolt = <1250000>;
  298. regulator-always-on;
  299. regulator-boot-on;
  300. };
  301. buck23_reg: buck23 {
  302. /* VDD_GPU*/
  303. regulator-name = "buck23";
  304. regulator-min-microvolt = <850000>;
  305. regulator-max-microvolt = <1250000>;
  306. regulator-boot-on;
  307. regulator-always-on;
  308. };
  309. };
  310. };
  311. pcf_lcd: pcf8757@20 {
  312. compatible = "ti,pcf8575", "nxp,pcf8575";
  313. reg = <0x20>;
  314. gpio-controller;
  315. #gpio-cells = <2>;
  316. interrupt-controller;
  317. #interrupt-cells = <2>;
  318. interrupt-parent = <&gpio1>;
  319. interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  320. };
  321. pcf_gpio_21: pcf8757@21 {
  322. compatible = "ti,pcf8575", "nxp,pcf8575";
  323. reg = <0x21>;
  324. gpio-controller;
  325. #gpio-cells = <2>;
  326. interrupt-parent = <&gpio1>;
  327. interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  328. interrupt-controller;
  329. #interrupt-cells = <2>;
  330. };
  331. pcf_hdmi: pcf8575@26 {
  332. compatible = "ti,pcf8575", "nxp,pcf8575";
  333. reg = <0x26>;
  334. gpio-controller;
  335. #gpio-cells = <2>;
  336. p1 {
  337. /* vin6_sel_s0: high: VIN6, low: audio */
  338. gpio-hog;
  339. gpios = <1 GPIO_ACTIVE_HIGH>;
  340. output-low;
  341. line-name = "vin6_sel_s0";
  342. };
  343. };
  344. tlv320aic3106: tlv320aic3106@19 {
  345. #sound-dai-cells = <0>;
  346. compatible = "ti,tlv320aic3106";
  347. reg = <0x19>;
  348. adc-settle-ms = <40>;
  349. ai3x-micbias-vg = <1>; /* 2.0V */
  350. status = "okay";
  351. /* Regulators */
  352. AVDD-supply = <&vio_3v3>;
  353. IOVDD-supply = <&vio_3v3>;
  354. DRVDD-supply = <&vio_3v3>;
  355. DVDD-supply = <&aic_dvdd>;
  356. };
  357. };
  358. &i2c5 {
  359. status = "okay";
  360. clock-frequency = <400000>;
  361. ov10633@37 {
  362. compatible = "ovti,ov10633";
  363. reg = <0x37>;
  364. clocks = <&clk_ov10633_fixed>;
  365. clock-names = "xvclk";
  366. mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */
  367. <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */
  368. port {
  369. onboardLI: endpoint {
  370. remote-endpoint = <&vin2a_ep>;
  371. hsync-active = <1>;
  372. vsync-active = <1>;
  373. pclk-sample = <0>;
  374. };
  375. };
  376. };
  377. };
  378. &cpu0 {
  379. vdd-supply = <&buck10_reg>;
  380. };
  381. &mmc1 {
  382. status = "okay";
  383. vmmc-supply = <&vio_3v3_sd>;
  384. vqmmc-supply = <&ldo4_reg>;
  385. bus-width = <4>;
  386. /*
  387. * SDCD signal is not being used here - using the fact that GPIO mode
  388. * is always hardwired.
  389. */
  390. cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
  391. pinctrl-names = "default", "hs";
  392. pinctrl-0 = <&mmc1_pins_default>;
  393. pinctrl-1 = <&mmc1_pins_hs>;
  394. };
  395. &mmc2 {
  396. status = "okay";
  397. vmmc-supply = <&vio_1v8>;
  398. vqmmc-supply = <&vio_1v8>;
  399. bus-width = <8>;
  400. non-removable;
  401. pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
  402. pinctrl-0 = <&mmc2_pins_default>;
  403. pinctrl-1 = <&mmc2_pins_default>;
  404. pinctrl-2 = <&mmc2_pins_default>;
  405. pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
  406. };
  407. &mmc4 {
  408. status = "okay";
  409. vmmc-supply = <&vio_3v6>;
  410. vqmmc-supply = <&vmmcwl_fixed>;
  411. pinctrl-names = "default", "hs", "sdr12", "sdr25";
  412. pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>;
  413. pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
  414. pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
  415. pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
  416. };
  417. /* No RTC on this device */
  418. &rtc {
  419. status = "disabled";
  420. };
  421. &mac {
  422. status = "okay";
  423. dual_emac;
  424. };
  425. &cpsw_emac0 {
  426. phy_id = <&davinci_mdio>, <2>;
  427. phy-mode = "rgmii-id";
  428. dual_emac_res_vlan = <1>;
  429. };
  430. &cpsw_emac1 {
  431. phy_id = <&davinci_mdio>, <3>;
  432. phy-mode = "rgmii-id";
  433. dual_emac_res_vlan = <2>;
  434. };
  435. &davinci_mdio {
  436. dp83867_0: ethernet-phy@2 {
  437. reg = <2>;
  438. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  439. ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
  440. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
  441. ti,min-output-impedance;
  442. ti,dp83867-rxctrl-strap-quirk;
  443. };
  444. dp83867_1: ethernet-phy@3 {
  445. reg = <3>;
  446. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  447. ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
  448. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
  449. ti,min-output-impedance;
  450. ti,dp83867-rxctrl-strap-quirk;
  451. };
  452. };
  453. &usb2_phy1 {
  454. phy-supply = <&ldo3_reg>;
  455. };
  456. &usb2_phy2 {
  457. phy-supply = <&ldo3_reg>;
  458. };
  459. &dss {
  460. status = "ok";
  461. vdda_video-supply = <&ldo5_reg>;
  462. };
  463. &hdmi {
  464. status = "ok";
  465. vdda-supply = <&ldo1_reg>;
  466. port {
  467. hdmi_out: endpoint {
  468. remote-endpoint = <&tpd12s015_in>;
  469. };
  470. };
  471. };
  472. &qspi {
  473. spi-max-frequency = <96000000>;
  474. m25p80@0 {
  475. spi-max-frequency = <96000000>;
  476. };
  477. };
  478. &pcie2_phy {
  479. status = "okay";
  480. };
  481. &pcie1_rc {
  482. num-lanes = <2>;
  483. phys = <&pcie1_phy>, <&pcie2_phy>;
  484. phy-names = "pcie-phy0", "pcie-phy1";
  485. };
  486. &pcie1_ep {
  487. num-lanes = <2>;
  488. phys = <&pcie1_phy>, <&pcie2_phy>;
  489. phy-names = "pcie-phy0", "pcie-phy1";
  490. };
  491. &extcon_usb1 {
  492. vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
  493. };
  494. &extcon_usb2 {
  495. vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
  496. };
  497. &m_can0 {
  498. can-transceiver {
  499. max-bitrate = <5000000>;
  500. };
  501. };
  502. &vin2a {
  503. vin2a_ep: endpoint@0 {
  504. slave-mode;
  505. remote-endpoint = <&onboardLI>;
  506. };
  507. };
  508. &ipu2 {
  509. status = "okay";
  510. memory-region = <&ipu2_memory_region>;
  511. };
  512. &ipu1 {
  513. status = "okay";
  514. memory-region = <&ipu1_memory_region>;
  515. };
  516. &dsp1 {
  517. status = "okay";
  518. memory-region = <&dsp1_memory_region>;
  519. };
  520. &dsp2 {
  521. status = "okay";
  522. memory-region = <&dsp2_memory_region>;
  523. };
  524. &gpu {
  525. memory-region = <&gpu_memory_region>;
  526. };
  527. #include "dra7-ipu-common-early-boot.dtsi"