tegra20-whistler.dts 14 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra20.dtsi"
  4. / {
  5. model = "NVIDIA Tegra20 Whistler evaluation board";
  6. compatible = "nvidia,whistler", "nvidia,tegra20";
  7. aliases {
  8. rtc0 = "/i2c@7000d000/max8907@3c";
  9. rtc1 = "/rtc@7000e000";
  10. serial0 = &uarta;
  11. };
  12. memory {
  13. reg = <0x00000000 0x20000000>;
  14. };
  15. host1x@50000000 {
  16. hdmi@54280000 {
  17. status = "okay";
  18. vdd-supply = <&hdmi_vdd_reg>;
  19. pll-supply = <&hdmi_pll_reg>;
  20. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  21. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  22. GPIO_ACTIVE_HIGH>;
  23. };
  24. };
  25. pinmux@70000014 {
  26. pinctrl-names = "default";
  27. pinctrl-0 = <&state_default>;
  28. state_default: pinmux {
  29. ata {
  30. nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
  31. "gmc", "gmd", "gpu";
  32. nvidia,function = "gmi";
  33. };
  34. atc {
  35. nvidia,pins = "atc", "atd";
  36. nvidia,function = "sdio4";
  37. };
  38. cdev1 {
  39. nvidia,pins = "cdev1";
  40. nvidia,function = "plla_out";
  41. };
  42. cdev2 {
  43. nvidia,pins = "cdev2";
  44. nvidia,function = "osc";
  45. };
  46. crtp {
  47. nvidia,pins = "crtp";
  48. nvidia,function = "crt";
  49. };
  50. csus {
  51. nvidia,pins = "csus";
  52. nvidia,function = "vi_sensor_clk";
  53. };
  54. dap1 {
  55. nvidia,pins = "dap1";
  56. nvidia,function = "dap1";
  57. };
  58. dap2 {
  59. nvidia,pins = "dap2";
  60. nvidia,function = "dap2";
  61. };
  62. dap3 {
  63. nvidia,pins = "dap3";
  64. nvidia,function = "dap3";
  65. };
  66. dap4 {
  67. nvidia,pins = "dap4";
  68. nvidia,function = "dap4";
  69. };
  70. ddc {
  71. nvidia,pins = "ddc";
  72. nvidia,function = "i2c2";
  73. };
  74. dta {
  75. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  76. nvidia,function = "vi";
  77. };
  78. dte {
  79. nvidia,pins = "dte";
  80. nvidia,function = "rsvd1";
  81. };
  82. dtf {
  83. nvidia,pins = "dtf";
  84. nvidia,function = "i2c3";
  85. };
  86. gme {
  87. nvidia,pins = "gme";
  88. nvidia,function = "dap5";
  89. };
  90. gpu7 {
  91. nvidia,pins = "gpu7";
  92. nvidia,function = "rtck";
  93. };
  94. gpv {
  95. nvidia,pins = "gpv";
  96. nvidia,function = "pcie";
  97. };
  98. hdint {
  99. nvidia,pins = "hdint", "pta";
  100. nvidia,function = "hdmi";
  101. };
  102. i2cp {
  103. nvidia,pins = "i2cp";
  104. nvidia,function = "i2cp";
  105. };
  106. irrx {
  107. nvidia,pins = "irrx", "irtx";
  108. nvidia,function = "uartb";
  109. };
  110. kbca {
  111. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  112. nvidia,function = "kbc";
  113. };
  114. kbcb {
  115. nvidia,pins = "kbcb", "kbcd";
  116. nvidia,function = "sdio2";
  117. };
  118. lcsn {
  119. nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
  120. "spia", "spib", "spic";
  121. nvidia,function = "spi3";
  122. };
  123. ld0 {
  124. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  125. "ld5", "ld6", "ld7", "ld8", "ld9",
  126. "ld10", "ld11", "ld12", "ld13", "ld14",
  127. "ld15", "ld16", "ld17", "ldc", "ldi",
  128. "lhp0", "lhp1", "lhp2", "lhs", "lm0",
  129. "lm1", "lpp", "lpw0", "lpw1", "lpw2",
  130. "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
  131. "lvs";
  132. nvidia,function = "displaya";
  133. };
  134. owc {
  135. nvidia,pins = "owc", "uac";
  136. nvidia,function = "owr";
  137. };
  138. pmc {
  139. nvidia,pins = "pmc";
  140. nvidia,function = "pwr_on";
  141. };
  142. rm {
  143. nvidia,pins = "rm";
  144. nvidia,function = "i2c1";
  145. };
  146. sdb {
  147. nvidia,pins = "sdb", "sdc", "sdd", "slxa",
  148. "slxc", "slxd", "slxk";
  149. nvidia,function = "sdio3";
  150. };
  151. sdio1 {
  152. nvidia,pins = "sdio1";
  153. nvidia,function = "sdio1";
  154. };
  155. spdi {
  156. nvidia,pins = "spdi", "spdo";
  157. nvidia,function = "rsvd2";
  158. };
  159. spid {
  160. nvidia,pins = "spid", "spie", "spig", "spih";
  161. nvidia,function = "spi2_alt";
  162. };
  163. spif {
  164. nvidia,pins = "spif";
  165. nvidia,function = "spi2";
  166. };
  167. uaa {
  168. nvidia,pins = "uaa", "uab";
  169. nvidia,function = "uarta";
  170. };
  171. uad {
  172. nvidia,pins = "uad";
  173. nvidia,function = "irda";
  174. };
  175. uca {
  176. nvidia,pins = "uca", "ucb";
  177. nvidia,function = "uartc";
  178. };
  179. uda {
  180. nvidia,pins = "uda";
  181. nvidia,function = "spi1";
  182. };
  183. conf_ata {
  184. nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
  185. "gmb", "gmc", "gmd", "irrx", "irtx",
  186. "kbca", "kbcb", "kbcc", "kbcd", "kbce",
  187. "kbcf", "sdc", "sdd", "spie", "spig",
  188. "spih", "uaa", "uab", "uad", "uca",
  189. "ucb";
  190. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  191. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  192. };
  193. conf_atd {
  194. nvidia,pins = "atd", "ate", "cdev1", "csus",
  195. "dap1", "dap2", "dap3", "dap4", "dte",
  196. "dtf", "gpu", "gpu7", "gpv", "i2cp",
  197. "rm", "sdio1", "slxa", "slxc", "slxd",
  198. "slxk", "spdi", "spdo", "uac", "uda";
  199. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  200. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  201. };
  202. conf_cdev2 {
  203. nvidia,pins = "cdev2", "spia", "spib";
  204. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  205. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  206. };
  207. conf_ck32 {
  208. nvidia,pins = "ck32", "ddrc", "lc", "pmca",
  209. "pmcb", "pmcc", "pmcd", "xm2c",
  210. "xm2d";
  211. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  212. };
  213. conf_crtp {
  214. nvidia,pins = "crtp";
  215. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  216. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  217. };
  218. conf_dta {
  219. nvidia,pins = "dta", "dtb", "dtc", "dtd",
  220. "spid", "spif";
  221. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  222. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  223. };
  224. conf_gme {
  225. nvidia,pins = "gme", "owc", "pta", "spic";
  226. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  228. };
  229. conf_ld17_0 {
  230. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  231. "ld23_22";
  232. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  233. };
  234. conf_ls {
  235. nvidia,pins = "ls", "pmce";
  236. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  237. };
  238. drive_dap1 {
  239. nvidia,pins = "drive_dap1";
  240. nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
  241. nvidia,schmitt = <TEGRA_PIN_ENABLE>;
  242. nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
  243. nvidia,pull-down-strength = <0>;
  244. nvidia,pull-up-strength = <0>;
  245. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  246. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  247. };
  248. };
  249. };
  250. i2s@70002800 {
  251. status = "okay";
  252. };
  253. serial@70006000 {
  254. status = "okay";
  255. };
  256. hdmi_ddc: i2c@7000c400 {
  257. status = "okay";
  258. clock-frequency = <100000>;
  259. };
  260. i2c@7000d000 {
  261. status = "okay";
  262. clock-frequency = <100000>;
  263. codec: codec@1a {
  264. compatible = "wlf,wm8753";
  265. reg = <0x1a>;
  266. };
  267. tca6416: gpio@20 {
  268. compatible = "ti,tca6416";
  269. reg = <0x20>;
  270. gpio-controller;
  271. #gpio-cells = <2>;
  272. };
  273. max8907@3c {
  274. compatible = "maxim,max8907";
  275. reg = <0x3c>;
  276. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  277. maxim,system-power-controller;
  278. mbatt-supply = <&usb0_vbus_reg>;
  279. in-v1-supply = <&mbatt_reg>;
  280. in-v2-supply = <&mbatt_reg>;
  281. in-v3-supply = <&mbatt_reg>;
  282. in1-supply = <&mbatt_reg>;
  283. in2-supply = <&nvvdd_sv3_reg>;
  284. in3-supply = <&mbatt_reg>;
  285. in4-supply = <&mbatt_reg>;
  286. in5-supply = <&mbatt_reg>;
  287. in6-supply = <&mbatt_reg>;
  288. in7-supply = <&mbatt_reg>;
  289. in8-supply = <&mbatt_reg>;
  290. in9-supply = <&mbatt_reg>;
  291. in10-supply = <&mbatt_reg>;
  292. in11-supply = <&mbatt_reg>;
  293. in12-supply = <&mbatt_reg>;
  294. in13-supply = <&mbatt_reg>;
  295. in14-supply = <&mbatt_reg>;
  296. in15-supply = <&mbatt_reg>;
  297. in16-supply = <&mbatt_reg>;
  298. in17-supply = <&nvvdd_sv3_reg>;
  299. in18-supply = <&nvvdd_sv3_reg>;
  300. in19-supply = <&mbatt_reg>;
  301. in20-supply = <&mbatt_reg>;
  302. regulators {
  303. mbatt_reg: mbatt {
  304. regulator-name = "vbat_pmu";
  305. regulator-always-on;
  306. };
  307. sd1 {
  308. regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
  309. regulator-min-microvolt = <1000000>;
  310. regulator-max-microvolt = <1000000>;
  311. regulator-always-on;
  312. };
  313. sd2 {
  314. regulator-name = "nvvdd_sv2,vdd_core";
  315. regulator-min-microvolt = <1200000>;
  316. regulator-max-microvolt = <1200000>;
  317. regulator-always-on;
  318. };
  319. nvvdd_sv3_reg: sd3 {
  320. regulator-name = "nvvdd_sv3";
  321. regulator-min-microvolt = <1800000>;
  322. regulator-max-microvolt = <1800000>;
  323. regulator-always-on;
  324. };
  325. ldo1 {
  326. regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
  327. regulator-min-microvolt = <3300000>;
  328. regulator-max-microvolt = <3300000>;
  329. regulator-always-on;
  330. };
  331. ldo2 {
  332. regulator-name = "nvvdd_ldo2,avdd_pll*";
  333. regulator-min-microvolt = <1100000>;
  334. regulator-max-microvolt = <1100000>;
  335. regulator-always-on;
  336. };
  337. ldo3 {
  338. regulator-name = "nvvdd_ldo3,vcom_1v8b";
  339. regulator-min-microvolt = <1800000>;
  340. regulator-max-microvolt = <1800000>;
  341. regulator-always-on;
  342. };
  343. ldo4 {
  344. regulator-name = "nvvdd_ldo4,avdd_usb*";
  345. regulator-min-microvolt = <3300000>;
  346. regulator-max-microvolt = <3300000>;
  347. regulator-always-on;
  348. };
  349. ldo5 {
  350. regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
  351. regulator-min-microvolt = <2800000>;
  352. regulator-max-microvolt = <2800000>;
  353. regulator-always-on;
  354. };
  355. hdmi_pll_reg: ldo6 {
  356. regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
  357. regulator-min-microvolt = <1800000>;
  358. regulator-max-microvolt = <1800000>;
  359. };
  360. ldo7 {
  361. regulator-name = "nvvdd_ldo7,avddio_audio";
  362. regulator-min-microvolt = <2800000>;
  363. regulator-max-microvolt = <2800000>;
  364. regulator-always-on;
  365. };
  366. ldo8 {
  367. regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
  368. regulator-min-microvolt = <3000000>;
  369. regulator-max-microvolt = <3000000>;
  370. };
  371. ldo9 {
  372. regulator-name = "nvvdd_ldo9,avdd_cam*";
  373. regulator-min-microvolt = <2800000>;
  374. regulator-max-microvolt = <2800000>;
  375. };
  376. ldo10 {
  377. regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
  378. regulator-min-microvolt = <3000000>;
  379. regulator-max-microvolt = <3000000>;
  380. regulator-always-on;
  381. };
  382. hdmi_vdd_reg: ldo11 {
  383. regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
  384. regulator-min-microvolt = <3300000>;
  385. regulator-max-microvolt = <3300000>;
  386. };
  387. ldo12 {
  388. regulator-name = "nvvdd_ldo12,vddio_sdio";
  389. regulator-min-microvolt = <2800000>;
  390. regulator-max-microvolt = <2800000>;
  391. regulator-always-on;
  392. };
  393. ldo13 {
  394. regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
  395. regulator-min-microvolt = <2800000>;
  396. regulator-max-microvolt = <2800000>;
  397. };
  398. ldo14 {
  399. regulator-name = "nvvdd_ldo14,avdd_vdac";
  400. regulator-min-microvolt = <2800000>;
  401. regulator-max-microvolt = <2800000>;
  402. };
  403. ldo15 {
  404. regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
  405. regulator-min-microvolt = <3300000>;
  406. regulator-max-microvolt = <3300000>;
  407. };
  408. ldo16 {
  409. regulator-name = "nvvdd_ldo16,vdd_dbrtr";
  410. regulator-min-microvolt = <1300000>;
  411. regulator-max-microvolt = <1300000>;
  412. };
  413. ldo17 {
  414. regulator-name = "nvvdd_ldo17,vddio_mipi";
  415. regulator-min-microvolt = <1200000>;
  416. regulator-max-microvolt = <1200000>;
  417. };
  418. ldo18 {
  419. regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
  420. regulator-min-microvolt = <1800000>;
  421. regulator-max-microvolt = <1800000>;
  422. };
  423. ldo19 {
  424. regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
  425. regulator-min-microvolt = <2800000>;
  426. regulator-max-microvolt = <2800000>;
  427. };
  428. ldo20 {
  429. regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
  430. regulator-min-microvolt = <1200000>;
  431. regulator-max-microvolt = <1200000>;
  432. regulator-always-on;
  433. };
  434. out5v {
  435. regulator-name = "usb0_vbus_reg";
  436. };
  437. out33v {
  438. regulator-name = "pmu_out3v3";
  439. };
  440. bbat {
  441. regulator-name = "pmu_bbat";
  442. regulator-min-microvolt = <2400000>;
  443. regulator-max-microvolt = <2400000>;
  444. regulator-always-on;
  445. };
  446. sdby {
  447. regulator-name = "vdd_aon";
  448. regulator-always-on;
  449. };
  450. vrtc {
  451. regulator-name = "vrtc,pmu_vccadc";
  452. regulator-always-on;
  453. };
  454. };
  455. };
  456. };
  457. kbc@7000e200 {
  458. status = "okay";
  459. nvidia,debounce-delay-ms = <20>;
  460. nvidia,repeat-delay-ms = <160>;
  461. nvidia,kbc-row-pins = <0 1 2>;
  462. nvidia,kbc-col-pins = <16 17>;
  463. nvidia,wakeup-source;
  464. linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
  465. MATRIX_KEY(0x01, 0x00, KEY_HOME)
  466. MATRIX_KEY(0x01, 0x01, KEY_BACK)
  467. MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
  468. };
  469. pmc@7000e400 {
  470. nvidia,invert-interrupt;
  471. nvidia,suspend-mode = <1>;
  472. nvidia,cpu-pwr-good-time = <2000>;
  473. nvidia,cpu-pwr-off-time = <1000>;
  474. nvidia,core-pwr-good-time = <0 3845>;
  475. nvidia,core-pwr-off-time = <93727>;
  476. nvidia,core-power-req-active-high;
  477. nvidia,sys-clock-req-active-high;
  478. nvidia,combined-power-req;
  479. };
  480. usb@c5000000 {
  481. status = "okay";
  482. };
  483. usb-phy@c5000000 {
  484. status = "okay";
  485. vbus-supply = <&vbus1_reg>;
  486. };
  487. usb@c5008000 {
  488. status = "okay";
  489. };
  490. usb-phy@c5008000 {
  491. status = "okay";
  492. vbus-supply = <&vbus3_reg>;
  493. };
  494. sdhci@c8000400 {
  495. status = "okay";
  496. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  497. wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
  498. bus-width = <8>;
  499. };
  500. sdhci@c8000600 {
  501. status = "okay";
  502. bus-width = <8>;
  503. non-removable;
  504. };
  505. clocks {
  506. compatible = "simple-bus";
  507. #address-cells = <1>;
  508. #size-cells = <0>;
  509. clk32k_in: clock@0 {
  510. compatible = "fixed-clock";
  511. reg=<0>;
  512. #clock-cells = <0>;
  513. clock-frequency = <32768>;
  514. };
  515. };
  516. regulators {
  517. compatible = "simple-bus";
  518. #address-cells = <1>;
  519. #size-cells = <0>;
  520. usb0_vbus_reg: regulator@0 {
  521. compatible = "regulator-fixed";
  522. reg = <0>;
  523. regulator-name = "usb0_vbus";
  524. regulator-min-microvolt = <5000000>;
  525. regulator-max-microvolt = <5000000>;
  526. regulator-always-on;
  527. };
  528. vbus1_reg: regulator@2 {
  529. compatible = "regulator-fixed";
  530. reg = <2>;
  531. regulator-name = "vbus1";
  532. regulator-min-microvolt = <5000000>;
  533. regulator-max-microvolt = <5000000>;
  534. enable-active-high;
  535. gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
  536. regulator-always-on;
  537. regulator-boot-on;
  538. };
  539. vbus3_reg: regulator@3 {
  540. compatible = "regulator-fixed";
  541. reg = <3>;
  542. regulator-name = "vbus3";
  543. regulator-min-microvolt = <5000000>;
  544. regulator-max-microvolt = <5000000>;
  545. enable-active-high;
  546. gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
  547. regulator-always-on;
  548. regulator-boot-on;
  549. };
  550. };
  551. sound {
  552. compatible = "nvidia,tegra-audio-wm8753-whistler",
  553. "nvidia,tegra-audio-wm8753";
  554. nvidia,model = "NVIDIA Tegra Whistler";
  555. nvidia,audio-routing =
  556. "Headphone Jack", "LOUT1",
  557. "Headphone Jack", "ROUT1",
  558. "MIC2", "Mic Jack",
  559. "MIC2N", "Mic Jack";
  560. nvidia,i2s-controller = <&tegra_i2s1>;
  561. nvidia,audio-codec = <&codec>;
  562. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  563. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  564. <&tegra_car TEGRA20_CLK_CDEV1>;
  565. clock-names = "pll_a", "pll_a_out0", "mclk";
  566. };
  567. };