tegra20-tamonten.dtsi 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529
  1. #include "tegra20.dtsi"
  2. / {
  3. model = "Avionic Design Tamonten SOM";
  4. compatible = "ad,tamonten", "nvidia,tegra20";
  5. aliases {
  6. rtc0 = "/i2c@7000d000/tps6586x@34";
  7. rtc1 = "/rtc@7000e000";
  8. serial0 = &uartd;
  9. };
  10. memory {
  11. reg = <0x00000000 0x20000000>;
  12. };
  13. host1x@50000000 {
  14. hdmi@54280000 {
  15. vdd-supply = <&hdmi_vdd_reg>;
  16. pll-supply = <&hdmi_pll_reg>;
  17. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  18. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  19. GPIO_ACTIVE_HIGH>;
  20. };
  21. };
  22. pinmux@70000014 {
  23. pinctrl-names = "default";
  24. pinctrl-0 = <&state_default>;
  25. state_default: pinmux {
  26. ata {
  27. nvidia,pins = "ata";
  28. nvidia,function = "ide";
  29. };
  30. atb {
  31. nvidia,pins = "atb", "gma", "gme";
  32. nvidia,function = "sdio4";
  33. };
  34. atc {
  35. nvidia,pins = "atc";
  36. nvidia,function = "nand";
  37. };
  38. atd {
  39. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  40. "spia", "spib", "spic";
  41. nvidia,function = "gmi";
  42. };
  43. cdev1 {
  44. nvidia,pins = "cdev1";
  45. nvidia,function = "plla_out";
  46. };
  47. cdev2 {
  48. nvidia,pins = "cdev2";
  49. nvidia,function = "pllp_out4";
  50. };
  51. crtp {
  52. nvidia,pins = "crtp";
  53. nvidia,function = "crt";
  54. };
  55. csus {
  56. nvidia,pins = "csus";
  57. nvidia,function = "vi_sensor_clk";
  58. };
  59. dap1 {
  60. nvidia,pins = "dap1";
  61. nvidia,function = "dap1";
  62. };
  63. dap2 {
  64. nvidia,pins = "dap2";
  65. nvidia,function = "dap2";
  66. };
  67. dap3 {
  68. nvidia,pins = "dap3";
  69. nvidia,function = "dap3";
  70. };
  71. dap4 {
  72. nvidia,pins = "dap4";
  73. nvidia,function = "dap4";
  74. };
  75. dta {
  76. nvidia,pins = "dta", "dtd";
  77. nvidia,function = "sdio2";
  78. };
  79. dtb {
  80. nvidia,pins = "dtb", "dtc", "dte";
  81. nvidia,function = "rsvd1";
  82. };
  83. dtf {
  84. nvidia,pins = "dtf";
  85. nvidia,function = "i2c3";
  86. };
  87. gmc {
  88. nvidia,pins = "gmc";
  89. nvidia,function = "uartd";
  90. };
  91. gpu7 {
  92. nvidia,pins = "gpu7";
  93. nvidia,function = "rtck";
  94. };
  95. gpv {
  96. nvidia,pins = "gpv", "slxa", "slxk";
  97. nvidia,function = "pcie";
  98. };
  99. hdint {
  100. nvidia,pins = "hdint";
  101. nvidia,function = "hdmi";
  102. };
  103. i2cp {
  104. nvidia,pins = "i2cp";
  105. nvidia,function = "i2cp";
  106. };
  107. irrx {
  108. nvidia,pins = "irrx", "irtx";
  109. nvidia,function = "uarta";
  110. };
  111. kbca {
  112. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  113. "kbce", "kbcf";
  114. nvidia,function = "kbc";
  115. };
  116. lcsn {
  117. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  118. "ld3", "ld4", "ld5", "ld6", "ld7",
  119. "ld8", "ld9", "ld10", "ld11", "ld12",
  120. "ld13", "ld14", "ld15", "ld16", "ld17",
  121. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  122. "lhs", "lm0", "lm1", "lpp", "lpw0",
  123. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  124. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  125. "lvs";
  126. nvidia,function = "displaya";
  127. };
  128. owc {
  129. nvidia,pins = "owc", "spdi", "spdo", "uac";
  130. nvidia,function = "rsvd2";
  131. };
  132. pmc {
  133. nvidia,pins = "pmc";
  134. nvidia,function = "pwr_on";
  135. };
  136. rm {
  137. nvidia,pins = "rm";
  138. nvidia,function = "i2c1";
  139. };
  140. sdb {
  141. nvidia,pins = "sdb", "sdc", "sdd";
  142. nvidia,function = "pwm";
  143. };
  144. sdio1 {
  145. nvidia,pins = "sdio1";
  146. nvidia,function = "sdio1";
  147. };
  148. slxc {
  149. nvidia,pins = "slxc", "slxd";
  150. nvidia,function = "spdif";
  151. };
  152. spid {
  153. nvidia,pins = "spid", "spie", "spif";
  154. nvidia,function = "spi1";
  155. };
  156. spig {
  157. nvidia,pins = "spig", "spih";
  158. nvidia,function = "spi2_alt";
  159. };
  160. uaa {
  161. nvidia,pins = "uaa", "uab", "uda";
  162. nvidia,function = "ulpi";
  163. };
  164. uad {
  165. nvidia,pins = "uad";
  166. nvidia,function = "irda";
  167. };
  168. uca {
  169. nvidia,pins = "uca", "ucb";
  170. nvidia,function = "uartc";
  171. };
  172. conf_ata {
  173. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  174. "cdev1", "cdev2", "dap1", "dtb", "gma",
  175. "gmb", "gmc", "gmd", "gme", "gpu7",
  176. "gpv", "i2cp", "pta", "rm", "slxa",
  177. "slxk", "spia", "spib", "uac";
  178. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  179. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  180. };
  181. conf_ck32 {
  182. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  183. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  185. };
  186. conf_csus {
  187. nvidia,pins = "csus", "spid", "spif";
  188. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  189. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  190. };
  191. conf_crtp {
  192. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  193. "dtc", "dte", "dtf", "gpu", "sdio1",
  194. "slxc", "slxd", "spdi", "spdo", "spig",
  195. "uda";
  196. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  197. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  198. };
  199. conf_ddc {
  200. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  201. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  202. "sdc";
  203. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  204. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  205. };
  206. conf_hdint {
  207. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  208. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  209. "lvp0", "owc", "sdb";
  210. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  211. };
  212. conf_irrx {
  213. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  214. "spie", "spih", "uaa", "uab", "uad",
  215. "uca", "ucb";
  216. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  217. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  218. };
  219. conf_lc {
  220. nvidia,pins = "lc", "ls";
  221. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  222. };
  223. conf_ld0 {
  224. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  225. "ld5", "ld6", "ld7", "ld8", "ld9",
  226. "ld10", "ld11", "ld12", "ld13", "ld14",
  227. "ld15", "ld16", "ld17", "ldi", "lhp0",
  228. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  229. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  230. "lvs", "pmc";
  231. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  232. };
  233. conf_ld17_0 {
  234. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  235. "ld23_22";
  236. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  237. };
  238. };
  239. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  240. ddc {
  241. nvidia,pins = "ddc";
  242. nvidia,function = "i2c2";
  243. };
  244. pta {
  245. nvidia,pins = "pta";
  246. nvidia,function = "rsvd4";
  247. };
  248. };
  249. state_i2cmux_pta: pinmux_i2cmux_pta {
  250. ddc {
  251. nvidia,pins = "ddc";
  252. nvidia,function = "rsvd4";
  253. };
  254. pta {
  255. nvidia,pins = "pta";
  256. nvidia,function = "i2c2";
  257. };
  258. };
  259. state_i2cmux_idle: pinmux_i2cmux_idle {
  260. ddc {
  261. nvidia,pins = "ddc";
  262. nvidia,function = "rsvd4";
  263. };
  264. pta {
  265. nvidia,pins = "pta";
  266. nvidia,function = "rsvd4";
  267. };
  268. };
  269. };
  270. i2s@70002800 {
  271. status = "okay";
  272. };
  273. serial@70006300 {
  274. status = "okay";
  275. };
  276. i2c@7000c000 {
  277. clock-frequency = <400000>;
  278. status = "okay";
  279. };
  280. i2c@7000c400 {
  281. clock-frequency = <100000>;
  282. status = "okay";
  283. };
  284. i2cmux {
  285. compatible = "i2c-mux-pinctrl";
  286. #address-cells = <1>;
  287. #size-cells = <0>;
  288. i2c-parent = <&{/i2c@7000c400}>;
  289. pinctrl-names = "ddc", "pta", "idle";
  290. pinctrl-0 = <&state_i2cmux_ddc>;
  291. pinctrl-1 = <&state_i2cmux_pta>;
  292. pinctrl-2 = <&state_i2cmux_idle>;
  293. hdmi_ddc: i2c@0 {
  294. reg = <0>;
  295. #address-cells = <1>;
  296. #size-cells = <0>;
  297. };
  298. i2c@1 {
  299. reg = <1>;
  300. #address-cells = <1>;
  301. #size-cells = <0>;
  302. };
  303. };
  304. i2c@7000d000 {
  305. clock-frequency = <400000>;
  306. status = "okay";
  307. pmic: tps6586x@34 {
  308. compatible = "ti,tps6586x";
  309. reg = <0x34>;
  310. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  311. ti,system-power-controller;
  312. #gpio-cells = <2>;
  313. gpio-controller;
  314. /* vdd_5v0_reg must be provided by the base board */
  315. sys-supply = <&vdd_5v0_reg>;
  316. vin-sm0-supply = <&sys_reg>;
  317. vin-sm1-supply = <&sys_reg>;
  318. vin-sm2-supply = <&sys_reg>;
  319. vinldo01-supply = <&sm2_reg>;
  320. vinldo23-supply = <&sm2_reg>;
  321. vinldo4-supply = <&sm2_reg>;
  322. vinldo678-supply = <&sm2_reg>;
  323. vinldo9-supply = <&sm2_reg>;
  324. regulators {
  325. sys_reg: sys {
  326. regulator-name = "vdd_sys";
  327. regulator-always-on;
  328. };
  329. sm0 {
  330. regulator-name = "vdd_sys_sm0,vdd_core";
  331. regulator-min-microvolt = <1200000>;
  332. regulator-max-microvolt = <1200000>;
  333. regulator-always-on;
  334. };
  335. sm1 {
  336. regulator-name = "vdd_sys_sm1,vdd_cpu";
  337. regulator-min-microvolt = <1000000>;
  338. regulator-max-microvolt = <1000000>;
  339. regulator-always-on;
  340. };
  341. sm2_reg: sm2 {
  342. regulator-name = "vdd_sys_sm2,vin_ldo*";
  343. regulator-min-microvolt = <3700000>;
  344. regulator-max-microvolt = <3700000>;
  345. regulator-always-on;
  346. };
  347. pci_clk_reg: ldo0 {
  348. regulator-name = "vdd_ldo0,vddio_pex_clk";
  349. regulator-min-microvolt = <3300000>;
  350. regulator-max-microvolt = <3300000>;
  351. };
  352. ldo1 {
  353. regulator-name = "vdd_ldo1,avdd_pll*";
  354. regulator-min-microvolt = <1100000>;
  355. regulator-max-microvolt = <1100000>;
  356. regulator-always-on;
  357. };
  358. ldo2 {
  359. regulator-name = "vdd_ldo2,vdd_rtc";
  360. regulator-min-microvolt = <1200000>;
  361. regulator-max-microvolt = <1200000>;
  362. };
  363. ldo3 {
  364. regulator-name = "vdd_ldo3,avdd_usb*";
  365. regulator-min-microvolt = <3300000>;
  366. regulator-max-microvolt = <3300000>;
  367. regulator-always-on;
  368. };
  369. ldo4 {
  370. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  371. regulator-min-microvolt = <1800000>;
  372. regulator-max-microvolt = <1800000>;
  373. regulator-always-on;
  374. };
  375. ldo5 {
  376. regulator-name = "vdd_ldo5,vcore_mmc";
  377. regulator-min-microvolt = <2850000>;
  378. regulator-max-microvolt = <2850000>;
  379. };
  380. ldo6 {
  381. regulator-name = "vdd_ldo6,avdd_vdac";
  382. /*
  383. * According to the Tegra 2 Automotive
  384. * DataSheet, a typical value for this
  385. * would be 2.8V, but the PMIC only
  386. * supports 2.85V.
  387. */
  388. regulator-min-microvolt = <2850000>;
  389. regulator-max-microvolt = <2850000>;
  390. };
  391. hdmi_vdd_reg: ldo7 {
  392. regulator-name = "vdd_ldo7,avdd_hdmi";
  393. regulator-min-microvolt = <3300000>;
  394. regulator-max-microvolt = <3300000>;
  395. };
  396. hdmi_pll_reg: ldo8 {
  397. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  398. regulator-min-microvolt = <1800000>;
  399. regulator-max-microvolt = <1800000>;
  400. };
  401. ldo9 {
  402. regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
  403. /*
  404. * According to the Tegra 2 Automotive
  405. * DataSheet, a typical value for this
  406. * would be 2.8V, but the PMIC only
  407. * supports 2.85V.
  408. */
  409. regulator-min-microvolt = <2850000>;
  410. regulator-max-microvolt = <2850000>;
  411. regulator-always-on;
  412. };
  413. ldo_rtc {
  414. regulator-name = "vdd_rtc_out";
  415. regulator-min-microvolt = <3300000>;
  416. regulator-max-microvolt = <3300000>;
  417. regulator-always-on;
  418. };
  419. };
  420. };
  421. temperature-sensor@4c {
  422. compatible = "onnn,nct1008";
  423. reg = <0x4c>;
  424. };
  425. };
  426. pmc@7000e400 {
  427. nvidia,invert-interrupt;
  428. nvidia,suspend-mode = <1>;
  429. nvidia,cpu-pwr-good-time = <5000>;
  430. nvidia,cpu-pwr-off-time = <5000>;
  431. nvidia,core-pwr-good-time = <3845 3845>;
  432. nvidia,core-pwr-off-time = <3875>;
  433. nvidia,sys-clock-req-active-high;
  434. };
  435. pcie-controller@80003000 {
  436. avdd-pex-supply = <&pci_vdd_reg>;
  437. vdd-pex-supply = <&pci_vdd_reg>;
  438. avdd-pex-pll-supply = <&pci_vdd_reg>;
  439. avdd-plle-supply = <&pci_vdd_reg>;
  440. vddio-pex-clk-supply = <&pci_clk_reg>;
  441. };
  442. usb@c5008000 {
  443. status = "okay";
  444. };
  445. usb-phy@c5008000 {
  446. status = "okay";
  447. };
  448. sdhci@c8000600 {
  449. cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
  450. wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  451. bus-width = <4>;
  452. status = "okay";
  453. };
  454. clocks {
  455. compatible = "simple-bus";
  456. #address-cells = <1>;
  457. #size-cells = <0>;
  458. clk32k_in: clock@0 {
  459. compatible = "fixed-clock";
  460. reg=<0>;
  461. #clock-cells = <0>;
  462. clock-frequency = <32768>;
  463. };
  464. };
  465. regulators {
  466. compatible = "simple-bus";
  467. #address-cells = <1>;
  468. #size-cells = <0>;
  469. pci_vdd_reg: regulator@1 {
  470. compatible = "regulator-fixed";
  471. reg = <1>;
  472. regulator-name = "vdd_1v05";
  473. regulator-min-microvolt = <1050000>;
  474. regulator-max-microvolt = <1050000>;
  475. gpio = <&pmic 2 0>;
  476. enable-active-high;
  477. };
  478. };
  479. };