sst-haswell-ipc.c 45 KB

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  1. /*
  2. * Intel SST Haswell/Broadwell IPC Support
  3. *
  4. * Copyright (C) 2013, Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/device.h>
  20. #include <linux/wait.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/export.h>
  24. #include <linux/slab.h>
  25. #include <linux/delay.h>
  26. #include <linux/sched.h>
  27. #include <linux/list.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/kthread.h>
  30. #include <linux/firmware.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/debugfs.h>
  33. #include "sst-haswell-ipc.h"
  34. #include "sst-dsp.h"
  35. #include "sst-dsp-priv.h"
  36. /* Global Message - Generic */
  37. #define IPC_GLB_TYPE_SHIFT 24
  38. #define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
  39. #define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
  40. /* Global Message - Reply */
  41. #define IPC_GLB_REPLY_SHIFT 0
  42. #define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
  43. #define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
  44. /* Stream Message - Generic */
  45. #define IPC_STR_TYPE_SHIFT 20
  46. #define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
  47. #define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
  48. #define IPC_STR_ID_SHIFT 16
  49. #define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
  50. #define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
  51. /* Stream Message - Reply */
  52. #define IPC_STR_REPLY_SHIFT 0
  53. #define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
  54. /* Stream Stage Message - Generic */
  55. #define IPC_STG_TYPE_SHIFT 12
  56. #define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
  57. #define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
  58. #define IPC_STG_ID_SHIFT 10
  59. #define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
  60. #define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
  61. /* Stream Stage Message - Reply */
  62. #define IPC_STG_REPLY_SHIFT 0
  63. #define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
  64. /* Debug Log Message - Generic */
  65. #define IPC_LOG_OP_SHIFT 20
  66. #define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
  67. #define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
  68. #define IPC_LOG_ID_SHIFT 16
  69. #define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
  70. #define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
  71. /* IPC message timeout (msecs) */
  72. #define IPC_TIMEOUT_MSECS 300
  73. #define IPC_BOOT_MSECS 200
  74. #define IPC_MSG_WAIT 0
  75. #define IPC_MSG_NOWAIT 1
  76. /* Firmware Ready Message */
  77. #define IPC_FW_READY (0x1 << 29)
  78. #define IPC_STATUS_MASK (0x3 << 30)
  79. #define IPC_EMPTY_LIST_SIZE 8
  80. #define IPC_MAX_STREAMS 4
  81. /* Mailbox */
  82. #define IPC_MAX_MAILBOX_BYTES 256
  83. /* Global Message - Types and Replies */
  84. enum ipc_glb_type {
  85. IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
  86. IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
  87. IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
  88. IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
  89. IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
  90. IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
  91. /* Request to store firmware context during D0->D3 transition */
  92. IPC_GLB_REQUEST_DUMP = 7,
  93. /* Request to restore firmware context during D3->D0 transition */
  94. IPC_GLB_RESTORE_CONTEXT = 8,
  95. IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
  96. IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
  97. IPC_GLB_SHORT_REPLY = 11,
  98. IPC_GLB_ENTER_DX_STATE = 12,
  99. IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
  100. IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
  101. IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
  102. IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
  103. };
  104. enum ipc_glb_reply {
  105. IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
  106. IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
  107. IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
  108. IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
  109. IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
  110. IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
  111. IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
  112. IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
  113. IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
  114. IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
  115. IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
  116. };
  117. /* Stream Message - Types */
  118. enum ipc_str_operation {
  119. IPC_STR_RESET = 0,
  120. IPC_STR_PAUSE = 1,
  121. IPC_STR_RESUME = 2,
  122. IPC_STR_STAGE_MESSAGE = 3,
  123. IPC_STR_NOTIFICATION = 4,
  124. IPC_STR_MAX_MESSAGE
  125. };
  126. /* Stream Stage Message Types */
  127. enum ipc_stg_operation {
  128. IPC_STG_GET_VOLUME = 0,
  129. IPC_STG_SET_VOLUME,
  130. IPC_STG_SET_WRITE_POSITION,
  131. IPC_STG_SET_FX_ENABLE,
  132. IPC_STG_SET_FX_DISABLE,
  133. IPC_STG_SET_FX_GET_PARAM,
  134. IPC_STG_SET_FX_SET_PARAM,
  135. IPC_STG_SET_FX_GET_INFO,
  136. IPC_STG_MUTE_LOOPBACK,
  137. IPC_STG_MAX_MESSAGE
  138. };
  139. /* Stream Stage Message Types For Notification*/
  140. enum ipc_stg_operation_notify {
  141. IPC_POSITION_CHANGED = 0,
  142. IPC_STG_GLITCH,
  143. IPC_STG_MAX_NOTIFY
  144. };
  145. enum ipc_glitch_type {
  146. IPC_GLITCH_UNDERRUN = 1,
  147. IPC_GLITCH_DECODER_ERROR,
  148. IPC_GLITCH_DOUBLED_WRITE_POS,
  149. IPC_GLITCH_MAX
  150. };
  151. /* Debug Control */
  152. enum ipc_debug_operation {
  153. IPC_DEBUG_ENABLE_LOG = 0,
  154. IPC_DEBUG_DISABLE_LOG = 1,
  155. IPC_DEBUG_REQUEST_LOG_DUMP = 2,
  156. IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
  157. IPC_DEBUG_MAX_DEBUG_LOG
  158. };
  159. /* Firmware Ready */
  160. struct sst_hsw_ipc_fw_ready {
  161. u32 inbox_offset;
  162. u32 outbox_offset;
  163. u32 inbox_size;
  164. u32 outbox_size;
  165. u32 fw_info_size;
  166. u8 fw_info[1];
  167. } __attribute__((packed));
  168. struct ipc_message {
  169. struct list_head list;
  170. u32 header;
  171. /* direction wrt host CPU */
  172. char tx_data[IPC_MAX_MAILBOX_BYTES];
  173. size_t tx_size;
  174. char rx_data[IPC_MAX_MAILBOX_BYTES];
  175. size_t rx_size;
  176. wait_queue_head_t waitq;
  177. bool pending;
  178. bool complete;
  179. bool wait;
  180. int errno;
  181. };
  182. struct sst_hsw_stream;
  183. struct sst_hsw;
  184. /* Stream infomation */
  185. struct sst_hsw_stream {
  186. /* configuration */
  187. struct sst_hsw_ipc_stream_alloc_req request;
  188. struct sst_hsw_ipc_stream_alloc_reply reply;
  189. struct sst_hsw_ipc_stream_free_req free_req;
  190. /* Mixer info */
  191. u32 mute_volume[SST_HSW_NO_CHANNELS];
  192. u32 mute[SST_HSW_NO_CHANNELS];
  193. /* runtime info */
  194. struct sst_hsw *hsw;
  195. int host_id;
  196. bool commited;
  197. bool running;
  198. /* Notification work */
  199. struct work_struct notify_work;
  200. u32 header;
  201. /* Position info from DSP */
  202. struct sst_hsw_ipc_stream_set_position wpos;
  203. struct sst_hsw_ipc_stream_get_position rpos;
  204. struct sst_hsw_ipc_stream_glitch_position glitch;
  205. /* Volume info */
  206. struct sst_hsw_ipc_volume_req vol_req;
  207. /* driver callback */
  208. u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
  209. void *pdata;
  210. struct list_head node;
  211. };
  212. /* FW log ring information */
  213. struct sst_hsw_log_stream {
  214. dma_addr_t dma_addr;
  215. unsigned char *dma_area;
  216. unsigned char *ring_descr;
  217. int pages;
  218. int size;
  219. /* Notification work */
  220. struct work_struct notify_work;
  221. wait_queue_head_t readers_wait_q;
  222. struct mutex rw_mutex;
  223. u32 last_pos;
  224. u32 curr_pos;
  225. u32 reader_pos;
  226. /* fw log config */
  227. u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
  228. struct sst_hsw *hsw;
  229. };
  230. /* SST Haswell IPC data */
  231. struct sst_hsw {
  232. struct device *dev;
  233. struct sst_dsp *dsp;
  234. struct platform_device *pdev_pcm;
  235. /* FW config */
  236. struct sst_hsw_ipc_fw_ready fw_ready;
  237. struct sst_hsw_ipc_fw_version version;
  238. struct sst_module *scratch;
  239. bool fw_done;
  240. /* stream */
  241. struct list_head stream_list;
  242. /* global mixer */
  243. struct sst_hsw_ipc_stream_info_reply mixer_info;
  244. enum sst_hsw_volume_curve curve_type;
  245. u32 curve_duration;
  246. u32 mute[SST_HSW_NO_CHANNELS];
  247. u32 mute_volume[SST_HSW_NO_CHANNELS];
  248. /* DX */
  249. struct sst_hsw_ipc_dx_reply dx;
  250. /* boot */
  251. wait_queue_head_t boot_wait;
  252. bool boot_complete;
  253. bool shutdown;
  254. /* IPC messaging */
  255. struct list_head tx_list;
  256. struct list_head rx_list;
  257. struct list_head empty_list;
  258. wait_queue_head_t wait_txq;
  259. struct task_struct *tx_thread;
  260. struct kthread_worker kworker;
  261. struct kthread_work kwork;
  262. bool pending;
  263. struct ipc_message *msg;
  264. /* FW log stream */
  265. struct sst_hsw_log_stream log_stream;
  266. };
  267. #define CREATE_TRACE_POINTS
  268. #include <trace/events/hswadsp.h>
  269. static inline u32 msg_get_global_type(u32 msg)
  270. {
  271. return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
  272. }
  273. static inline u32 msg_get_global_reply(u32 msg)
  274. {
  275. return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
  276. }
  277. static inline u32 msg_get_stream_type(u32 msg)
  278. {
  279. return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
  280. }
  281. static inline u32 msg_get_stage_type(u32 msg)
  282. {
  283. return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
  284. }
  285. static inline u32 msg_set_stage_type(u32 msg, u32 type)
  286. {
  287. return (msg & ~IPC_STG_TYPE_MASK) +
  288. (type << IPC_STG_TYPE_SHIFT);
  289. }
  290. static inline u32 msg_get_stream_id(u32 msg)
  291. {
  292. return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
  293. }
  294. static inline u32 msg_get_notify_reason(u32 msg)
  295. {
  296. return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
  297. }
  298. u32 create_channel_map(enum sst_hsw_channel_config config)
  299. {
  300. switch (config) {
  301. case SST_HSW_CHANNEL_CONFIG_MONO:
  302. return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
  303. case SST_HSW_CHANNEL_CONFIG_STEREO:
  304. return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
  305. | (SST_HSW_CHANNEL_RIGHT << 4));
  306. case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
  307. return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
  308. | (SST_HSW_CHANNEL_RIGHT << 4)
  309. | (SST_HSW_CHANNEL_LFE << 8 ));
  310. case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
  311. return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
  312. | (SST_HSW_CHANNEL_CENTER << 4)
  313. | (SST_HSW_CHANNEL_RIGHT << 8));
  314. case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
  315. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  316. | (SST_HSW_CHANNEL_CENTER << 4)
  317. | (SST_HSW_CHANNEL_RIGHT << 8)
  318. | (SST_HSW_CHANNEL_LFE << 12));
  319. case SST_HSW_CHANNEL_CONFIG_QUATRO:
  320. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  321. | (SST_HSW_CHANNEL_RIGHT << 4)
  322. | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
  323. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
  324. case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
  325. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  326. | (SST_HSW_CHANNEL_CENTER << 4)
  327. | (SST_HSW_CHANNEL_RIGHT << 8)
  328. | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
  329. case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
  330. return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
  331. | (SST_HSW_CHANNEL_CENTER << 4)
  332. | (SST_HSW_CHANNEL_RIGHT << 8)
  333. | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
  334. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
  335. case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
  336. return (0xFF000000 | SST_HSW_CHANNEL_CENTER
  337. | (SST_HSW_CHANNEL_LEFT << 4)
  338. | (SST_HSW_CHANNEL_RIGHT << 8)
  339. | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
  340. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
  341. | (SST_HSW_CHANNEL_LFE << 20));
  342. case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
  343. return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
  344. | (SST_HSW_CHANNEL_LEFT << 4));
  345. default:
  346. return 0xFFFFFFFF;
  347. }
  348. }
  349. static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
  350. int stream_id)
  351. {
  352. struct sst_hsw_stream *stream;
  353. list_for_each_entry(stream, &hsw->stream_list, node) {
  354. if (stream->reply.stream_hw_id == stream_id)
  355. return stream;
  356. }
  357. return NULL;
  358. }
  359. static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
  360. {
  361. struct sst_dsp *sst = hsw->dsp;
  362. u32 isr, ipcd, imrx, ipcx;
  363. ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
  364. isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
  365. ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  366. imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
  367. dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
  368. text, ipcx, isr, ipcd, imrx);
  369. }
  370. /* locks held by caller */
  371. static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
  372. {
  373. struct ipc_message *msg = NULL;
  374. if (!list_empty(&hsw->empty_list)) {
  375. msg = list_first_entry(&hsw->empty_list, struct ipc_message,
  376. list);
  377. list_del(&msg->list);
  378. }
  379. return msg;
  380. }
  381. static void ipc_tx_msgs(struct kthread_work *work)
  382. {
  383. struct sst_hsw *hsw =
  384. container_of(work, struct sst_hsw, kwork);
  385. struct ipc_message *msg;
  386. unsigned long flags;
  387. u32 ipcx;
  388. spin_lock_irqsave(&hsw->dsp->spinlock, flags);
  389. if (list_empty(&hsw->tx_list) || hsw->pending) {
  390. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  391. return;
  392. }
  393. /* if the DSP is busy we will TX messages after IRQ */
  394. ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
  395. if (ipcx & SST_IPCX_BUSY) {
  396. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  397. return;
  398. }
  399. msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
  400. list_move(&msg->list, &hsw->rx_list);
  401. /* send the message */
  402. sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
  403. sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
  404. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  405. }
  406. /* locks held by caller */
  407. static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
  408. {
  409. msg->complete = true;
  410. trace_ipc_reply("completed", msg->header);
  411. if (!msg->wait)
  412. list_add_tail(&msg->list, &hsw->empty_list);
  413. else
  414. wake_up(&msg->waitq);
  415. }
  416. static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
  417. void *rx_data)
  418. {
  419. unsigned long flags;
  420. int ret;
  421. /* wait for DSP completion (in all cases atm inc pending) */
  422. ret = wait_event_timeout(msg->waitq, msg->complete,
  423. msecs_to_jiffies(IPC_TIMEOUT_MSECS));
  424. spin_lock_irqsave(&hsw->dsp->spinlock, flags);
  425. if (ret == 0) {
  426. ipc_shim_dbg(hsw, "message timeout");
  427. trace_ipc_error("error message timeout for", msg->header);
  428. ret = -ETIMEDOUT;
  429. } else {
  430. /* copy the data returned from DSP */
  431. if (msg->rx_size)
  432. memcpy(rx_data, msg->rx_data, msg->rx_size);
  433. ret = msg->errno;
  434. }
  435. list_add_tail(&msg->list, &hsw->empty_list);
  436. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  437. return ret;
  438. }
  439. static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
  440. size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
  441. {
  442. struct ipc_message *msg;
  443. unsigned long flags;
  444. spin_lock_irqsave(&hsw->dsp->spinlock, flags);
  445. msg = msg_get_empty(hsw);
  446. if (msg == NULL) {
  447. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  448. return -EBUSY;
  449. }
  450. if (tx_bytes)
  451. memcpy(msg->tx_data, tx_data, tx_bytes);
  452. msg->header = header;
  453. msg->tx_size = tx_bytes;
  454. msg->rx_size = rx_bytes;
  455. msg->wait = wait;
  456. msg->errno = 0;
  457. msg->pending = false;
  458. msg->complete = false;
  459. list_add_tail(&msg->list, &hsw->tx_list);
  460. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  461. queue_kthread_work(&hsw->kworker, &hsw->kwork);
  462. if (wait)
  463. return tx_wait_done(hsw, msg, rx_data);
  464. else
  465. return 0;
  466. }
  467. static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
  468. void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
  469. {
  470. return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
  471. rx_bytes, 1);
  472. }
  473. static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
  474. void *tx_data, size_t tx_bytes)
  475. {
  476. return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
  477. }
  478. static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
  479. {
  480. struct sst_hsw_ipc_fw_ready fw_ready;
  481. u32 offset;
  482. offset = (header & 0x1FFFFFFF) << 3;
  483. dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
  484. header, offset);
  485. /* copy data from the DSP FW ready offset */
  486. sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
  487. sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
  488. fw_ready.inbox_size, fw_ready.outbox_offset,
  489. fw_ready.outbox_size);
  490. hsw->boot_complete = true;
  491. wake_up(&hsw->boot_wait);
  492. dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
  493. fw_ready.inbox_offset, fw_ready.inbox_size);
  494. dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
  495. fw_ready.outbox_offset, fw_ready.outbox_size);
  496. }
  497. static void hsw_notification_work(struct work_struct *work)
  498. {
  499. struct sst_hsw_stream *stream = container_of(work,
  500. struct sst_hsw_stream, notify_work);
  501. struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
  502. struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
  503. struct sst_hsw *hsw = stream->hsw;
  504. u32 reason;
  505. reason = msg_get_notify_reason(stream->header);
  506. switch (reason) {
  507. case IPC_STG_GLITCH:
  508. trace_ipc_notification("DSP stream under/overrun",
  509. stream->reply.stream_hw_id);
  510. sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
  511. dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
  512. glitch->glitch_type, glitch->present_pos,
  513. glitch->write_pos);
  514. break;
  515. case IPC_POSITION_CHANGED:
  516. trace_ipc_notification("DSP stream position changed for",
  517. stream->reply.stream_hw_id);
  518. sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
  519. if (stream->notify_position)
  520. stream->notify_position(stream, stream->pdata);
  521. break;
  522. default:
  523. dev_err(hsw->dev, "error: unknown notification 0x%x\n",
  524. stream->header);
  525. break;
  526. }
  527. /* tell DSP that notification has been handled */
  528. sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,
  529. SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
  530. /* unmask busy interrupt */
  531. sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
  532. }
  533. static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
  534. {
  535. struct ipc_message *msg;
  536. /* clear reply bits & status bits */
  537. header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
  538. if (list_empty(&hsw->rx_list)) {
  539. dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
  540. header);
  541. return NULL;
  542. }
  543. list_for_each_entry(msg, &hsw->rx_list, list) {
  544. if (msg->header == header)
  545. return msg;
  546. }
  547. return NULL;
  548. }
  549. static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
  550. {
  551. struct sst_hsw_stream *stream;
  552. u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
  553. u32 stream_id = msg_get_stream_id(header);
  554. u32 stream_msg = msg_get_stream_type(header);
  555. stream = get_stream_by_id(hsw, stream_id);
  556. if (stream == NULL)
  557. return;
  558. switch (stream_msg) {
  559. case IPC_STR_STAGE_MESSAGE:
  560. case IPC_STR_NOTIFICATION:
  561. case IPC_STR_RESET:
  562. break;
  563. case IPC_STR_PAUSE:
  564. stream->running = false;
  565. trace_ipc_notification("stream paused",
  566. stream->reply.stream_hw_id);
  567. break;
  568. case IPC_STR_RESUME:
  569. stream->running = true;
  570. trace_ipc_notification("stream running",
  571. stream->reply.stream_hw_id);
  572. break;
  573. }
  574. }
  575. static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
  576. {
  577. struct ipc_message *msg;
  578. u32 reply = msg_get_global_reply(header);
  579. trace_ipc_reply("processing -->", header);
  580. msg = reply_find_msg(hsw, header);
  581. if (msg == NULL) {
  582. trace_ipc_error("error: can't find message header", header);
  583. return -EIO;
  584. }
  585. /* first process the header */
  586. switch (reply) {
  587. case IPC_GLB_REPLY_PENDING:
  588. trace_ipc_pending_reply("received", header);
  589. msg->pending = true;
  590. hsw->pending = true;
  591. return 1;
  592. case IPC_GLB_REPLY_SUCCESS:
  593. if (msg->pending) {
  594. trace_ipc_pending_reply("completed", header);
  595. sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
  596. msg->rx_size);
  597. hsw->pending = false;
  598. } else {
  599. /* copy data from the DSP */
  600. sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
  601. msg->rx_size);
  602. }
  603. break;
  604. /* these will be rare - but useful for debug */
  605. case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
  606. trace_ipc_error("error: unknown message type", header);
  607. msg->errno = -EBADMSG;
  608. break;
  609. case IPC_GLB_REPLY_OUT_OF_RESOURCES:
  610. trace_ipc_error("error: out of resources", header);
  611. msg->errno = -ENOMEM;
  612. break;
  613. case IPC_GLB_REPLY_BUSY:
  614. trace_ipc_error("error: reply busy", header);
  615. msg->errno = -EBUSY;
  616. break;
  617. case IPC_GLB_REPLY_FAILURE:
  618. trace_ipc_error("error: reply failure", header);
  619. msg->errno = -EINVAL;
  620. break;
  621. case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
  622. trace_ipc_error("error: stage uninitialized", header);
  623. msg->errno = -EINVAL;
  624. break;
  625. case IPC_GLB_REPLY_NOT_FOUND:
  626. trace_ipc_error("error: reply not found", header);
  627. msg->errno = -EINVAL;
  628. break;
  629. case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
  630. trace_ipc_error("error: source not started", header);
  631. msg->errno = -EINVAL;
  632. break;
  633. case IPC_GLB_REPLY_INVALID_REQUEST:
  634. trace_ipc_error("error: invalid request", header);
  635. msg->errno = -EINVAL;
  636. break;
  637. case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
  638. trace_ipc_error("error: invalid parameter", header);
  639. msg->errno = -EINVAL;
  640. break;
  641. default:
  642. trace_ipc_error("error: unknown reply", header);
  643. msg->errno = -EINVAL;
  644. break;
  645. }
  646. /* update any stream states */
  647. hsw_stream_update(hsw, msg);
  648. /* wake up and return the error if we have waiters on this message ? */
  649. list_del(&msg->list);
  650. tx_msg_reply_complete(hsw, msg);
  651. return 1;
  652. }
  653. static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
  654. {
  655. u32 stream_msg, stream_id, stage_type;
  656. struct sst_hsw_stream *stream;
  657. int handled = 0;
  658. stream_msg = msg_get_stream_type(header);
  659. stream_id = msg_get_stream_id(header);
  660. stage_type = msg_get_stage_type(header);
  661. stream = get_stream_by_id(hsw, stream_id);
  662. if (stream == NULL)
  663. return handled;
  664. stream->header = header;
  665. switch (stream_msg) {
  666. case IPC_STR_STAGE_MESSAGE:
  667. dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
  668. header);
  669. break;
  670. case IPC_STR_NOTIFICATION:
  671. schedule_work(&stream->notify_work);
  672. break;
  673. default:
  674. /* handle pending message complete request */
  675. handled = hsw_process_reply(hsw, header);
  676. break;
  677. }
  678. return handled;
  679. }
  680. static int hsw_log_message(struct sst_hsw *hsw, u32 header)
  681. {
  682. u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
  683. struct sst_hsw_log_stream *stream = &hsw->log_stream;
  684. int ret = 1;
  685. if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
  686. dev_err(hsw->dev,
  687. "error: log msg not implemented 0x%8.8x\n", header);
  688. return 0;
  689. }
  690. mutex_lock(&stream->rw_mutex);
  691. stream->last_pos = stream->curr_pos;
  692. sst_dsp_inbox_read(
  693. hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
  694. mutex_unlock(&stream->rw_mutex);
  695. schedule_work(&stream->notify_work);
  696. return ret;
  697. }
  698. static int hsw_process_notification(struct sst_hsw *hsw)
  699. {
  700. struct sst_dsp *sst = hsw->dsp;
  701. u32 type, header;
  702. int handled = 1;
  703. header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  704. type = msg_get_global_type(header);
  705. trace_ipc_request("processing -->", header);
  706. /* FW Ready is a special case */
  707. if (!hsw->boot_complete && header & IPC_FW_READY) {
  708. hsw_fw_ready(hsw, header);
  709. return handled;
  710. }
  711. switch (type) {
  712. case IPC_GLB_GET_FW_VERSION:
  713. case IPC_GLB_ALLOCATE_STREAM:
  714. case IPC_GLB_FREE_STREAM:
  715. case IPC_GLB_GET_FW_CAPABILITIES:
  716. case IPC_GLB_REQUEST_DUMP:
  717. case IPC_GLB_GET_DEVICE_FORMATS:
  718. case IPC_GLB_SET_DEVICE_FORMATS:
  719. case IPC_GLB_ENTER_DX_STATE:
  720. case IPC_GLB_GET_MIXER_STREAM_INFO:
  721. case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
  722. case IPC_GLB_RESTORE_CONTEXT:
  723. case IPC_GLB_SHORT_REPLY:
  724. dev_err(hsw->dev, "error: message type %d header 0x%x\n",
  725. type, header);
  726. break;
  727. case IPC_GLB_STREAM_MESSAGE:
  728. handled = hsw_stream_message(hsw, header);
  729. break;
  730. case IPC_GLB_DEBUG_LOG_MESSAGE:
  731. handled = hsw_log_message(hsw, header);
  732. break;
  733. default:
  734. dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
  735. type, header);
  736. break;
  737. }
  738. return handled;
  739. }
  740. static irqreturn_t hsw_irq_thread(int irq, void *context)
  741. {
  742. struct sst_dsp *sst = (struct sst_dsp *) context;
  743. struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
  744. u32 ipcx, ipcd;
  745. int handled;
  746. unsigned long flags;
  747. spin_lock_irqsave(&sst->spinlock, flags);
  748. ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
  749. ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  750. /* reply message from DSP */
  751. if (ipcx & SST_IPCX_DONE) {
  752. /* Handle Immediate reply from DSP Core */
  753. handled = hsw_process_reply(hsw, ipcx);
  754. if (handled > 0) {
  755. /* clear DONE bit - tell DSP we have completed */
  756. sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
  757. SST_IPCX_DONE, 0);
  758. /* unmask Done interrupt */
  759. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  760. SST_IMRX_DONE, 0);
  761. }
  762. }
  763. /* new message from DSP */
  764. if (ipcd & SST_IPCD_BUSY) {
  765. /* Handle Notification and Delayed reply from DSP Core */
  766. handled = hsw_process_notification(hsw);
  767. /* clear BUSY bit and set DONE bit - accept new messages */
  768. if (handled > 0) {
  769. sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
  770. SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
  771. /* unmask busy interrupt */
  772. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  773. SST_IMRX_BUSY, 0);
  774. }
  775. }
  776. spin_unlock_irqrestore(&sst->spinlock, flags);
  777. /* continue to send any remaining messages... */
  778. queue_kthread_work(&hsw->kworker, &hsw->kwork);
  779. return IRQ_HANDLED;
  780. }
  781. int sst_hsw_fw_get_version(struct sst_hsw *hsw,
  782. struct sst_hsw_ipc_fw_version *version)
  783. {
  784. int ret;
  785. ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
  786. NULL, 0, version, sizeof(*version));
  787. if (ret < 0)
  788. dev_err(hsw->dev, "error: get version failed\n");
  789. return ret;
  790. }
  791. /* Mixer Controls */
  792. int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  793. u32 stage_id, u32 channel)
  794. {
  795. int ret;
  796. ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
  797. &stream->mute_volume[channel]);
  798. if (ret < 0)
  799. return ret;
  800. ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
  801. if (ret < 0) {
  802. dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
  803. stream->reply.stream_hw_id, channel);
  804. return ret;
  805. }
  806. stream->mute[channel] = 1;
  807. return 0;
  808. }
  809. int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  810. u32 stage_id, u32 channel)
  811. {
  812. int ret;
  813. stream->mute[channel] = 0;
  814. ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
  815. stream->mute_volume[channel]);
  816. if (ret < 0) {
  817. dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
  818. stream->reply.stream_hw_id, channel);
  819. return ret;
  820. }
  821. return 0;
  822. }
  823. int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  824. u32 stage_id, u32 channel, u32 *volume)
  825. {
  826. if (channel > 1)
  827. return -EINVAL;
  828. sst_dsp_read(hsw->dsp, volume,
  829. stream->reply.volume_register_address[channel],
  830. sizeof(*volume));
  831. return 0;
  832. }
  833. int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
  834. struct sst_hsw_stream *stream, u64 curve_duration,
  835. enum sst_hsw_volume_curve curve)
  836. {
  837. /* curve duration in steps of 100ns */
  838. stream->vol_req.curve_duration = curve_duration;
  839. stream->vol_req.curve_type = curve;
  840. return 0;
  841. }
  842. /* stream volume */
  843. int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
  844. struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
  845. {
  846. struct sst_hsw_ipc_volume_req *req;
  847. u32 header;
  848. int ret;
  849. trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
  850. if (channel > 1)
  851. return -EINVAL;
  852. if (stream->mute[channel]) {
  853. stream->mute_volume[channel] = volume;
  854. return 0;
  855. }
  856. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  857. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  858. header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
  859. header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
  860. header |= (stage_id << IPC_STG_ID_SHIFT);
  861. req = &stream->vol_req;
  862. req->channel = channel;
  863. req->target_volume = volume;
  864. ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
  865. if (ret < 0) {
  866. dev_err(hsw->dev, "error: set stream volume failed\n");
  867. return ret;
  868. }
  869. return 0;
  870. }
  871. int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
  872. {
  873. int ret;
  874. ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
  875. &hsw->mute_volume[channel]);
  876. if (ret < 0)
  877. return ret;
  878. ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
  879. if (ret < 0) {
  880. dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
  881. channel);
  882. return ret;
  883. }
  884. hsw->mute[channel] = 1;
  885. return 0;
  886. }
  887. int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
  888. {
  889. int ret;
  890. ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
  891. hsw->mixer_info.volume_register_address[channel]);
  892. if (ret < 0) {
  893. dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
  894. channel);
  895. return ret;
  896. }
  897. hsw->mute[channel] = 0;
  898. return 0;
  899. }
  900. int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
  901. u32 *volume)
  902. {
  903. if (channel > 1)
  904. return -EINVAL;
  905. sst_dsp_read(hsw->dsp, volume,
  906. hsw->mixer_info.volume_register_address[channel],
  907. sizeof(*volume));
  908. return 0;
  909. }
  910. int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
  911. u64 curve_duration, enum sst_hsw_volume_curve curve)
  912. {
  913. /* curve duration in steps of 100ns */
  914. hsw->curve_duration = curve_duration;
  915. hsw->curve_type = curve;
  916. return 0;
  917. }
  918. /* global mixer volume */
  919. int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
  920. u32 volume)
  921. {
  922. struct sst_hsw_ipc_volume_req req;
  923. u32 header;
  924. int ret;
  925. trace_ipc_request("set mixer volume", volume);
  926. /* set both at same time ? */
  927. if (channel == 2) {
  928. if (hsw->mute[0] && hsw->mute[1]) {
  929. hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
  930. return 0;
  931. } else if (hsw->mute[0])
  932. req.channel = 1;
  933. else if (hsw->mute[1])
  934. req.channel = 0;
  935. else
  936. req.channel = 0xffffffff;
  937. } else {
  938. /* set only 1 channel */
  939. if (hsw->mute[channel]) {
  940. hsw->mute_volume[channel] = volume;
  941. return 0;
  942. }
  943. req.channel = channel;
  944. }
  945. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  946. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  947. header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
  948. header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
  949. header |= (stage_id << IPC_STG_ID_SHIFT);
  950. req.curve_duration = hsw->curve_duration;
  951. req.curve_type = hsw->curve_type;
  952. req.target_volume = volume;
  953. ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
  954. if (ret < 0) {
  955. dev_err(hsw->dev, "error: set mixer volume failed\n");
  956. return ret;
  957. }
  958. return 0;
  959. }
  960. /* Stream API */
  961. struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
  962. u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
  963. void *data)
  964. {
  965. struct sst_hsw_stream *stream;
  966. struct sst_dsp *sst = hsw->dsp;
  967. unsigned long flags;
  968. stream = kzalloc(sizeof(*stream), GFP_KERNEL);
  969. if (stream == NULL)
  970. return NULL;
  971. spin_lock_irqsave(&sst->spinlock, flags);
  972. list_add(&stream->node, &hsw->stream_list);
  973. stream->notify_position = notify_position;
  974. stream->pdata = data;
  975. stream->hsw = hsw;
  976. stream->host_id = id;
  977. /* work to process notification messages */
  978. INIT_WORK(&stream->notify_work, hsw_notification_work);
  979. spin_unlock_irqrestore(&sst->spinlock, flags);
  980. return stream;
  981. }
  982. int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  983. {
  984. u32 header;
  985. int ret = 0;
  986. struct sst_dsp *sst = hsw->dsp;
  987. unsigned long flags;
  988. /* dont free DSP streams that are not commited */
  989. if (!stream->commited)
  990. goto out;
  991. trace_ipc_request("stream free", stream->host_id);
  992. stream->free_req.stream_id = stream->reply.stream_hw_id;
  993. header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
  994. ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
  995. sizeof(stream->free_req), NULL, 0);
  996. if (ret < 0) {
  997. dev_err(hsw->dev, "error: free stream %d failed\n",
  998. stream->free_req.stream_id);
  999. return -EAGAIN;
  1000. }
  1001. trace_hsw_stream_free_req(stream, &stream->free_req);
  1002. out:
  1003. cancel_work_sync(&stream->notify_work);
  1004. spin_lock_irqsave(&sst->spinlock, flags);
  1005. list_del(&stream->node);
  1006. kfree(stream);
  1007. spin_unlock_irqrestore(&sst->spinlock, flags);
  1008. return ret;
  1009. }
  1010. int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
  1011. struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
  1012. {
  1013. if (stream->commited) {
  1014. dev_err(hsw->dev, "error: stream committed for set bits\n");
  1015. return -EINVAL;
  1016. }
  1017. stream->request.format.bitdepth = bits;
  1018. return 0;
  1019. }
  1020. int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
  1021. struct sst_hsw_stream *stream, int channels)
  1022. {
  1023. if (stream->commited) {
  1024. dev_err(hsw->dev, "error: stream committed for set channels\n");
  1025. return -EINVAL;
  1026. }
  1027. /* stereo is only supported atm */
  1028. if (channels != 2)
  1029. return -EINVAL;
  1030. stream->request.format.ch_num = channels;
  1031. return 0;
  1032. }
  1033. int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
  1034. struct sst_hsw_stream *stream, int rate)
  1035. {
  1036. if (stream->commited) {
  1037. dev_err(hsw->dev, "error: stream committed for set rate\n");
  1038. return -EINVAL;
  1039. }
  1040. stream->request.format.frequency = rate;
  1041. return 0;
  1042. }
  1043. int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
  1044. struct sst_hsw_stream *stream, u32 map,
  1045. enum sst_hsw_channel_config config)
  1046. {
  1047. if (stream->commited) {
  1048. dev_err(hsw->dev, "error: stream committed for set map\n");
  1049. return -EINVAL;
  1050. }
  1051. stream->request.format.map = map;
  1052. stream->request.format.config = config;
  1053. return 0;
  1054. }
  1055. int sst_hsw_stream_set_style(struct sst_hsw *hsw,
  1056. struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
  1057. {
  1058. if (stream->commited) {
  1059. dev_err(hsw->dev, "error: stream committed for set style\n");
  1060. return -EINVAL;
  1061. }
  1062. stream->request.format.style = style;
  1063. return 0;
  1064. }
  1065. int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
  1066. struct sst_hsw_stream *stream, u32 bits)
  1067. {
  1068. if (stream->commited) {
  1069. dev_err(hsw->dev, "error: stream committed for set valid bits\n");
  1070. return -EINVAL;
  1071. }
  1072. stream->request.format.valid_bit = bits;
  1073. return 0;
  1074. }
  1075. /* Stream Configuration */
  1076. int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1077. enum sst_hsw_stream_path_id path_id,
  1078. enum sst_hsw_stream_type stream_type,
  1079. enum sst_hsw_stream_format format_id)
  1080. {
  1081. if (stream->commited) {
  1082. dev_err(hsw->dev, "error: stream committed for set format\n");
  1083. return -EINVAL;
  1084. }
  1085. stream->request.path_id = path_id;
  1086. stream->request.stream_type = stream_type;
  1087. stream->request.format_id = format_id;
  1088. trace_hsw_stream_alloc_request(stream, &stream->request);
  1089. return 0;
  1090. }
  1091. int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1092. u32 ring_pt_address, u32 num_pages,
  1093. u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
  1094. {
  1095. if (stream->commited) {
  1096. dev_err(hsw->dev, "error: stream committed for buffer\n");
  1097. return -EINVAL;
  1098. }
  1099. stream->request.ringinfo.ring_pt_address = ring_pt_address;
  1100. stream->request.ringinfo.num_pages = num_pages;
  1101. stream->request.ringinfo.ring_size = ring_size;
  1102. stream->request.ringinfo.ring_offset = ring_offset;
  1103. stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
  1104. trace_hsw_stream_buffer(stream);
  1105. return 0;
  1106. }
  1107. int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
  1108. struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
  1109. u32 entry_point)
  1110. {
  1111. struct sst_hsw_module_map *map = &stream->request.map;
  1112. if (stream->commited) {
  1113. dev_err(hsw->dev, "error: stream committed for set module\n");
  1114. return -EINVAL;
  1115. }
  1116. /* only support initial module atm */
  1117. map->module_entries_count = 1;
  1118. map->module_entries[0].module_id = module_id;
  1119. map->module_entries[0].entry_point = entry_point;
  1120. return 0;
  1121. }
  1122. int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
  1123. struct sst_hsw_stream *stream, u32 offset, u32 size)
  1124. {
  1125. if (stream->commited) {
  1126. dev_err(hsw->dev, "error: stream committed for set pmem\n");
  1127. return -EINVAL;
  1128. }
  1129. stream->request.persistent_mem.offset = offset;
  1130. stream->request.persistent_mem.size = size;
  1131. return 0;
  1132. }
  1133. int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
  1134. struct sst_hsw_stream *stream, u32 offset, u32 size)
  1135. {
  1136. if (stream->commited) {
  1137. dev_err(hsw->dev, "error: stream committed for set smem\n");
  1138. return -EINVAL;
  1139. }
  1140. stream->request.scratch_mem.offset = offset;
  1141. stream->request.scratch_mem.size = size;
  1142. return 0;
  1143. }
  1144. int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  1145. {
  1146. struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
  1147. struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
  1148. u32 header;
  1149. int ret;
  1150. trace_ipc_request("stream alloc", stream->host_id);
  1151. header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
  1152. ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
  1153. reply, sizeof(*reply));
  1154. if (ret < 0) {
  1155. dev_err(hsw->dev, "error: stream commit failed\n");
  1156. return ret;
  1157. }
  1158. stream->commited = 1;
  1159. trace_hsw_stream_alloc_reply(stream);
  1160. return 0;
  1161. }
  1162. /* Stream Information - these calls could be inline but we want the IPC
  1163. ABI to be opaque to client PCM drivers to cope with any future ABI changes */
  1164. int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
  1165. struct sst_hsw_stream *stream)
  1166. {
  1167. return stream->reply.stream_hw_id;
  1168. }
  1169. int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
  1170. struct sst_hsw_stream *stream)
  1171. {
  1172. return stream->reply.mixer_hw_id;
  1173. }
  1174. u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
  1175. struct sst_hsw_stream *stream)
  1176. {
  1177. return stream->reply.read_position_register_address;
  1178. }
  1179. u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
  1180. struct sst_hsw_stream *stream)
  1181. {
  1182. return stream->reply.presentation_position_register_address;
  1183. }
  1184. u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
  1185. struct sst_hsw_stream *stream, u32 channel)
  1186. {
  1187. if (channel >= 2)
  1188. return 0;
  1189. return stream->reply.peak_meter_register_address[channel];
  1190. }
  1191. u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
  1192. struct sst_hsw_stream *stream, u32 channel)
  1193. {
  1194. if (channel >= 2)
  1195. return 0;
  1196. return stream->reply.volume_register_address[channel];
  1197. }
  1198. int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
  1199. {
  1200. struct sst_hsw_ipc_stream_info_reply *reply;
  1201. u32 header;
  1202. int ret;
  1203. reply = &hsw->mixer_info;
  1204. header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
  1205. trace_ipc_request("get global mixer info", 0);
  1206. ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
  1207. if (ret < 0) {
  1208. dev_err(hsw->dev, "error: get stream info failed\n");
  1209. return ret;
  1210. }
  1211. trace_hsw_mixer_info_reply(reply);
  1212. return 0;
  1213. }
  1214. /* Send stream command */
  1215. static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
  1216. int stream_id, int wait)
  1217. {
  1218. u32 header;
  1219. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
  1220. header |= (stream_id << IPC_STR_ID_SHIFT);
  1221. if (wait)
  1222. return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
  1223. else
  1224. return ipc_tx_message_nowait(hsw, header, NULL, 0);
  1225. }
  1226. /* Stream ALSA trigger operations */
  1227. int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1228. int wait)
  1229. {
  1230. int ret;
  1231. trace_ipc_request("stream pause", stream->reply.stream_hw_id);
  1232. ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
  1233. stream->reply.stream_hw_id, wait);
  1234. if (ret < 0)
  1235. dev_err(hsw->dev, "error: failed to pause stream %d\n",
  1236. stream->reply.stream_hw_id);
  1237. return ret;
  1238. }
  1239. int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1240. int wait)
  1241. {
  1242. int ret;
  1243. trace_ipc_request("stream resume", stream->reply.stream_hw_id);
  1244. ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
  1245. stream->reply.stream_hw_id, wait);
  1246. if (ret < 0)
  1247. dev_err(hsw->dev, "error: failed to resume stream %d\n",
  1248. stream->reply.stream_hw_id);
  1249. return ret;
  1250. }
  1251. int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  1252. {
  1253. int ret, tries = 10;
  1254. /* dont reset streams that are not commited */
  1255. if (!stream->commited)
  1256. return 0;
  1257. /* wait for pause to complete before we reset the stream */
  1258. while (stream->running && tries--)
  1259. msleep(1);
  1260. if (!tries) {
  1261. dev_err(hsw->dev, "error: reset stream %d still running\n",
  1262. stream->reply.stream_hw_id);
  1263. return -EINVAL;
  1264. }
  1265. trace_ipc_request("stream reset", stream->reply.stream_hw_id);
  1266. ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
  1267. stream->reply.stream_hw_id, 1);
  1268. if (ret < 0)
  1269. dev_err(hsw->dev, "error: failed to reset stream %d\n",
  1270. stream->reply.stream_hw_id);
  1271. return ret;
  1272. }
  1273. /* Stream pointer positions */
  1274. u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
  1275. struct sst_hsw_stream *stream)
  1276. {
  1277. u32 rpos;
  1278. sst_dsp_read(hsw->dsp, &rpos,
  1279. stream->reply.read_position_register_address, sizeof(rpos));
  1280. return rpos;
  1281. }
  1282. /* Stream presentation (monotonic) positions */
  1283. u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
  1284. struct sst_hsw_stream *stream)
  1285. {
  1286. u64 ppos;
  1287. sst_dsp_read(hsw->dsp, &ppos,
  1288. stream->reply.presentation_position_register_address,
  1289. sizeof(ppos));
  1290. return ppos;
  1291. }
  1292. int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
  1293. struct sst_hsw_stream *stream, u32 stage_id, u32 position)
  1294. {
  1295. u32 header;
  1296. int ret;
  1297. trace_stream_write_position(stream->reply.stream_hw_id, position);
  1298. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  1299. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  1300. header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
  1301. header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
  1302. header |= (stage_id << IPC_STG_ID_SHIFT);
  1303. stream->wpos.position = position;
  1304. ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
  1305. sizeof(stream->wpos));
  1306. if (ret < 0)
  1307. dev_err(hsw->dev, "error: stream %d set position %d failed\n",
  1308. stream->reply.stream_hw_id, position);
  1309. return ret;
  1310. }
  1311. /* physical BE config */
  1312. int sst_hsw_device_set_config(struct sst_hsw *hsw,
  1313. enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
  1314. enum sst_hsw_device_mode mode, u32 clock_divider)
  1315. {
  1316. struct sst_hsw_ipc_device_config_req config;
  1317. u32 header;
  1318. int ret;
  1319. trace_ipc_request("set device config", dev);
  1320. config.ssp_interface = dev;
  1321. config.clock_frequency = mclk;
  1322. config.mode = mode;
  1323. config.clock_divider = clock_divider;
  1324. trace_hsw_device_config_req(&config);
  1325. header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
  1326. ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
  1327. NULL, 0);
  1328. if (ret < 0)
  1329. dev_err(hsw->dev, "error: set device formats failed\n");
  1330. return ret;
  1331. }
  1332. EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
  1333. /* DX Config */
  1334. int sst_hsw_dx_set_state(struct sst_hsw *hsw,
  1335. enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
  1336. {
  1337. u32 header, state_;
  1338. int ret;
  1339. header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
  1340. state_ = state;
  1341. trace_ipc_request("PM enter Dx state", state);
  1342. ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
  1343. dx, sizeof(*dx));
  1344. if (ret < 0) {
  1345. dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
  1346. return ret;
  1347. }
  1348. dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
  1349. dx->entries_no, state);
  1350. memcpy(&hsw->dx, dx, sizeof(*dx));
  1351. return 0;
  1352. }
  1353. /* Used to save state into hsw->dx_reply */
  1354. int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
  1355. u32 *offset, u32 *size, u32 *source)
  1356. {
  1357. struct sst_hsw_ipc_dx_memory_item *dx_mem;
  1358. struct sst_hsw_ipc_dx_reply *dx_reply;
  1359. int entry_no;
  1360. dx_reply = &hsw->dx;
  1361. entry_no = dx_reply->entries_no;
  1362. trace_ipc_request("PM get Dx state", entry_no);
  1363. if (item >= entry_no)
  1364. return -EINVAL;
  1365. dx_mem = &dx_reply->mem_info[item];
  1366. *offset = dx_mem->offset;
  1367. *size = dx_mem->size;
  1368. *source = dx_mem->source;
  1369. return 0;
  1370. }
  1371. static int msg_empty_list_init(struct sst_hsw *hsw)
  1372. {
  1373. int i;
  1374. hsw->msg = kzalloc(sizeof(struct ipc_message) *
  1375. IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
  1376. if (hsw->msg == NULL)
  1377. return -ENOMEM;
  1378. for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
  1379. init_waitqueue_head(&hsw->msg[i].waitq);
  1380. list_add(&hsw->msg[i].list, &hsw->empty_list);
  1381. }
  1382. return 0;
  1383. }
  1384. void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
  1385. struct sst_module *scratch)
  1386. {
  1387. hsw->scratch = scratch;
  1388. }
  1389. struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
  1390. {
  1391. return hsw->dsp;
  1392. }
  1393. static struct sst_dsp_device hsw_dev = {
  1394. .thread = hsw_irq_thread,
  1395. .ops = &haswell_ops,
  1396. };
  1397. int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
  1398. {
  1399. struct sst_hsw_ipc_fw_version version;
  1400. struct sst_hsw *hsw;
  1401. struct sst_fw *hsw_sst_fw;
  1402. int ret;
  1403. dev_dbg(dev, "initialising Audio DSP IPC\n");
  1404. hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
  1405. if (hsw == NULL)
  1406. return -ENOMEM;
  1407. hsw->dev = dev;
  1408. INIT_LIST_HEAD(&hsw->stream_list);
  1409. INIT_LIST_HEAD(&hsw->tx_list);
  1410. INIT_LIST_HEAD(&hsw->rx_list);
  1411. INIT_LIST_HEAD(&hsw->empty_list);
  1412. init_waitqueue_head(&hsw->boot_wait);
  1413. init_waitqueue_head(&hsw->wait_txq);
  1414. ret = msg_empty_list_init(hsw);
  1415. if (ret < 0)
  1416. goto list_err;
  1417. /* start the IPC message thread */
  1418. init_kthread_worker(&hsw->kworker);
  1419. hsw->tx_thread = kthread_run(kthread_worker_fn,
  1420. &hsw->kworker,
  1421. dev_name(hsw->dev));
  1422. if (IS_ERR(hsw->tx_thread)) {
  1423. ret = PTR_ERR(hsw->tx_thread);
  1424. dev_err(hsw->dev, "error: failed to create message TX task\n");
  1425. goto list_err;
  1426. }
  1427. init_kthread_work(&hsw->kwork, ipc_tx_msgs);
  1428. hsw_dev.thread_context = hsw;
  1429. /* init SST shim */
  1430. hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
  1431. if (hsw->dsp == NULL) {
  1432. ret = -ENODEV;
  1433. goto list_err;
  1434. }
  1435. /* keep the DSP in reset state for base FW loading */
  1436. sst_dsp_reset(hsw->dsp);
  1437. hsw_sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
  1438. if (hsw_sst_fw == NULL) {
  1439. ret = -ENODEV;
  1440. dev_err(dev, "error: failed to load firmware\n");
  1441. goto fw_err;
  1442. }
  1443. /* wait for DSP boot completion */
  1444. sst_dsp_boot(hsw->dsp);
  1445. ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
  1446. msecs_to_jiffies(IPC_BOOT_MSECS));
  1447. if (ret == 0) {
  1448. ret = -EIO;
  1449. dev_err(hsw->dev, "error: ADSP boot timeout\n");
  1450. goto boot_err;
  1451. }
  1452. /* get the FW version */
  1453. sst_hsw_fw_get_version(hsw, &version);
  1454. dev_info(hsw->dev, "FW loaded: type %d - version: %d.%d build %d\n",
  1455. version.type, version.major, version.minor, version.build);
  1456. /* get the globalmixer */
  1457. ret = sst_hsw_mixer_get_info(hsw);
  1458. if (ret < 0) {
  1459. dev_err(hsw->dev, "error: failed to get stream info\n");
  1460. goto boot_err;
  1461. }
  1462. pdata->dsp = hsw;
  1463. return 0;
  1464. boot_err:
  1465. sst_dsp_reset(hsw->dsp);
  1466. sst_fw_free(hsw_sst_fw);
  1467. fw_err:
  1468. sst_dsp_free(hsw->dsp);
  1469. kfree(hsw->msg);
  1470. list_err:
  1471. return ret;
  1472. }
  1473. EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
  1474. void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
  1475. {
  1476. struct sst_hsw *hsw = pdata->dsp;
  1477. sst_dsp_reset(hsw->dsp);
  1478. sst_fw_free_all(hsw->dsp);
  1479. sst_dsp_free(hsw->dsp);
  1480. kfree(hsw->scratch);
  1481. kfree(hsw->msg);
  1482. }
  1483. EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);