dmaengine.c 31 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called COPYING.
  16. */
  17. /*
  18. * This code implements the DMA subsystem. It provides a HW-neutral interface
  19. * for other kernel code to use asynchronous memory copy capabilities,
  20. * if present, and allows different HW DMA drivers to register as providing
  21. * this capability.
  22. *
  23. * Due to the fact we are accelerating what is already a relatively fast
  24. * operation, the code goes to great lengths to avoid additional overhead,
  25. * such as locking.
  26. *
  27. * LOCKING:
  28. *
  29. * The subsystem keeps a global list of dma_device structs it is protected by a
  30. * mutex, dma_list_mutex.
  31. *
  32. * A subsystem can get access to a channel by calling dmaengine_get() followed
  33. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  34. * dma_request_channel(). Once a channel is allocated a reference is taken
  35. * against its corresponding driver to disable removal.
  36. *
  37. * Each device has a channels list, which runs unlocked but is never modified
  38. * once the device is registered, it's just setup by the driver.
  39. *
  40. * See Documentation/dmaengine.txt for more details
  41. */
  42. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  43. #include <linux/dma-mapping.h>
  44. #include <linux/init.h>
  45. #include <linux/module.h>
  46. #include <linux/mm.h>
  47. #include <linux/device.h>
  48. #include <linux/dmaengine.h>
  49. #include <linux/hardirq.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/percpu.h>
  52. #include <linux/rcupdate.h>
  53. #include <linux/mutex.h>
  54. #include <linux/jiffies.h>
  55. #include <linux/rculist.h>
  56. #include <linux/idr.h>
  57. #include <linux/slab.h>
  58. #include <linux/acpi.h>
  59. #include <linux/acpi_dma.h>
  60. #include <linux/of_dma.h>
  61. #include <linux/mempool.h>
  62. static DEFINE_MUTEX(dma_list_mutex);
  63. static DEFINE_IDR(dma_idr);
  64. static LIST_HEAD(dma_device_list);
  65. static long dmaengine_ref_count;
  66. /* --- sysfs implementation --- */
  67. /**
  68. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  69. * @dev - device node
  70. *
  71. * Must be called under dma_list_mutex
  72. */
  73. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  74. {
  75. struct dma_chan_dev *chan_dev;
  76. chan_dev = container_of(dev, typeof(*chan_dev), device);
  77. return chan_dev->chan;
  78. }
  79. static ssize_t memcpy_count_show(struct device *dev,
  80. struct device_attribute *attr, char *buf)
  81. {
  82. struct dma_chan *chan;
  83. unsigned long count = 0;
  84. int i;
  85. int err;
  86. mutex_lock(&dma_list_mutex);
  87. chan = dev_to_dma_chan(dev);
  88. if (chan) {
  89. for_each_possible_cpu(i)
  90. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  91. err = sprintf(buf, "%lu\n", count);
  92. } else
  93. err = -ENODEV;
  94. mutex_unlock(&dma_list_mutex);
  95. return err;
  96. }
  97. static DEVICE_ATTR_RO(memcpy_count);
  98. static ssize_t bytes_transferred_show(struct device *dev,
  99. struct device_attribute *attr, char *buf)
  100. {
  101. struct dma_chan *chan;
  102. unsigned long count = 0;
  103. int i;
  104. int err;
  105. mutex_lock(&dma_list_mutex);
  106. chan = dev_to_dma_chan(dev);
  107. if (chan) {
  108. for_each_possible_cpu(i)
  109. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  110. err = sprintf(buf, "%lu\n", count);
  111. } else
  112. err = -ENODEV;
  113. mutex_unlock(&dma_list_mutex);
  114. return err;
  115. }
  116. static DEVICE_ATTR_RO(bytes_transferred);
  117. static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
  118. char *buf)
  119. {
  120. struct dma_chan *chan;
  121. int err;
  122. mutex_lock(&dma_list_mutex);
  123. chan = dev_to_dma_chan(dev);
  124. if (chan)
  125. err = sprintf(buf, "%d\n", chan->client_count);
  126. else
  127. err = -ENODEV;
  128. mutex_unlock(&dma_list_mutex);
  129. return err;
  130. }
  131. static DEVICE_ATTR_RO(in_use);
  132. static struct attribute *dma_dev_attrs[] = {
  133. &dev_attr_memcpy_count.attr,
  134. &dev_attr_bytes_transferred.attr,
  135. &dev_attr_in_use.attr,
  136. NULL,
  137. };
  138. ATTRIBUTE_GROUPS(dma_dev);
  139. static void chan_dev_release(struct device *dev)
  140. {
  141. struct dma_chan_dev *chan_dev;
  142. chan_dev = container_of(dev, typeof(*chan_dev), device);
  143. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  144. mutex_lock(&dma_list_mutex);
  145. idr_remove(&dma_idr, chan_dev->dev_id);
  146. mutex_unlock(&dma_list_mutex);
  147. kfree(chan_dev->idr_ref);
  148. }
  149. kfree(chan_dev);
  150. }
  151. static struct class dma_devclass = {
  152. .name = "dma",
  153. .dev_groups = dma_dev_groups,
  154. .dev_release = chan_dev_release,
  155. };
  156. /* --- client and device registration --- */
  157. #define dma_device_satisfies_mask(device, mask) \
  158. __dma_device_satisfies_mask((device), &(mask))
  159. static int
  160. __dma_device_satisfies_mask(struct dma_device *device,
  161. const dma_cap_mask_t *want)
  162. {
  163. dma_cap_mask_t has;
  164. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  165. DMA_TX_TYPE_END);
  166. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  167. }
  168. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  169. {
  170. return chan->device->dev->driver->owner;
  171. }
  172. /**
  173. * balance_ref_count - catch up the channel reference count
  174. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  175. *
  176. * balance_ref_count must be called under dma_list_mutex
  177. */
  178. static void balance_ref_count(struct dma_chan *chan)
  179. {
  180. struct module *owner = dma_chan_to_owner(chan);
  181. while (chan->client_count < dmaengine_ref_count) {
  182. __module_get(owner);
  183. chan->client_count++;
  184. }
  185. }
  186. /**
  187. * dma_chan_get - try to grab a dma channel's parent driver module
  188. * @chan - channel to grab
  189. *
  190. * Must be called under dma_list_mutex
  191. */
  192. static int dma_chan_get(struct dma_chan *chan)
  193. {
  194. struct module *owner = dma_chan_to_owner(chan);
  195. int ret;
  196. /* The channel is already in use, update client count */
  197. if (chan->client_count) {
  198. __module_get(owner);
  199. goto out;
  200. }
  201. if (!try_module_get(owner))
  202. return -ENODEV;
  203. /* allocate upon first client reference */
  204. if (chan->device->device_alloc_chan_resources) {
  205. ret = chan->device->device_alloc_chan_resources(chan);
  206. if (ret < 0)
  207. goto err_out;
  208. }
  209. if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  210. balance_ref_count(chan);
  211. out:
  212. chan->client_count++;
  213. return 0;
  214. err_out:
  215. module_put(owner);
  216. return ret;
  217. }
  218. /**
  219. * dma_chan_put - drop a reference to a dma channel's parent driver module
  220. * @chan - channel to release
  221. *
  222. * Must be called under dma_list_mutex
  223. */
  224. static void dma_chan_put(struct dma_chan *chan)
  225. {
  226. /* This channel is not in use, bail out */
  227. if (!chan->client_count)
  228. return;
  229. chan->client_count--;
  230. module_put(dma_chan_to_owner(chan));
  231. /* This channel is not in use anymore, free it */
  232. if (!chan->client_count && chan->device->device_free_chan_resources)
  233. chan->device->device_free_chan_resources(chan);
  234. /* If the channel is used via a DMA request router, free the mapping */
  235. if (chan->router && chan->router->route_free) {
  236. chan->router->route_free(chan->router->dev, chan->route_data);
  237. chan->router = NULL;
  238. chan->route_data = NULL;
  239. }
  240. }
  241. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  242. {
  243. enum dma_status status;
  244. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  245. dma_async_issue_pending(chan);
  246. do {
  247. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  248. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  249. pr_err("%s: timeout!\n", __func__);
  250. return DMA_ERROR;
  251. }
  252. if (status != DMA_IN_PROGRESS)
  253. break;
  254. cpu_relax();
  255. } while (1);
  256. return status;
  257. }
  258. EXPORT_SYMBOL(dma_sync_wait);
  259. /**
  260. * dma_cap_mask_all - enable iteration over all operation types
  261. */
  262. static dma_cap_mask_t dma_cap_mask_all;
  263. /**
  264. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  265. * @chan - associated channel for this entry
  266. */
  267. struct dma_chan_tbl_ent {
  268. struct dma_chan *chan;
  269. };
  270. /**
  271. * channel_table - percpu lookup table for memory-to-memory offload providers
  272. */
  273. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  274. static int __init dma_channel_table_init(void)
  275. {
  276. enum dma_transaction_type cap;
  277. int err = 0;
  278. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  279. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  280. * but are not associated with an operation so they do not need
  281. * an entry in the channel_table
  282. */
  283. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  284. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  285. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  286. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  287. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  288. if (!channel_table[cap]) {
  289. err = -ENOMEM;
  290. break;
  291. }
  292. }
  293. if (err) {
  294. pr_err("initialization failure\n");
  295. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  296. free_percpu(channel_table[cap]);
  297. }
  298. return err;
  299. }
  300. arch_initcall(dma_channel_table_init);
  301. /**
  302. * dma_find_channel - find a channel to carry out the operation
  303. * @tx_type: transaction type
  304. */
  305. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  306. {
  307. return this_cpu_read(channel_table[tx_type]->chan);
  308. }
  309. EXPORT_SYMBOL(dma_find_channel);
  310. /**
  311. * dma_issue_pending_all - flush all pending operations across all channels
  312. */
  313. void dma_issue_pending_all(void)
  314. {
  315. struct dma_device *device;
  316. struct dma_chan *chan;
  317. rcu_read_lock();
  318. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  319. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  320. continue;
  321. list_for_each_entry(chan, &device->channels, device_node)
  322. if (chan->client_count)
  323. device->device_issue_pending(chan);
  324. }
  325. rcu_read_unlock();
  326. }
  327. EXPORT_SYMBOL(dma_issue_pending_all);
  328. /**
  329. * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
  330. */
  331. static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
  332. {
  333. int node = dev_to_node(chan->device->dev);
  334. return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
  335. }
  336. /**
  337. * min_chan - returns the channel with min count and in the same numa-node as the cpu
  338. * @cap: capability to match
  339. * @cpu: cpu index which the channel should be close to
  340. *
  341. * If some channels are close to the given cpu, the one with the lowest
  342. * reference count is returned. Otherwise, cpu is ignored and only the
  343. * reference count is taken into account.
  344. * Must be called under dma_list_mutex.
  345. */
  346. static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
  347. {
  348. struct dma_device *device;
  349. struct dma_chan *chan;
  350. struct dma_chan *min = NULL;
  351. struct dma_chan *localmin = NULL;
  352. list_for_each_entry(device, &dma_device_list, global_node) {
  353. if (!dma_has_cap(cap, device->cap_mask) ||
  354. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  355. continue;
  356. list_for_each_entry(chan, &device->channels, device_node) {
  357. if (!chan->client_count)
  358. continue;
  359. if (!min || chan->table_count < min->table_count)
  360. min = chan;
  361. if (dma_chan_is_local(chan, cpu))
  362. if (!localmin ||
  363. chan->table_count < localmin->table_count)
  364. localmin = chan;
  365. }
  366. }
  367. chan = localmin ? localmin : min;
  368. if (chan)
  369. chan->table_count++;
  370. return chan;
  371. }
  372. /**
  373. * dma_channel_rebalance - redistribute the available channels
  374. *
  375. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  376. * operation type) in the SMP case, and operation isolation (avoid
  377. * multi-tasking channels) in the non-SMP case. Must be called under
  378. * dma_list_mutex.
  379. */
  380. static void dma_channel_rebalance(void)
  381. {
  382. struct dma_chan *chan;
  383. struct dma_device *device;
  384. int cpu;
  385. int cap;
  386. /* undo the last distribution */
  387. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  388. for_each_possible_cpu(cpu)
  389. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  390. list_for_each_entry(device, &dma_device_list, global_node) {
  391. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  392. continue;
  393. list_for_each_entry(chan, &device->channels, device_node)
  394. chan->table_count = 0;
  395. }
  396. /* don't populate the channel_table if no clients are available */
  397. if (!dmaengine_ref_count)
  398. return;
  399. /* redistribute available channels */
  400. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  401. for_each_online_cpu(cpu) {
  402. chan = min_chan(cap, cpu);
  403. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  404. }
  405. }
  406. int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
  407. {
  408. struct dma_device *device;
  409. if (!chan || !caps)
  410. return -EINVAL;
  411. device = chan->device;
  412. /* check if the channel supports slave transactions */
  413. if (!test_bit(DMA_SLAVE, device->cap_mask.bits))
  414. return -ENXIO;
  415. /*
  416. * Check whether it reports it uses the generic slave
  417. * capabilities, if not, that means it doesn't support any
  418. * kind of slave capabilities reporting.
  419. */
  420. if (!device->directions)
  421. return -ENXIO;
  422. caps->src_addr_widths = device->src_addr_widths;
  423. caps->dst_addr_widths = device->dst_addr_widths;
  424. caps->directions = device->directions;
  425. caps->residue_granularity = device->residue_granularity;
  426. caps->descriptor_reuse = device->descriptor_reuse;
  427. /*
  428. * Some devices implement only pause (e.g. to get residuum) but no
  429. * resume. However cmd_pause is advertised as pause AND resume.
  430. */
  431. caps->cmd_pause = !!(device->device_pause && device->device_resume);
  432. caps->cmd_terminate = !!device->device_terminate_all;
  433. return 0;
  434. }
  435. EXPORT_SYMBOL_GPL(dma_get_slave_caps);
  436. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  437. struct dma_device *dev,
  438. dma_filter_fn fn, void *fn_param)
  439. {
  440. struct dma_chan *chan;
  441. if (!__dma_device_satisfies_mask(dev, mask)) {
  442. pr_debug("%s: wrong capabilities\n", __func__);
  443. return NULL;
  444. }
  445. /* devices with multiple channels need special handling as we need to
  446. * ensure that all channels are either private or public.
  447. */
  448. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  449. list_for_each_entry(chan, &dev->channels, device_node) {
  450. /* some channels are already publicly allocated */
  451. if (chan->client_count)
  452. return NULL;
  453. }
  454. list_for_each_entry(chan, &dev->channels, device_node) {
  455. if (chan->client_count) {
  456. pr_debug("%s: %s busy\n",
  457. __func__, dma_chan_name(chan));
  458. continue;
  459. }
  460. if (fn && !fn(chan, fn_param)) {
  461. pr_debug("%s: %s filter said false\n",
  462. __func__, dma_chan_name(chan));
  463. continue;
  464. }
  465. return chan;
  466. }
  467. return NULL;
  468. }
  469. /**
  470. * dma_get_slave_channel - try to get specific channel exclusively
  471. * @chan: target channel
  472. */
  473. struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
  474. {
  475. int err = -EBUSY;
  476. /* lock against __dma_request_channel */
  477. mutex_lock(&dma_list_mutex);
  478. if (chan->client_count == 0) {
  479. struct dma_device *device = chan->device;
  480. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  481. device->privatecnt++;
  482. err = dma_chan_get(chan);
  483. if (err) {
  484. pr_debug("%s: failed to get %s: (%d)\n",
  485. __func__, dma_chan_name(chan), err);
  486. chan = NULL;
  487. if (--device->privatecnt == 0)
  488. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  489. }
  490. } else
  491. chan = NULL;
  492. mutex_unlock(&dma_list_mutex);
  493. return chan;
  494. }
  495. EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  496. struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
  497. {
  498. dma_cap_mask_t mask;
  499. struct dma_chan *chan;
  500. int err;
  501. dma_cap_zero(mask);
  502. dma_cap_set(DMA_SLAVE, mask);
  503. /* lock against __dma_request_channel */
  504. mutex_lock(&dma_list_mutex);
  505. chan = private_candidate(&mask, device, NULL, NULL);
  506. if (chan) {
  507. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  508. device->privatecnt++;
  509. err = dma_chan_get(chan);
  510. if (err) {
  511. pr_debug("%s: failed to get %s: (%d)\n",
  512. __func__, dma_chan_name(chan), err);
  513. chan = NULL;
  514. if (--device->privatecnt == 0)
  515. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  516. }
  517. }
  518. mutex_unlock(&dma_list_mutex);
  519. return chan;
  520. }
  521. EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
  522. /**
  523. * __dma_request_channel - try to allocate an exclusive channel
  524. * @mask: capabilities that the channel must satisfy
  525. * @fn: optional callback to disposition available channels
  526. * @fn_param: opaque parameter to pass to dma_filter_fn
  527. *
  528. * Returns pointer to appropriate DMA channel on success or NULL.
  529. */
  530. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  531. dma_filter_fn fn, void *fn_param)
  532. {
  533. struct dma_device *device, *_d;
  534. struct dma_chan *chan = NULL;
  535. int err;
  536. /* Find a channel */
  537. mutex_lock(&dma_list_mutex);
  538. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  539. chan = private_candidate(mask, device, fn, fn_param);
  540. if (chan) {
  541. /* Found a suitable channel, try to grab, prep, and
  542. * return it. We first set DMA_PRIVATE to disable
  543. * balance_ref_count as this channel will not be
  544. * published in the general-purpose allocator
  545. */
  546. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  547. device->privatecnt++;
  548. err = dma_chan_get(chan);
  549. if (err == -ENODEV) {
  550. pr_debug("%s: %s module removed\n",
  551. __func__, dma_chan_name(chan));
  552. list_del_rcu(&device->global_node);
  553. } else if (err)
  554. pr_debug("%s: failed to get %s: (%d)\n",
  555. __func__, dma_chan_name(chan), err);
  556. else
  557. break;
  558. if (--device->privatecnt == 0)
  559. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  560. chan = NULL;
  561. }
  562. }
  563. mutex_unlock(&dma_list_mutex);
  564. pr_debug("%s: %s (%s)\n",
  565. __func__,
  566. chan ? "success" : "fail",
  567. chan ? dma_chan_name(chan) : NULL);
  568. return chan;
  569. }
  570. EXPORT_SYMBOL_GPL(__dma_request_channel);
  571. /**
  572. * dma_request_slave_channel_reason - try to allocate an exclusive slave channel
  573. * @dev: pointer to client device structure
  574. * @name: slave channel name
  575. *
  576. * Returns pointer to appropriate DMA channel on success or an error pointer.
  577. */
  578. struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
  579. const char *name)
  580. {
  581. /* If device-tree is present get slave info from here */
  582. if (dev->of_node)
  583. return of_dma_request_slave_channel(dev->of_node, name);
  584. /* If device was enumerated by ACPI get slave info from here */
  585. if (ACPI_HANDLE(dev))
  586. return acpi_dma_request_slave_chan_by_name(dev, name);
  587. return ERR_PTR(-ENODEV);
  588. }
  589. EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
  590. /**
  591. * dma_request_slave_channel - try to allocate an exclusive slave channel
  592. * @dev: pointer to client device structure
  593. * @name: slave channel name
  594. *
  595. * Returns pointer to appropriate DMA channel on success or NULL.
  596. */
  597. struct dma_chan *dma_request_slave_channel(struct device *dev,
  598. const char *name)
  599. {
  600. struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
  601. if (IS_ERR(ch))
  602. return NULL;
  603. dma_cap_set(DMA_PRIVATE, ch->device->cap_mask);
  604. ch->device->privatecnt++;
  605. return ch;
  606. }
  607. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  608. void dma_release_channel(struct dma_chan *chan)
  609. {
  610. mutex_lock(&dma_list_mutex);
  611. WARN_ONCE(chan->client_count != 1,
  612. "chan reference count %d != 1\n", chan->client_count);
  613. dma_chan_put(chan);
  614. /* drop PRIVATE cap enabled by __dma_request_channel() */
  615. if (--chan->device->privatecnt == 0)
  616. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  617. mutex_unlock(&dma_list_mutex);
  618. }
  619. EXPORT_SYMBOL_GPL(dma_release_channel);
  620. /**
  621. * dmaengine_get - register interest in dma_channels
  622. */
  623. void dmaengine_get(void)
  624. {
  625. struct dma_device *device, *_d;
  626. struct dma_chan *chan;
  627. int err;
  628. mutex_lock(&dma_list_mutex);
  629. dmaengine_ref_count++;
  630. /* try to grab channels */
  631. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  632. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  633. continue;
  634. list_for_each_entry(chan, &device->channels, device_node) {
  635. err = dma_chan_get(chan);
  636. if (err == -ENODEV) {
  637. /* module removed before we could use it */
  638. list_del_rcu(&device->global_node);
  639. break;
  640. } else if (err)
  641. pr_debug("%s: failed to get %s: (%d)\n",
  642. __func__, dma_chan_name(chan), err);
  643. }
  644. }
  645. /* if this is the first reference and there were channels
  646. * waiting we need to rebalance to get those channels
  647. * incorporated into the channel table
  648. */
  649. if (dmaengine_ref_count == 1)
  650. dma_channel_rebalance();
  651. mutex_unlock(&dma_list_mutex);
  652. }
  653. EXPORT_SYMBOL(dmaengine_get);
  654. /**
  655. * dmaengine_put - let dma drivers be removed when ref_count == 0
  656. */
  657. void dmaengine_put(void)
  658. {
  659. struct dma_device *device;
  660. struct dma_chan *chan;
  661. mutex_lock(&dma_list_mutex);
  662. dmaengine_ref_count--;
  663. BUG_ON(dmaengine_ref_count < 0);
  664. /* drop channel references */
  665. list_for_each_entry(device, &dma_device_list, global_node) {
  666. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  667. continue;
  668. list_for_each_entry(chan, &device->channels, device_node)
  669. dma_chan_put(chan);
  670. }
  671. mutex_unlock(&dma_list_mutex);
  672. }
  673. EXPORT_SYMBOL(dmaengine_put);
  674. static bool device_has_all_tx_types(struct dma_device *device)
  675. {
  676. /* A device that satisfies this test has channels that will never cause
  677. * an async_tx channel switch event as all possible operation types can
  678. * be handled.
  679. */
  680. #ifdef CONFIG_ASYNC_TX_DMA
  681. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  682. return false;
  683. #endif
  684. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  685. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  686. return false;
  687. #endif
  688. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  689. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  690. return false;
  691. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  692. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  693. return false;
  694. #endif
  695. #endif
  696. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  697. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  698. return false;
  699. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  700. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  701. return false;
  702. #endif
  703. #endif
  704. return true;
  705. }
  706. static int get_dma_id(struct dma_device *device)
  707. {
  708. int rc;
  709. mutex_lock(&dma_list_mutex);
  710. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  711. if (rc >= 0)
  712. device->dev_id = rc;
  713. mutex_unlock(&dma_list_mutex);
  714. return rc < 0 ? rc : 0;
  715. }
  716. /**
  717. * dma_async_device_register - registers DMA devices found
  718. * @device: &dma_device
  719. */
  720. int dma_async_device_register(struct dma_device *device)
  721. {
  722. int chancnt = 0, rc;
  723. struct dma_chan* chan;
  724. atomic_t *idr_ref;
  725. if (!device)
  726. return -ENODEV;
  727. /* validate device routines */
  728. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  729. !device->device_prep_dma_memcpy);
  730. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  731. !device->device_prep_dma_xor);
  732. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  733. !device->device_prep_dma_xor_val);
  734. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  735. !device->device_prep_dma_pq);
  736. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  737. !device->device_prep_dma_pq_val);
  738. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  739. !device->device_prep_dma_memset);
  740. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  741. !device->device_prep_dma_interrupt);
  742. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  743. !device->device_prep_dma_sg);
  744. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  745. !device->device_prep_dma_cyclic);
  746. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  747. !device->device_prep_interleaved_dma);
  748. BUG_ON(!device->device_tx_status);
  749. BUG_ON(!device->device_issue_pending);
  750. BUG_ON(!device->dev);
  751. /* note: this only matters in the
  752. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  753. */
  754. if (device_has_all_tx_types(device))
  755. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  756. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  757. if (!idr_ref)
  758. return -ENOMEM;
  759. rc = get_dma_id(device);
  760. if (rc != 0) {
  761. kfree(idr_ref);
  762. return rc;
  763. }
  764. atomic_set(idr_ref, 0);
  765. /* represent channels in sysfs. Probably want devs too */
  766. list_for_each_entry(chan, &device->channels, device_node) {
  767. rc = -ENOMEM;
  768. chan->local = alloc_percpu(typeof(*chan->local));
  769. if (chan->local == NULL)
  770. goto err_out;
  771. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  772. if (chan->dev == NULL) {
  773. free_percpu(chan->local);
  774. chan->local = NULL;
  775. goto err_out;
  776. }
  777. chan->chan_id = chancnt++;
  778. chan->dev->device.class = &dma_devclass;
  779. chan->dev->device.parent = device->dev;
  780. chan->dev->chan = chan;
  781. chan->dev->idr_ref = idr_ref;
  782. chan->dev->dev_id = device->dev_id;
  783. atomic_inc(idr_ref);
  784. dev_set_name(&chan->dev->device, "dma%dchan%d",
  785. device->dev_id, chan->chan_id);
  786. rc = device_register(&chan->dev->device);
  787. if (rc) {
  788. free_percpu(chan->local);
  789. chan->local = NULL;
  790. kfree(chan->dev);
  791. atomic_dec(idr_ref);
  792. goto err_out;
  793. }
  794. chan->client_count = 0;
  795. }
  796. device->chancnt = chancnt;
  797. mutex_lock(&dma_list_mutex);
  798. /* take references on public channels */
  799. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  800. list_for_each_entry(chan, &device->channels, device_node) {
  801. /* if clients are already waiting for channels we need
  802. * to take references on their behalf
  803. */
  804. if (dma_chan_get(chan) == -ENODEV) {
  805. /* note we can only get here for the first
  806. * channel as the remaining channels are
  807. * guaranteed to get a reference
  808. */
  809. rc = -ENODEV;
  810. mutex_unlock(&dma_list_mutex);
  811. goto err_out;
  812. }
  813. }
  814. list_add_tail_rcu(&device->global_node, &dma_device_list);
  815. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  816. device->privatecnt++; /* Always private */
  817. dma_channel_rebalance();
  818. mutex_unlock(&dma_list_mutex);
  819. return 0;
  820. err_out:
  821. /* if we never registered a channel just release the idr */
  822. if (atomic_read(idr_ref) == 0) {
  823. mutex_lock(&dma_list_mutex);
  824. idr_remove(&dma_idr, device->dev_id);
  825. mutex_unlock(&dma_list_mutex);
  826. kfree(idr_ref);
  827. return rc;
  828. }
  829. list_for_each_entry(chan, &device->channels, device_node) {
  830. if (chan->local == NULL)
  831. continue;
  832. mutex_lock(&dma_list_mutex);
  833. chan->dev->chan = NULL;
  834. mutex_unlock(&dma_list_mutex);
  835. device_unregister(&chan->dev->device);
  836. free_percpu(chan->local);
  837. }
  838. return rc;
  839. }
  840. EXPORT_SYMBOL(dma_async_device_register);
  841. /**
  842. * dma_async_device_unregister - unregister a DMA device
  843. * @device: &dma_device
  844. *
  845. * This routine is called by dma driver exit routines, dmaengine holds module
  846. * references to prevent it being called while channels are in use.
  847. */
  848. void dma_async_device_unregister(struct dma_device *device)
  849. {
  850. struct dma_chan *chan;
  851. mutex_lock(&dma_list_mutex);
  852. list_del_rcu(&device->global_node);
  853. dma_channel_rebalance();
  854. mutex_unlock(&dma_list_mutex);
  855. list_for_each_entry(chan, &device->channels, device_node) {
  856. WARN_ONCE(chan->client_count,
  857. "%s called while %d clients hold a reference\n",
  858. __func__, chan->client_count);
  859. mutex_lock(&dma_list_mutex);
  860. chan->dev->chan = NULL;
  861. mutex_unlock(&dma_list_mutex);
  862. device_unregister(&chan->dev->device);
  863. free_percpu(chan->local);
  864. }
  865. }
  866. EXPORT_SYMBOL(dma_async_device_unregister);
  867. struct dmaengine_unmap_pool {
  868. struct kmem_cache *cache;
  869. const char *name;
  870. mempool_t *pool;
  871. size_t size;
  872. };
  873. #define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
  874. static struct dmaengine_unmap_pool unmap_pool[] = {
  875. __UNMAP_POOL(2),
  876. #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
  877. __UNMAP_POOL(16),
  878. __UNMAP_POOL(128),
  879. __UNMAP_POOL(256),
  880. #endif
  881. };
  882. static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
  883. {
  884. int order = get_count_order(nr);
  885. switch (order) {
  886. case 0 ... 1:
  887. return &unmap_pool[0];
  888. case 2 ... 4:
  889. return &unmap_pool[1];
  890. case 5 ... 7:
  891. return &unmap_pool[2];
  892. case 8:
  893. return &unmap_pool[3];
  894. default:
  895. BUG();
  896. return NULL;
  897. }
  898. }
  899. static void dmaengine_unmap(struct kref *kref)
  900. {
  901. struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
  902. struct device *dev = unmap->dev;
  903. int cnt, i;
  904. cnt = unmap->to_cnt;
  905. for (i = 0; i < cnt; i++)
  906. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  907. DMA_TO_DEVICE);
  908. cnt += unmap->from_cnt;
  909. for (; i < cnt; i++)
  910. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  911. DMA_FROM_DEVICE);
  912. cnt += unmap->bidi_cnt;
  913. for (; i < cnt; i++) {
  914. if (unmap->addr[i] == 0)
  915. continue;
  916. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  917. DMA_BIDIRECTIONAL);
  918. }
  919. cnt = unmap->map_cnt;
  920. mempool_free(unmap, __get_unmap_pool(cnt)->pool);
  921. }
  922. void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
  923. {
  924. if (unmap)
  925. kref_put(&unmap->kref, dmaengine_unmap);
  926. }
  927. EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
  928. static void dmaengine_destroy_unmap_pool(void)
  929. {
  930. int i;
  931. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  932. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  933. mempool_destroy(p->pool);
  934. p->pool = NULL;
  935. kmem_cache_destroy(p->cache);
  936. p->cache = NULL;
  937. }
  938. }
  939. static int __init dmaengine_init_unmap_pool(void)
  940. {
  941. int i;
  942. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  943. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  944. size_t size;
  945. size = sizeof(struct dmaengine_unmap_data) +
  946. sizeof(dma_addr_t) * p->size;
  947. p->cache = kmem_cache_create(p->name, size, 0,
  948. SLAB_HWCACHE_ALIGN, NULL);
  949. if (!p->cache)
  950. break;
  951. p->pool = mempool_create_slab_pool(1, p->cache);
  952. if (!p->pool)
  953. break;
  954. }
  955. if (i == ARRAY_SIZE(unmap_pool))
  956. return 0;
  957. dmaengine_destroy_unmap_pool();
  958. return -ENOMEM;
  959. }
  960. struct dmaengine_unmap_data *
  961. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
  962. {
  963. struct dmaengine_unmap_data *unmap;
  964. unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
  965. if (!unmap)
  966. return NULL;
  967. memset(unmap, 0, sizeof(*unmap));
  968. kref_init(&unmap->kref);
  969. unmap->dev = dev;
  970. unmap->map_cnt = nr;
  971. return unmap;
  972. }
  973. EXPORT_SYMBOL(dmaengine_get_unmap_data);
  974. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  975. struct dma_chan *chan)
  976. {
  977. tx->chan = chan;
  978. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  979. spin_lock_init(&tx->lock);
  980. #endif
  981. }
  982. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  983. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  984. * @tx: in-flight transaction to wait on
  985. */
  986. enum dma_status
  987. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  988. {
  989. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  990. if (!tx)
  991. return DMA_COMPLETE;
  992. while (tx->cookie == -EBUSY) {
  993. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  994. pr_err("%s timeout waiting for descriptor submission\n",
  995. __func__);
  996. return DMA_ERROR;
  997. }
  998. cpu_relax();
  999. }
  1000. return dma_sync_wait(tx->chan, tx->cookie);
  1001. }
  1002. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  1003. /* dma_run_dependencies - helper routine for dma drivers to process
  1004. * (start) dependent operations on their target channel
  1005. * @tx: transaction with dependencies
  1006. */
  1007. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  1008. {
  1009. struct dma_async_tx_descriptor *dep = txd_next(tx);
  1010. struct dma_async_tx_descriptor *dep_next;
  1011. struct dma_chan *chan;
  1012. if (!dep)
  1013. return;
  1014. /* we'll submit tx->next now, so clear the link */
  1015. txd_clear_next(tx);
  1016. chan = dep->chan;
  1017. /* keep submitting up until a channel switch is detected
  1018. * in that case we will be called again as a result of
  1019. * processing the interrupt from async_tx_channel_switch
  1020. */
  1021. for (; dep; dep = dep_next) {
  1022. txd_lock(dep);
  1023. txd_clear_parent(dep);
  1024. dep_next = txd_next(dep);
  1025. if (dep_next && dep_next->chan == chan)
  1026. txd_clear_next(dep); /* ->next will be submitted */
  1027. else
  1028. dep_next = NULL; /* submit current dep and terminate */
  1029. txd_unlock(dep);
  1030. dep->tx_submit(dep);
  1031. }
  1032. chan->device->device_issue_pending(chan);
  1033. }
  1034. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  1035. static int __init dma_bus_init(void)
  1036. {
  1037. int err = dmaengine_init_unmap_pool();
  1038. if (err)
  1039. return err;
  1040. return class_register(&dma_devclass);
  1041. }
  1042. arch_initcall(dma_bus_init);