coda-bit.c 56 KB

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  1. /*
  2. * Coda multi-standard codec IP - BIT processor functions
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/kernel.h>
  17. #include <linux/log2.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <linux/videodev2.h>
  22. #include <media/v4l2-common.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-fh.h>
  25. #include <media/v4l2-mem2mem.h>
  26. #include <media/videobuf2-core.h>
  27. #include <media/videobuf2-dma-contig.h>
  28. #include <media/videobuf2-vmalloc.h>
  29. #include "coda.h"
  30. #define CODA_PARA_BUF_SIZE (10 * 1024)
  31. #define CODA7_PS_BUF_SIZE 0x28000
  32. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  33. #define CODA_DEFAULT_GAMMA 4096
  34. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  35. static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
  36. static inline int coda_is_initialized(struct coda_dev *dev)
  37. {
  38. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  39. }
  40. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  41. {
  42. return coda_read(dev, CODA_REG_BIT_BUSY);
  43. }
  44. static int coda_wait_timeout(struct coda_dev *dev)
  45. {
  46. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  47. while (coda_isbusy(dev)) {
  48. if (time_after(jiffies, timeout))
  49. return -ETIMEDOUT;
  50. }
  51. return 0;
  52. }
  53. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  54. {
  55. struct coda_dev *dev = ctx->dev;
  56. if (dev->devtype->product == CODA_960 ||
  57. dev->devtype->product == CODA_7541) {
  58. /* Restore context related registers to CODA */
  59. coda_write(dev, ctx->bit_stream_param,
  60. CODA_REG_BIT_BIT_STREAM_PARAM);
  61. coda_write(dev, ctx->frm_dis_flg,
  62. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  63. coda_write(dev, ctx->frame_mem_ctrl,
  64. CODA_REG_BIT_FRAME_MEM_CTRL);
  65. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  66. }
  67. if (dev->devtype->product == CODA_960) {
  68. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  69. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  70. }
  71. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  72. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  73. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  74. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  75. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  76. }
  77. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  78. {
  79. struct coda_dev *dev = ctx->dev;
  80. coda_command_async(ctx, cmd);
  81. return coda_wait_timeout(dev);
  82. }
  83. int coda_hw_reset(struct coda_ctx *ctx)
  84. {
  85. struct coda_dev *dev = ctx->dev;
  86. unsigned long timeout;
  87. unsigned int idx;
  88. int ret;
  89. if (!dev->rstc)
  90. return -ENOENT;
  91. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  92. if (dev->devtype->product == CODA_960) {
  93. timeout = jiffies + msecs_to_jiffies(100);
  94. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  95. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  96. if (time_after(jiffies, timeout))
  97. return -ETIME;
  98. cpu_relax();
  99. }
  100. }
  101. ret = reset_control_reset(dev->rstc);
  102. if (ret < 0)
  103. return ret;
  104. if (dev->devtype->product == CODA_960)
  105. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  106. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  107. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  108. ret = coda_wait_timeout(dev);
  109. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  110. return ret;
  111. }
  112. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  113. {
  114. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  115. struct coda_dev *dev = ctx->dev;
  116. u32 rd_ptr;
  117. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  118. kfifo->out = (kfifo->in & ~kfifo->mask) |
  119. (rd_ptr - ctx->bitstream.paddr);
  120. if (kfifo->out > kfifo->in)
  121. kfifo->out -= kfifo->mask + 1;
  122. }
  123. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  124. {
  125. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  126. struct coda_dev *dev = ctx->dev;
  127. u32 rd_ptr, wr_ptr;
  128. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  129. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  130. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  131. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  132. }
  133. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  134. {
  135. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  136. struct coda_dev *dev = ctx->dev;
  137. u32 wr_ptr;
  138. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  139. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  140. }
  141. static int coda_bitstream_queue(struct coda_ctx *ctx,
  142. struct vb2_buffer *src_buf)
  143. {
  144. u32 src_size = vb2_get_plane_payload(src_buf, 0);
  145. u32 n;
  146. n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
  147. src_size);
  148. if (n < src_size)
  149. return -ENOSPC;
  150. dma_sync_single_for_device(&ctx->dev->plat_dev->dev,
  151. ctx->bitstream.paddr, ctx->bitstream.size,
  152. DMA_TO_DEVICE);
  153. src_buf->v4l2_buf.sequence = ctx->qsequence++;
  154. return 0;
  155. }
  156. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  157. struct vb2_buffer *src_buf)
  158. {
  159. int ret;
  160. if (coda_get_bitstream_payload(ctx) +
  161. vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
  162. return false;
  163. if (vb2_plane_vaddr(src_buf, 0) == NULL) {
  164. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  165. return true;
  166. }
  167. ret = coda_bitstream_queue(ctx, src_buf);
  168. if (ret < 0) {
  169. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  170. return false;
  171. }
  172. /* Sync read pointer to device */
  173. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  174. coda_kfifo_sync_to_device_write(ctx);
  175. ctx->hold = false;
  176. return true;
  177. }
  178. void coda_fill_bitstream(struct coda_ctx *ctx, bool streaming)
  179. {
  180. struct vb2_buffer *src_buf;
  181. struct coda_buffer_meta *meta;
  182. u32 start;
  183. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  184. /*
  185. * Only queue a single JPEG into the bitstream buffer, except
  186. * to increase payload over 512 bytes or if in hold state.
  187. */
  188. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  189. (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
  190. break;
  191. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  192. /* Drop frames that do not start/end with a SOI/EOI markers */
  193. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  194. !coda_jpeg_check_buffer(ctx, src_buf)) {
  195. v4l2_err(&ctx->dev->v4l2_dev,
  196. "dropping invalid JPEG frame %d\n",
  197. ctx->qsequence);
  198. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  199. v4l2_m2m_buf_done(src_buf, streaming ?
  200. VB2_BUF_STATE_ERROR :
  201. VB2_BUF_STATE_QUEUED);
  202. continue;
  203. }
  204. /* Buffer start position */
  205. start = ctx->bitstream_fifo.kfifo.in &
  206. ctx->bitstream_fifo.kfifo.mask;
  207. if (coda_bitstream_try_queue(ctx, src_buf)) {
  208. /*
  209. * Source buffer is queued in the bitstream ringbuffer;
  210. * queue the timestamp and mark source buffer as done
  211. */
  212. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  213. meta = kmalloc(sizeof(*meta), GFP_KERNEL);
  214. if (meta) {
  215. meta->sequence = src_buf->v4l2_buf.sequence;
  216. meta->timecode = src_buf->v4l2_buf.timecode;
  217. meta->timestamp = src_buf->v4l2_buf.timestamp;
  218. meta->start = start;
  219. meta->end = ctx->bitstream_fifo.kfifo.in &
  220. ctx->bitstream_fifo.kfifo.mask;
  221. list_add_tail(&meta->list,
  222. &ctx->buffer_meta_list);
  223. }
  224. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  225. } else {
  226. break;
  227. }
  228. }
  229. }
  230. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  231. {
  232. struct coda_dev *dev = ctx->dev;
  233. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  234. /* If this context is currently running, update the hardware flag */
  235. if ((dev->devtype->product == CODA_960) &&
  236. coda_isbusy(dev) &&
  237. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  238. coda_write(dev, ctx->bit_stream_param,
  239. CODA_REG_BIT_BIT_STREAM_PARAM);
  240. }
  241. }
  242. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  243. {
  244. struct coda_dev *dev = ctx->dev;
  245. u32 *p = ctx->parabuf.vaddr;
  246. if (dev->devtype->product == CODA_DX6)
  247. p[index] = value;
  248. else
  249. p[index ^ 1] = value;
  250. }
  251. static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
  252. struct coda_aux_buf *buf, size_t size,
  253. const char *name)
  254. {
  255. return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
  256. }
  257. static void coda_free_framebuffers(struct coda_ctx *ctx)
  258. {
  259. int i;
  260. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  261. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  262. }
  263. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  264. struct coda_q_data *q_data, u32 fourcc)
  265. {
  266. struct coda_dev *dev = ctx->dev;
  267. int width, height;
  268. dma_addr_t paddr;
  269. int ysize;
  270. int ret;
  271. int i;
  272. if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  273. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
  274. width = round_up(q_data->width, 16);
  275. height = round_up(q_data->height, 16);
  276. } else {
  277. width = round_up(q_data->width, 8);
  278. height = q_data->height;
  279. }
  280. ysize = width * height;
  281. /* Allocate frame buffers */
  282. for (i = 0; i < ctx->num_internal_frames; i++) {
  283. size_t size;
  284. char *name;
  285. size = ysize + ysize / 2;
  286. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  287. dev->devtype->product != CODA_DX6)
  288. size += ysize / 4;
  289. name = kasprintf(GFP_KERNEL, "fb%d", i);
  290. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
  291. size, name);
  292. kfree(name);
  293. if (ret < 0) {
  294. coda_free_framebuffers(ctx);
  295. return ret;
  296. }
  297. }
  298. /* Register frame buffers in the parameter buffer */
  299. for (i = 0; i < ctx->num_internal_frames; i++) {
  300. paddr = ctx->internal_frames[i].paddr;
  301. /* Start addresses of Y, Cb, Cr planes */
  302. coda_parabuf_write(ctx, i * 3 + 0, paddr);
  303. coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize);
  304. coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize / 4);
  305. /* mvcol buffer for h.264 */
  306. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  307. dev->devtype->product != CODA_DX6)
  308. coda_parabuf_write(ctx, 96 + i,
  309. ctx->internal_frames[i].paddr +
  310. ysize + ysize/4 + ysize/4);
  311. }
  312. /* mvcol buffer for mpeg4 */
  313. if ((dev->devtype->product != CODA_DX6) &&
  314. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
  315. coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
  316. ysize + ysize/4 + ysize/4);
  317. return 0;
  318. }
  319. static void coda_free_context_buffers(struct coda_ctx *ctx)
  320. {
  321. struct coda_dev *dev = ctx->dev;
  322. coda_free_aux_buf(dev, &ctx->slicebuf);
  323. coda_free_aux_buf(dev, &ctx->psbuf);
  324. if (dev->devtype->product != CODA_DX6)
  325. coda_free_aux_buf(dev, &ctx->workbuf);
  326. coda_free_aux_buf(dev, &ctx->parabuf);
  327. }
  328. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  329. struct coda_q_data *q_data)
  330. {
  331. struct coda_dev *dev = ctx->dev;
  332. size_t size;
  333. int ret;
  334. if (!ctx->parabuf.vaddr) {
  335. ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
  336. CODA_PARA_BUF_SIZE, "parabuf");
  337. if (ret < 0)
  338. return ret;
  339. }
  340. if (dev->devtype->product == CODA_DX6)
  341. return 0;
  342. if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
  343. /* worst case slice size */
  344. size = (DIV_ROUND_UP(q_data->width, 16) *
  345. DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
  346. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  347. "slicebuf");
  348. if (ret < 0)
  349. goto err;
  350. }
  351. if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
  352. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  353. CODA7_PS_BUF_SIZE, "psbuf");
  354. if (ret < 0)
  355. goto err;
  356. }
  357. if (!ctx->workbuf.vaddr) {
  358. size = dev->devtype->workbuf_size;
  359. if (dev->devtype->product == CODA_960 &&
  360. q_data->fourcc == V4L2_PIX_FMT_H264)
  361. size += CODA9_PS_SAVE_SIZE;
  362. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
  363. "workbuf");
  364. if (ret < 0)
  365. goto err;
  366. }
  367. return 0;
  368. err:
  369. coda_free_context_buffers(ctx);
  370. return ret;
  371. }
  372. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
  373. int header_code, u8 *header, int *size)
  374. {
  375. struct coda_dev *dev = ctx->dev;
  376. size_t bufsize;
  377. int ret;
  378. int i;
  379. if (dev->devtype->product == CODA_960)
  380. memset(vb2_plane_vaddr(buf, 0), 0, 64);
  381. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
  382. CODA_CMD_ENC_HEADER_BB_START);
  383. bufsize = vb2_plane_size(buf, 0);
  384. if (dev->devtype->product == CODA_960)
  385. bufsize /= 1024;
  386. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  387. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  388. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  389. if (ret < 0) {
  390. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  391. return ret;
  392. }
  393. if (dev->devtype->product == CODA_960) {
  394. for (i = 63; i > 0; i--)
  395. if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
  396. break;
  397. *size = i + 1;
  398. } else {
  399. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  400. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  401. }
  402. memcpy(header, vb2_plane_vaddr(buf, 0), *size);
  403. return 0;
  404. }
  405. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  406. {
  407. phys_addr_t ret;
  408. size = round_up(size, 1024);
  409. if (size > iram->remaining)
  410. return 0;
  411. iram->remaining -= size;
  412. ret = iram->next_paddr;
  413. iram->next_paddr += size;
  414. return ret;
  415. }
  416. static void coda_setup_iram(struct coda_ctx *ctx)
  417. {
  418. struct coda_iram_info *iram_info = &ctx->iram_info;
  419. struct coda_dev *dev = ctx->dev;
  420. int w64, w128;
  421. int mb_width;
  422. int dbk_bits;
  423. int bit_bits;
  424. int ip_bits;
  425. memset(iram_info, 0, sizeof(*iram_info));
  426. iram_info->next_paddr = dev->iram.paddr;
  427. iram_info->remaining = dev->iram.size;
  428. if (!dev->iram.vaddr)
  429. return;
  430. switch (dev->devtype->product) {
  431. case CODA_7541:
  432. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  433. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  434. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  435. break;
  436. case CODA_960:
  437. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  438. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  439. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  440. break;
  441. default: /* CODA_DX6 */
  442. return;
  443. }
  444. if (ctx->inst_type == CODA_INST_ENCODER) {
  445. struct coda_q_data *q_data_src;
  446. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  447. mb_width = DIV_ROUND_UP(q_data_src->width, 16);
  448. w128 = mb_width * 128;
  449. w64 = mb_width * 64;
  450. /* Prioritize in case IRAM is too small for everything */
  451. if (dev->devtype->product == CODA_7541) {
  452. iram_info->search_ram_size = round_up(mb_width * 16 *
  453. 36 + 2048, 1024);
  454. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  455. iram_info->search_ram_size);
  456. if (!iram_info->search_ram_paddr) {
  457. pr_err("IRAM is smaller than the search ram size\n");
  458. goto out;
  459. }
  460. iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
  461. CODA7_USE_ME_ENABLE;
  462. }
  463. /* Only H.264BP and H.263P3 are considered */
  464. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  465. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  466. if (!iram_info->buf_dbk_c_use)
  467. goto out;
  468. iram_info->axi_sram_use |= dbk_bits;
  469. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  470. if (!iram_info->buf_bit_use)
  471. goto out;
  472. iram_info->axi_sram_use |= bit_bits;
  473. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  474. if (!iram_info->buf_ip_ac_dc_use)
  475. goto out;
  476. iram_info->axi_sram_use |= ip_bits;
  477. /* OVL and BTP disabled for encoder */
  478. } else if (ctx->inst_type == CODA_INST_DECODER) {
  479. struct coda_q_data *q_data_dst;
  480. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  481. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  482. w128 = mb_width * 128;
  483. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  484. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  485. if (!iram_info->buf_dbk_c_use)
  486. goto out;
  487. iram_info->axi_sram_use |= dbk_bits;
  488. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  489. if (!iram_info->buf_bit_use)
  490. goto out;
  491. iram_info->axi_sram_use |= bit_bits;
  492. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  493. if (!iram_info->buf_ip_ac_dc_use)
  494. goto out;
  495. iram_info->axi_sram_use |= ip_bits;
  496. /* OVL and BTP unused as there is no VC1 support yet */
  497. }
  498. out:
  499. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  500. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  501. "IRAM smaller than needed\n");
  502. if (dev->devtype->product == CODA_7541) {
  503. /* TODO - Enabling these causes picture errors on CODA7541 */
  504. if (ctx->inst_type == CODA_INST_DECODER) {
  505. /* fw 1.4.50 */
  506. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  507. CODA7_USE_IP_ENABLE);
  508. } else {
  509. /* fw 13.4.29 */
  510. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  511. CODA7_USE_HOST_DBK_ENABLE |
  512. CODA7_USE_IP_ENABLE |
  513. CODA7_USE_DBK_ENABLE);
  514. }
  515. }
  516. }
  517. static u32 coda_supported_firmwares[] = {
  518. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  519. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  520. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  521. };
  522. static bool coda_firmware_supported(u32 vernum)
  523. {
  524. int i;
  525. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  526. if (vernum == coda_supported_firmwares[i])
  527. return true;
  528. return false;
  529. }
  530. int coda_check_firmware(struct coda_dev *dev)
  531. {
  532. u16 product, major, minor, release;
  533. u32 data;
  534. int ret;
  535. ret = clk_prepare_enable(dev->clk_per);
  536. if (ret)
  537. goto err_clk_per;
  538. ret = clk_prepare_enable(dev->clk_ahb);
  539. if (ret)
  540. goto err_clk_ahb;
  541. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  542. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  543. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  544. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  545. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  546. if (coda_wait_timeout(dev)) {
  547. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  548. ret = -EIO;
  549. goto err_run_cmd;
  550. }
  551. if (dev->devtype->product == CODA_960) {
  552. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  553. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  554. data);
  555. }
  556. /* Check we are compatible with the loaded firmware */
  557. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  558. product = CODA_FIRMWARE_PRODUCT(data);
  559. major = CODA_FIRMWARE_MAJOR(data);
  560. minor = CODA_FIRMWARE_MINOR(data);
  561. release = CODA_FIRMWARE_RELEASE(data);
  562. clk_disable_unprepare(dev->clk_per);
  563. clk_disable_unprepare(dev->clk_ahb);
  564. if (product != dev->devtype->product) {
  565. v4l2_err(&dev->v4l2_dev,
  566. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  567. coda_product_name(dev->devtype->product),
  568. coda_product_name(product), major, minor, release);
  569. return -EINVAL;
  570. }
  571. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  572. coda_product_name(product));
  573. if (coda_firmware_supported(data)) {
  574. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  575. major, minor, release);
  576. } else {
  577. v4l2_warn(&dev->v4l2_dev,
  578. "Unsupported firmware version: %u.%u.%u\n",
  579. major, minor, release);
  580. }
  581. return 0;
  582. err_run_cmd:
  583. clk_disable_unprepare(dev->clk_ahb);
  584. err_clk_ahb:
  585. clk_disable_unprepare(dev->clk_per);
  586. err_clk_per:
  587. return ret;
  588. }
  589. /*
  590. * Encoder context operations
  591. */
  592. static int coda_encoder_reqbufs(struct coda_ctx *ctx,
  593. struct v4l2_requestbuffers *rb)
  594. {
  595. struct coda_q_data *q_data_src;
  596. int ret;
  597. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  598. return 0;
  599. if (rb->count) {
  600. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  601. ret = coda_alloc_context_buffers(ctx, q_data_src);
  602. if (ret < 0)
  603. return ret;
  604. } else {
  605. coda_free_context_buffers(ctx);
  606. }
  607. return 0;
  608. }
  609. static int coda_start_encoding(struct coda_ctx *ctx)
  610. {
  611. struct coda_dev *dev = ctx->dev;
  612. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  613. struct coda_q_data *q_data_src, *q_data_dst;
  614. u32 bitstream_buf, bitstream_size;
  615. struct vb2_buffer *buf;
  616. int gamma, ret, value;
  617. u32 dst_fourcc;
  618. int num_fb;
  619. u32 stride;
  620. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  621. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  622. dst_fourcc = q_data_dst->fourcc;
  623. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  624. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  625. bitstream_size = q_data_dst->sizeimage;
  626. if (!coda_is_initialized(dev)) {
  627. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  628. return -EFAULT;
  629. }
  630. if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
  631. if (!ctx->params.jpeg_qmat_tab[0])
  632. ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
  633. if (!ctx->params.jpeg_qmat_tab[1])
  634. ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
  635. coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
  636. }
  637. mutex_lock(&dev->coda_mutex);
  638. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  639. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  640. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  641. switch (dev->devtype->product) {
  642. case CODA_DX6:
  643. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  644. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  645. break;
  646. case CODA_960:
  647. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  648. /* fallthrough */
  649. case CODA_7541:
  650. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  651. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  652. break;
  653. }
  654. ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
  655. if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
  656. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  657. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  658. if (dev->devtype->product == CODA_DX6) {
  659. /* Configure the coda */
  660. coda_write(dev, dev->iram.paddr,
  661. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  662. }
  663. /* Could set rotation here if needed */
  664. value = 0;
  665. switch (dev->devtype->product) {
  666. case CODA_DX6:
  667. value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
  668. << CODADX6_PICWIDTH_OFFSET;
  669. value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
  670. << CODA_PICHEIGHT_OFFSET;
  671. break;
  672. case CODA_7541:
  673. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  674. value = (round_up(q_data_src->width, 16) &
  675. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  676. value |= (round_up(q_data_src->height, 16) &
  677. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  678. break;
  679. }
  680. /* fallthrough */
  681. case CODA_960:
  682. value = (q_data_src->width & CODA7_PICWIDTH_MASK)
  683. << CODA7_PICWIDTH_OFFSET;
  684. value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
  685. << CODA_PICHEIGHT_OFFSET;
  686. }
  687. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  688. if (dst_fourcc == V4L2_PIX_FMT_JPEG)
  689. ctx->params.framerate = 0;
  690. coda_write(dev, ctx->params.framerate,
  691. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  692. ctx->params.codec_mode = ctx->codec->mode;
  693. switch (dst_fourcc) {
  694. case V4L2_PIX_FMT_MPEG4:
  695. if (dev->devtype->product == CODA_960)
  696. coda_write(dev, CODA9_STD_MPEG4,
  697. CODA_CMD_ENC_SEQ_COD_STD);
  698. else
  699. coda_write(dev, CODA_STD_MPEG4,
  700. CODA_CMD_ENC_SEQ_COD_STD);
  701. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  702. break;
  703. case V4L2_PIX_FMT_H264:
  704. if (dev->devtype->product == CODA_960)
  705. coda_write(dev, CODA9_STD_H264,
  706. CODA_CMD_ENC_SEQ_COD_STD);
  707. else
  708. coda_write(dev, CODA_STD_H264,
  709. CODA_CMD_ENC_SEQ_COD_STD);
  710. if (ctx->params.h264_deblk_enabled) {
  711. value = ((ctx->params.h264_deblk_alpha &
  712. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  713. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  714. ((ctx->params.h264_deblk_beta &
  715. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  716. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
  717. } else {
  718. value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
  719. }
  720. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  721. break;
  722. case V4L2_PIX_FMT_JPEG:
  723. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
  724. coda_write(dev, ctx->params.jpeg_restart_interval,
  725. CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
  726. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
  727. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
  728. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
  729. coda_jpeg_write_tables(ctx);
  730. break;
  731. default:
  732. v4l2_err(v4l2_dev,
  733. "dst format (0x%08x) invalid.\n", dst_fourcc);
  734. ret = -EINVAL;
  735. goto out;
  736. }
  737. /*
  738. * slice mode and GOP size registers are used for thumb size/offset
  739. * in JPEG mode
  740. */
  741. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  742. switch (ctx->params.slice_mode) {
  743. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  744. value = 0;
  745. break;
  746. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  747. value = (ctx->params.slice_max_mb &
  748. CODA_SLICING_SIZE_MASK)
  749. << CODA_SLICING_SIZE_OFFSET;
  750. value |= (1 & CODA_SLICING_UNIT_MASK)
  751. << CODA_SLICING_UNIT_OFFSET;
  752. value |= 1 & CODA_SLICING_MODE_MASK;
  753. break;
  754. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  755. value = (ctx->params.slice_max_bits &
  756. CODA_SLICING_SIZE_MASK)
  757. << CODA_SLICING_SIZE_OFFSET;
  758. value |= (0 & CODA_SLICING_UNIT_MASK)
  759. << CODA_SLICING_UNIT_OFFSET;
  760. value |= 1 & CODA_SLICING_MODE_MASK;
  761. break;
  762. }
  763. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  764. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  765. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  766. }
  767. if (ctx->params.bitrate) {
  768. /* Rate control enabled */
  769. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  770. << CODA_RATECONTROL_BITRATE_OFFSET;
  771. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  772. if (dev->devtype->product == CODA_960)
  773. value |= BIT(31); /* disable autoskip */
  774. } else {
  775. value = 0;
  776. }
  777. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  778. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  779. coda_write(dev, ctx->params.intra_refresh,
  780. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  781. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  782. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  783. value = 0;
  784. if (dev->devtype->product == CODA_960)
  785. gamma = CODA9_DEFAULT_GAMMA;
  786. else
  787. gamma = CODA_DEFAULT_GAMMA;
  788. if (gamma > 0) {
  789. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  790. CODA_CMD_ENC_SEQ_RC_GAMMA);
  791. }
  792. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  793. coda_write(dev,
  794. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  795. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  796. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  797. }
  798. if (dev->devtype->product == CODA_960) {
  799. if (ctx->params.h264_max_qp)
  800. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  801. if (CODA_DEFAULT_GAMMA > 0)
  802. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  803. } else {
  804. if (CODA_DEFAULT_GAMMA > 0) {
  805. if (dev->devtype->product == CODA_DX6)
  806. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  807. else
  808. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  809. }
  810. if (ctx->params.h264_min_qp)
  811. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  812. if (ctx->params.h264_max_qp)
  813. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  814. }
  815. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  816. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  817. coda_setup_iram(ctx);
  818. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  819. switch (dev->devtype->product) {
  820. case CODA_DX6:
  821. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  822. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  823. break;
  824. case CODA_7541:
  825. coda_write(dev, ctx->iram_info.search_ram_paddr,
  826. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  827. coda_write(dev, ctx->iram_info.search_ram_size,
  828. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  829. break;
  830. case CODA_960:
  831. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  832. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  833. }
  834. }
  835. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  836. if (ret < 0) {
  837. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  838. goto out;
  839. }
  840. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  841. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  842. ret = -EFAULT;
  843. goto out;
  844. }
  845. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  846. if (dev->devtype->product == CODA_960)
  847. ctx->num_internal_frames = 4;
  848. else
  849. ctx->num_internal_frames = 2;
  850. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  851. if (ret < 0) {
  852. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  853. goto out;
  854. }
  855. num_fb = 2;
  856. stride = q_data_src->bytesperline;
  857. } else {
  858. ctx->num_internal_frames = 0;
  859. num_fb = 0;
  860. stride = 0;
  861. }
  862. coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
  863. coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
  864. if (dev->devtype->product == CODA_7541) {
  865. coda_write(dev, q_data_src->bytesperline,
  866. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  867. }
  868. if (dev->devtype->product != CODA_DX6) {
  869. coda_write(dev, ctx->iram_info.buf_bit_use,
  870. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  871. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  872. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  873. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  874. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  875. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  876. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  877. coda_write(dev, ctx->iram_info.buf_ovl_use,
  878. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  879. if (dev->devtype->product == CODA_960) {
  880. coda_write(dev, ctx->iram_info.buf_btp_use,
  881. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  882. /* FIXME */
  883. coda_write(dev, ctx->internal_frames[2].paddr,
  884. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  885. coda_write(dev, ctx->internal_frames[3].paddr,
  886. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  887. }
  888. }
  889. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  890. if (ret < 0) {
  891. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  892. goto out;
  893. }
  894. /* Save stream headers */
  895. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  896. switch (dst_fourcc) {
  897. case V4L2_PIX_FMT_H264:
  898. /*
  899. * Get SPS in the first frame and copy it to an
  900. * intermediate buffer.
  901. */
  902. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  903. &ctx->vpu_header[0][0],
  904. &ctx->vpu_header_size[0]);
  905. if (ret < 0)
  906. goto out;
  907. /*
  908. * Get PPS in the first frame and copy it to an
  909. * intermediate buffer.
  910. */
  911. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  912. &ctx->vpu_header[1][0],
  913. &ctx->vpu_header_size[1]);
  914. if (ret < 0)
  915. goto out;
  916. /*
  917. * Length of H.264 headers is variable and thus it might not be
  918. * aligned for the coda to append the encoded frame. In that is
  919. * the case a filler NAL must be added to header 2.
  920. */
  921. ctx->vpu_header_size[2] = coda_h264_padding(
  922. (ctx->vpu_header_size[0] +
  923. ctx->vpu_header_size[1]),
  924. ctx->vpu_header[2]);
  925. break;
  926. case V4L2_PIX_FMT_MPEG4:
  927. /*
  928. * Get VOS in the first frame and copy it to an
  929. * intermediate buffer
  930. */
  931. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  932. &ctx->vpu_header[0][0],
  933. &ctx->vpu_header_size[0]);
  934. if (ret < 0)
  935. goto out;
  936. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  937. &ctx->vpu_header[1][0],
  938. &ctx->vpu_header_size[1]);
  939. if (ret < 0)
  940. goto out;
  941. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  942. &ctx->vpu_header[2][0],
  943. &ctx->vpu_header_size[2]);
  944. if (ret < 0)
  945. goto out;
  946. break;
  947. default:
  948. /* No more formats need to save headers at the moment */
  949. break;
  950. }
  951. out:
  952. mutex_unlock(&dev->coda_mutex);
  953. return ret;
  954. }
  955. static int coda_prepare_encode(struct coda_ctx *ctx)
  956. {
  957. struct coda_q_data *q_data_src, *q_data_dst;
  958. struct vb2_buffer *src_buf, *dst_buf;
  959. struct coda_dev *dev = ctx->dev;
  960. int force_ipicture;
  961. int quant_param = 0;
  962. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  963. u32 rot_mode = 0;
  964. u32 dst_fourcc;
  965. u32 reg;
  966. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  967. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  968. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  969. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  970. dst_fourcc = q_data_dst->fourcc;
  971. src_buf->v4l2_buf.sequence = ctx->osequence;
  972. dst_buf->v4l2_buf.sequence = ctx->osequence;
  973. ctx->osequence++;
  974. /*
  975. * Workaround coda firmware BUG that only marks the first
  976. * frame as IDR. This is a problem for some decoders that can't
  977. * recover when a frame is lost.
  978. */
  979. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  980. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  981. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  982. } else {
  983. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  984. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  985. }
  986. if (dev->devtype->product == CODA_960)
  987. coda_set_gdi_regs(ctx);
  988. /*
  989. * Copy headers at the beginning of the first frame for H.264 only.
  990. * In MPEG4 they are already copied by the coda.
  991. */
  992. if (src_buf->v4l2_buf.sequence == 0) {
  993. pic_stream_buffer_addr =
  994. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  995. ctx->vpu_header_size[0] +
  996. ctx->vpu_header_size[1] +
  997. ctx->vpu_header_size[2];
  998. pic_stream_buffer_size = q_data_dst->sizeimage -
  999. ctx->vpu_header_size[0] -
  1000. ctx->vpu_header_size[1] -
  1001. ctx->vpu_header_size[2];
  1002. memcpy(vb2_plane_vaddr(dst_buf, 0),
  1003. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  1004. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  1005. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  1006. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  1007. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  1008. ctx->vpu_header_size[2]);
  1009. } else {
  1010. pic_stream_buffer_addr =
  1011. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  1012. pic_stream_buffer_size = q_data_dst->sizeimage;
  1013. }
  1014. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1015. force_ipicture = 1;
  1016. switch (dst_fourcc) {
  1017. case V4L2_PIX_FMT_H264:
  1018. quant_param = ctx->params.h264_intra_qp;
  1019. break;
  1020. case V4L2_PIX_FMT_MPEG4:
  1021. quant_param = ctx->params.mpeg4_intra_qp;
  1022. break;
  1023. case V4L2_PIX_FMT_JPEG:
  1024. quant_param = 30;
  1025. break;
  1026. default:
  1027. v4l2_warn(&ctx->dev->v4l2_dev,
  1028. "cannot set intra qp, fmt not supported\n");
  1029. break;
  1030. }
  1031. } else {
  1032. force_ipicture = 0;
  1033. switch (dst_fourcc) {
  1034. case V4L2_PIX_FMT_H264:
  1035. quant_param = ctx->params.h264_inter_qp;
  1036. break;
  1037. case V4L2_PIX_FMT_MPEG4:
  1038. quant_param = ctx->params.mpeg4_inter_qp;
  1039. break;
  1040. default:
  1041. v4l2_warn(&ctx->dev->v4l2_dev,
  1042. "cannot set inter qp, fmt not supported\n");
  1043. break;
  1044. }
  1045. }
  1046. /* submit */
  1047. if (ctx->params.rot_mode)
  1048. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1049. coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  1050. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  1051. if (dev->devtype->product == CODA_960) {
  1052. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  1053. coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
  1054. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  1055. reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
  1056. } else {
  1057. reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
  1058. }
  1059. coda_write_base(ctx, q_data_src, src_buf, reg);
  1060. coda_write(dev, force_ipicture << 1 & 0x2,
  1061. CODA_CMD_ENC_PIC_OPTION);
  1062. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1063. coda_write(dev, pic_stream_buffer_size / 1024,
  1064. CODA_CMD_ENC_PIC_BB_SIZE);
  1065. if (!ctx->streamon_out) {
  1066. /* After streamoff on the output side, set stream end flag */
  1067. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1068. coda_write(dev, ctx->bit_stream_param,
  1069. CODA_REG_BIT_BIT_STREAM_PARAM);
  1070. }
  1071. if (dev->devtype->product != CODA_DX6)
  1072. coda_write(dev, ctx->iram_info.axi_sram_use,
  1073. CODA7_REG_BIT_AXI_SRAM_USE);
  1074. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1075. return 0;
  1076. }
  1077. static void coda_finish_encode(struct coda_ctx *ctx)
  1078. {
  1079. struct vb2_buffer *src_buf, *dst_buf;
  1080. struct coda_dev *dev = ctx->dev;
  1081. u32 wr_ptr, start_ptr;
  1082. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1083. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1084. /* Get results from the coda */
  1085. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1086. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1087. /* Calculate bytesused field */
  1088. if (dst_buf->v4l2_buf.sequence == 0) {
  1089. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
  1090. ctx->vpu_header_size[0] +
  1091. ctx->vpu_header_size[1] +
  1092. ctx->vpu_header_size[2]);
  1093. } else {
  1094. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
  1095. }
  1096. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1097. wr_ptr - start_ptr);
  1098. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1099. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1100. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
  1101. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1102. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1103. } else {
  1104. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1105. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1106. }
  1107. dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
  1108. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1109. dst_buf->v4l2_buf.flags |=
  1110. src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1111. dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
  1112. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1113. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1114. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1115. ctx->gopcounter--;
  1116. if (ctx->gopcounter < 0)
  1117. ctx->gopcounter = ctx->params.gop_size - 1;
  1118. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1119. "job finished: encoding frame (%d) (%s)\n",
  1120. dst_buf->v4l2_buf.sequence,
  1121. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1122. "KEYFRAME" : "PFRAME");
  1123. }
  1124. static void coda_seq_end_work(struct work_struct *work)
  1125. {
  1126. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1127. struct coda_dev *dev = ctx->dev;
  1128. mutex_lock(&ctx->buffer_mutex);
  1129. mutex_lock(&dev->coda_mutex);
  1130. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1131. "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
  1132. __func__);
  1133. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1134. v4l2_err(&dev->v4l2_dev,
  1135. "CODA_COMMAND_SEQ_END failed\n");
  1136. }
  1137. kfifo_init(&ctx->bitstream_fifo,
  1138. ctx->bitstream.vaddr, ctx->bitstream.size);
  1139. coda_free_framebuffers(ctx);
  1140. mutex_unlock(&dev->coda_mutex);
  1141. mutex_unlock(&ctx->buffer_mutex);
  1142. }
  1143. static void coda_bit_release(struct coda_ctx *ctx)
  1144. {
  1145. mutex_lock(&ctx->buffer_mutex);
  1146. coda_free_framebuffers(ctx);
  1147. coda_free_context_buffers(ctx);
  1148. coda_free_bitstream_buffer(ctx);
  1149. mutex_unlock(&ctx->buffer_mutex);
  1150. }
  1151. const struct coda_context_ops coda_bit_encode_ops = {
  1152. .queue_init = coda_encoder_queue_init,
  1153. .reqbufs = coda_encoder_reqbufs,
  1154. .start_streaming = coda_start_encoding,
  1155. .prepare_run = coda_prepare_encode,
  1156. .finish_run = coda_finish_encode,
  1157. .seq_end_work = coda_seq_end_work,
  1158. .release = coda_bit_release,
  1159. };
  1160. /*
  1161. * Decoder context operations
  1162. */
  1163. static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
  1164. struct coda_q_data *q_data)
  1165. {
  1166. if (ctx->bitstream.vaddr)
  1167. return 0;
  1168. ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
  1169. ctx->bitstream.vaddr = dma_alloc_writecombine(
  1170. &ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1171. &ctx->bitstream.paddr, GFP_KERNEL);
  1172. if (!ctx->bitstream.vaddr) {
  1173. v4l2_err(&ctx->dev->v4l2_dev,
  1174. "failed to allocate bitstream ringbuffer");
  1175. return -ENOMEM;
  1176. }
  1177. kfifo_init(&ctx->bitstream_fifo,
  1178. ctx->bitstream.vaddr, ctx->bitstream.size);
  1179. return 0;
  1180. }
  1181. static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
  1182. {
  1183. if (ctx->bitstream.vaddr == NULL)
  1184. return;
  1185. dma_free_writecombine(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1186. ctx->bitstream.vaddr, ctx->bitstream.paddr);
  1187. ctx->bitstream.vaddr = NULL;
  1188. kfifo_init(&ctx->bitstream_fifo, NULL, 0);
  1189. }
  1190. static int coda_decoder_reqbufs(struct coda_ctx *ctx,
  1191. struct v4l2_requestbuffers *rb)
  1192. {
  1193. struct coda_q_data *q_data_src;
  1194. int ret;
  1195. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  1196. return 0;
  1197. if (rb->count) {
  1198. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1199. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1200. if (ret < 0)
  1201. return ret;
  1202. ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
  1203. if (ret < 0) {
  1204. coda_free_context_buffers(ctx);
  1205. return ret;
  1206. }
  1207. } else {
  1208. coda_free_bitstream_buffer(ctx);
  1209. coda_free_context_buffers(ctx);
  1210. }
  1211. return 0;
  1212. }
  1213. static int __coda_start_decoding(struct coda_ctx *ctx)
  1214. {
  1215. struct coda_q_data *q_data_src, *q_data_dst;
  1216. u32 bitstream_buf, bitstream_size;
  1217. struct coda_dev *dev = ctx->dev;
  1218. int width, height;
  1219. u32 src_fourcc, dst_fourcc;
  1220. u32 val;
  1221. int ret;
  1222. /* Start decoding */
  1223. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1224. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1225. bitstream_buf = ctx->bitstream.paddr;
  1226. bitstream_size = ctx->bitstream.size;
  1227. src_fourcc = q_data_src->fourcc;
  1228. dst_fourcc = q_data_dst->fourcc;
  1229. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1230. /* Update coda bitstream read and write pointers from kfifo */
  1231. coda_kfifo_sync_to_device_full(ctx);
  1232. ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
  1233. if (dst_fourcc == V4L2_PIX_FMT_NV12)
  1234. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1235. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  1236. ctx->display_idx = -1;
  1237. ctx->frm_dis_flg = 0;
  1238. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1239. coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
  1240. CODA_REG_BIT_BIT_STREAM_PARAM);
  1241. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1242. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1243. val = 0;
  1244. if ((dev->devtype->product == CODA_7541) ||
  1245. (dev->devtype->product == CODA_960))
  1246. val |= CODA_REORDER_ENABLE;
  1247. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1248. val |= CODA_NO_INT_ENABLE;
  1249. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1250. ctx->params.codec_mode = ctx->codec->mode;
  1251. if (dev->devtype->product == CODA_960 &&
  1252. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1253. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1254. else
  1255. ctx->params.codec_mode_aux = 0;
  1256. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1257. if (dev->devtype->product == CODA_7541) {
  1258. coda_write(dev, ctx->psbuf.paddr,
  1259. CODA_CMD_DEC_SEQ_PS_BB_START);
  1260. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1261. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1262. }
  1263. if (dev->devtype->product == CODA_960) {
  1264. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1265. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1266. }
  1267. }
  1268. if (dev->devtype->product != CODA_960)
  1269. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1270. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  1271. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1272. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1273. return -ETIMEDOUT;
  1274. }
  1275. /* Update kfifo out pointer from coda bitstream read pointer */
  1276. coda_kfifo_sync_from_device(ctx);
  1277. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1278. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1279. v4l2_err(&dev->v4l2_dev,
  1280. "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
  1281. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1282. return -EAGAIN;
  1283. }
  1284. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1285. if (dev->devtype->product == CODA_DX6) {
  1286. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1287. height = val & CODADX6_PICHEIGHT_MASK;
  1288. } else {
  1289. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1290. height = val & CODA7_PICHEIGHT_MASK;
  1291. }
  1292. if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
  1293. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1294. width, height, q_data_dst->bytesperline,
  1295. q_data_dst->height);
  1296. return -EINVAL;
  1297. }
  1298. width = round_up(width, 16);
  1299. height = round_up(height, 16);
  1300. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
  1301. __func__, ctx->idx, width, height);
  1302. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1303. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1304. v4l2_err(&dev->v4l2_dev,
  1305. "not enough framebuffers to decode (%d < %d)\n",
  1306. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1307. return -EINVAL;
  1308. }
  1309. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1310. u32 left_right;
  1311. u32 top_bottom;
  1312. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1313. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1314. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1315. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1316. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1317. (left_right & 0x3ff);
  1318. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1319. (top_bottom & 0x3ff);
  1320. }
  1321. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1322. if (ret < 0) {
  1323. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1324. return ret;
  1325. }
  1326. /* Tell the decoder how many frame buffers we allocated. */
  1327. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1328. coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1329. if (dev->devtype->product != CODA_DX6) {
  1330. /* Set secondary AXI IRAM */
  1331. coda_setup_iram(ctx);
  1332. coda_write(dev, ctx->iram_info.buf_bit_use,
  1333. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1334. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1335. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1336. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1337. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1338. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1339. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1340. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1341. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1342. if (dev->devtype->product == CODA_960)
  1343. coda_write(dev, ctx->iram_info.buf_btp_use,
  1344. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1345. }
  1346. if (dev->devtype->product == CODA_960) {
  1347. int cbb_size, crb_size;
  1348. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1349. /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
  1350. coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  1351. if (dst_fourcc == V4L2_PIX_FMT_NV12) {
  1352. cbb_size = 0;
  1353. crb_size = 16;
  1354. } else {
  1355. cbb_size = 8;
  1356. crb_size = 8;
  1357. }
  1358. coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
  1359. 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  1360. cbb_size << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
  1361. crb_size << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
  1362. CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  1363. }
  1364. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1365. coda_write(dev, ctx->slicebuf.paddr,
  1366. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1367. coda_write(dev, ctx->slicebuf.size / 1024,
  1368. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1369. }
  1370. if (dev->devtype->product == CODA_7541) {
  1371. int max_mb_x = 1920 / 16;
  1372. int max_mb_y = 1088 / 16;
  1373. int max_mb_num = max_mb_x * max_mb_y;
  1374. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1375. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1376. } else if (dev->devtype->product == CODA_960) {
  1377. int max_mb_x = 1920 / 16;
  1378. int max_mb_y = 1088 / 16;
  1379. int max_mb_num = max_mb_x * max_mb_y;
  1380. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1381. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1382. }
  1383. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1384. v4l2_err(&ctx->dev->v4l2_dev,
  1385. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1386. return -ETIMEDOUT;
  1387. }
  1388. return 0;
  1389. }
  1390. static int coda_start_decoding(struct coda_ctx *ctx)
  1391. {
  1392. struct coda_dev *dev = ctx->dev;
  1393. int ret;
  1394. mutex_lock(&dev->coda_mutex);
  1395. ret = __coda_start_decoding(ctx);
  1396. mutex_unlock(&dev->coda_mutex);
  1397. return ret;
  1398. }
  1399. static int coda_prepare_decode(struct coda_ctx *ctx)
  1400. {
  1401. struct vb2_buffer *dst_buf;
  1402. struct coda_dev *dev = ctx->dev;
  1403. struct coda_q_data *q_data_dst;
  1404. struct coda_buffer_meta *meta;
  1405. u32 reg_addr, reg_stride;
  1406. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1407. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1408. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1409. mutex_lock(&ctx->bitstream_mutex);
  1410. coda_fill_bitstream(ctx, true);
  1411. mutex_unlock(&ctx->bitstream_mutex);
  1412. if (coda_get_bitstream_payload(ctx) < 512 &&
  1413. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1414. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1415. "bitstream payload: %d, skipping\n",
  1416. coda_get_bitstream_payload(ctx));
  1417. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1418. return -EAGAIN;
  1419. }
  1420. /* Run coda_start_decoding (again) if not yet initialized */
  1421. if (!ctx->initialized) {
  1422. int ret = __coda_start_decoding(ctx);
  1423. if (ret < 0) {
  1424. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1425. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1426. return -EAGAIN;
  1427. } else {
  1428. ctx->initialized = 1;
  1429. }
  1430. }
  1431. if (dev->devtype->product == CODA_960)
  1432. coda_set_gdi_regs(ctx);
  1433. if (dev->devtype->product == CODA_960) {
  1434. /*
  1435. * The CODA960 seems to have an internal list of buffers with
  1436. * 64 entries that includes the registered frame buffers as
  1437. * well as the rotator buffer output.
  1438. * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
  1439. */
  1440. coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
  1441. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1442. reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
  1443. reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
  1444. } else {
  1445. reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
  1446. reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
  1447. }
  1448. coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
  1449. coda_write(dev, q_data_dst->bytesperline, reg_stride);
  1450. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
  1451. CODA_CMD_DEC_PIC_ROT_MODE);
  1452. switch (dev->devtype->product) {
  1453. case CODA_DX6:
  1454. /* TBD */
  1455. case CODA_7541:
  1456. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1457. break;
  1458. case CODA_960:
  1459. /* 'hardcode to use interrupt disable mode'? */
  1460. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1461. break;
  1462. }
  1463. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1464. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1465. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1466. if (dev->devtype->product != CODA_DX6)
  1467. coda_write(dev, ctx->iram_info.axi_sram_use,
  1468. CODA7_REG_BIT_AXI_SRAM_USE);
  1469. meta = list_first_entry_or_null(&ctx->buffer_meta_list,
  1470. struct coda_buffer_meta, list);
  1471. if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
  1472. /* If this is the last buffer in the bitstream, add padding */
  1473. if (meta->end == (ctx->bitstream_fifo.kfifo.in &
  1474. ctx->bitstream_fifo.kfifo.mask)) {
  1475. static unsigned char buf[512];
  1476. unsigned int pad;
  1477. /* Pad to multiple of 256 and then add 256 more */
  1478. pad = ((0 - meta->end) & 0xff) + 256;
  1479. memset(buf, 0xff, sizeof(buf));
  1480. kfifo_in(&ctx->bitstream_fifo, buf, pad);
  1481. }
  1482. }
  1483. coda_kfifo_sync_to_device_full(ctx);
  1484. /* Clear decode success flag */
  1485. coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
  1486. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1487. return 0;
  1488. }
  1489. static void coda_finish_decode(struct coda_ctx *ctx)
  1490. {
  1491. struct coda_dev *dev = ctx->dev;
  1492. struct coda_q_data *q_data_src;
  1493. struct coda_q_data *q_data_dst;
  1494. struct vb2_buffer *dst_buf;
  1495. struct coda_buffer_meta *meta;
  1496. unsigned long payload;
  1497. int width, height;
  1498. int decoded_idx;
  1499. int display_idx;
  1500. u32 src_fourcc;
  1501. int success;
  1502. u32 err_mb;
  1503. u32 val;
  1504. /* Update kfifo out pointer from coda bitstream read pointer */
  1505. coda_kfifo_sync_from_device(ctx);
  1506. /*
  1507. * in stream-end mode, the read pointer can overshoot the write pointer
  1508. * by up to 512 bytes
  1509. */
  1510. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1511. if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
  1512. kfifo_init(&ctx->bitstream_fifo,
  1513. ctx->bitstream.vaddr, ctx->bitstream.size);
  1514. }
  1515. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1516. src_fourcc = q_data_src->fourcc;
  1517. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1518. if (val != 1)
  1519. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1520. success = val & 0x1;
  1521. if (!success)
  1522. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1523. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1524. if (val & (1 << 3))
  1525. v4l2_err(&dev->v4l2_dev,
  1526. "insufficient PS buffer space (%d bytes)\n",
  1527. ctx->psbuf.size);
  1528. if (val & (1 << 2))
  1529. v4l2_err(&dev->v4l2_dev,
  1530. "insufficient slice buffer space (%d bytes)\n",
  1531. ctx->slicebuf.size);
  1532. }
  1533. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  1534. width = (val >> 16) & 0xffff;
  1535. height = val & 0xffff;
  1536. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1537. /* frame crop information */
  1538. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1539. u32 left_right;
  1540. u32 top_bottom;
  1541. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  1542. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  1543. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  1544. /* Keep current crop information */
  1545. } else {
  1546. struct v4l2_rect *rect = &q_data_dst->rect;
  1547. rect->left = left_right >> 16 & 0xffff;
  1548. rect->top = top_bottom >> 16 & 0xffff;
  1549. rect->width = width - rect->left -
  1550. (left_right & 0xffff);
  1551. rect->height = height - rect->top -
  1552. (top_bottom & 0xffff);
  1553. }
  1554. } else {
  1555. /* no cropping */
  1556. }
  1557. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  1558. if (err_mb > 0)
  1559. v4l2_err(&dev->v4l2_dev,
  1560. "errors in %d macroblocks\n", err_mb);
  1561. if (dev->devtype->product == CODA_7541) {
  1562. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  1563. if (val == 0) {
  1564. /* not enough bitstream data */
  1565. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1566. "prescan failed: %d\n", val);
  1567. ctx->hold = true;
  1568. return;
  1569. }
  1570. }
  1571. ctx->frm_dis_flg = coda_read(dev,
  1572. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1573. /*
  1574. * The previous display frame was copied out by the rotator,
  1575. * now it can be overwritten again
  1576. */
  1577. if (ctx->display_idx >= 0 &&
  1578. ctx->display_idx < ctx->num_internal_frames) {
  1579. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  1580. coda_write(dev, ctx->frm_dis_flg,
  1581. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1582. }
  1583. /*
  1584. * The index of the last decoded frame, not necessarily in
  1585. * display order, and the index of the next display frame.
  1586. * The latter could have been decoded in a previous run.
  1587. */
  1588. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  1589. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  1590. if (decoded_idx == -1) {
  1591. /* no frame was decoded, but we might have a display frame */
  1592. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  1593. ctx->sequence_offset++;
  1594. else if (ctx->display_idx < 0)
  1595. ctx->hold = true;
  1596. } else if (decoded_idx == -2) {
  1597. /* no frame was decoded, we still return remaining buffers */
  1598. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  1599. v4l2_err(&dev->v4l2_dev,
  1600. "decoded frame index out of range: %d\n", decoded_idx);
  1601. } else {
  1602. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
  1603. val -= ctx->sequence_offset;
  1604. mutex_lock(&ctx->bitstream_mutex);
  1605. if (!list_empty(&ctx->buffer_meta_list)) {
  1606. meta = list_first_entry(&ctx->buffer_meta_list,
  1607. struct coda_buffer_meta, list);
  1608. list_del(&meta->list);
  1609. if (val != (meta->sequence & 0xffff)) {
  1610. v4l2_err(&dev->v4l2_dev,
  1611. "sequence number mismatch (%d(%d) != %d)\n",
  1612. val, ctx->sequence_offset,
  1613. meta->sequence);
  1614. }
  1615. ctx->frame_metas[decoded_idx] = *meta;
  1616. kfree(meta);
  1617. } else {
  1618. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  1619. memset(&ctx->frame_metas[decoded_idx], 0,
  1620. sizeof(struct coda_buffer_meta));
  1621. ctx->frame_metas[decoded_idx].sequence = val;
  1622. ctx->sequence_offset++;
  1623. }
  1624. mutex_unlock(&ctx->bitstream_mutex);
  1625. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  1626. if (val == 0)
  1627. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
  1628. else if (val == 1)
  1629. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
  1630. else
  1631. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
  1632. ctx->frame_errors[decoded_idx] = err_mb;
  1633. }
  1634. if (display_idx == -1) {
  1635. /*
  1636. * no more frames to be decoded, but there could still
  1637. * be rotator output to dequeue
  1638. */
  1639. ctx->hold = true;
  1640. } else if (display_idx == -3) {
  1641. /* possibly prescan failure */
  1642. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  1643. v4l2_err(&dev->v4l2_dev,
  1644. "presentation frame index out of range: %d\n",
  1645. display_idx);
  1646. }
  1647. /* If a frame was copied out, return it */
  1648. if (ctx->display_idx >= 0 &&
  1649. ctx->display_idx < ctx->num_internal_frames) {
  1650. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1651. dst_buf->v4l2_buf.sequence = ctx->osequence++;
  1652. dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1653. V4L2_BUF_FLAG_PFRAME |
  1654. V4L2_BUF_FLAG_BFRAME);
  1655. dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
  1656. meta = &ctx->frame_metas[ctx->display_idx];
  1657. dst_buf->v4l2_buf.timecode = meta->timecode;
  1658. dst_buf->v4l2_buf.timestamp = meta->timestamp;
  1659. switch (q_data_dst->fourcc) {
  1660. case V4L2_PIX_FMT_YUV420:
  1661. case V4L2_PIX_FMT_YVU420:
  1662. case V4L2_PIX_FMT_NV12:
  1663. default:
  1664. payload = width * height * 3 / 2;
  1665. break;
  1666. case V4L2_PIX_FMT_YUV422P:
  1667. payload = width * height * 2;
  1668. break;
  1669. }
  1670. vb2_set_plane_payload(dst_buf, 0, payload);
  1671. v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
  1672. VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  1673. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1674. "job finished: decoding frame (%d) (%s)\n",
  1675. dst_buf->v4l2_buf.sequence,
  1676. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1677. "KEYFRAME" : "PFRAME");
  1678. } else {
  1679. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1680. "job finished: no frame decoded\n");
  1681. }
  1682. /* The rotator will copy the current display frame next time */
  1683. ctx->display_idx = display_idx;
  1684. }
  1685. const struct coda_context_ops coda_bit_decode_ops = {
  1686. .queue_init = coda_decoder_queue_init,
  1687. .reqbufs = coda_decoder_reqbufs,
  1688. .start_streaming = coda_start_decoding,
  1689. .prepare_run = coda_prepare_decode,
  1690. .finish_run = coda_finish_decode,
  1691. .seq_end_work = coda_seq_end_work,
  1692. .release = coda_bit_release,
  1693. };
  1694. irqreturn_t coda_irq_handler(int irq, void *data)
  1695. {
  1696. struct coda_dev *dev = data;
  1697. struct coda_ctx *ctx;
  1698. /* read status register to attend the IRQ */
  1699. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1700. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1701. CODA_REG_BIT_INT_CLEAR);
  1702. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1703. if (ctx == NULL) {
  1704. v4l2_err(&dev->v4l2_dev,
  1705. "Instance released before the end of transaction\n");
  1706. mutex_unlock(&dev->coda_mutex);
  1707. return IRQ_HANDLED;
  1708. }
  1709. if (ctx->aborting) {
  1710. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1711. "task has been aborted\n");
  1712. }
  1713. if (coda_isbusy(ctx->dev)) {
  1714. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1715. "coda is still busy!!!!\n");
  1716. return IRQ_NONE;
  1717. }
  1718. complete(&ctx->completion);
  1719. return IRQ_HANDLED;
  1720. }