gpio-pca953x.c 22 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #include <asm/unaligned.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/acpi.h>
  23. #define PCA953X_INPUT 0
  24. #define PCA953X_OUTPUT 1
  25. #define PCA953X_INVERT 2
  26. #define PCA953X_DIRECTION 3
  27. #define REG_ADDR_AI 0x80
  28. #define PCA957X_IN 0
  29. #define PCA957X_INVRT 1
  30. #define PCA957X_BKEN 2
  31. #define PCA957X_PUPD 3
  32. #define PCA957X_CFG 4
  33. #define PCA957X_OUT 5
  34. #define PCA957X_MSK 6
  35. #define PCA957X_INTS 7
  36. #define PCAL953X_IN_LATCH 34
  37. #define PCAL953X_INT_MASK 37
  38. #define PCAL953X_INT_STAT 38
  39. #define PCA_GPIO_MASK 0x00FF
  40. #define PCA_INT 0x0100
  41. #define PCA_PCAL 0x0200
  42. #define PCA953X_TYPE 0x1000
  43. #define PCA957X_TYPE 0x2000
  44. #define PCA_TYPE_MASK 0xF000
  45. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  46. static const struct i2c_device_id pca953x_id[] = {
  47. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9536", 4 | PCA953X_TYPE, },
  51. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  53. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  54. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  55. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  56. { "pca9556", 8 | PCA953X_TYPE, },
  57. { "pca9557", 8 | PCA953X_TYPE, },
  58. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  59. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  60. { "pca9698", 40 | PCA953X_TYPE, },
  61. { "max7310", 8 | PCA953X_TYPE, },
  62. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  63. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  64. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  65. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  66. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  67. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  68. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  69. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  70. { "xra1202", 8 | PCA953X_TYPE },
  71. { }
  72. };
  73. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  74. static const struct acpi_device_id pca953x_acpi_ids[] = {
  75. { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  76. { }
  77. };
  78. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  79. #define MAX_BANK 5
  80. #define BANK_SZ 8
  81. #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
  82. struct pca953x_chip {
  83. unsigned gpio_start;
  84. u8 reg_output[MAX_BANK];
  85. u8 reg_direction[MAX_BANK];
  86. struct mutex i2c_lock;
  87. #ifdef CONFIG_GPIO_PCA953X_IRQ
  88. struct mutex irq_lock;
  89. u8 irq_mask[MAX_BANK];
  90. u8 irq_stat[MAX_BANK];
  91. u8 irq_trig_raise[MAX_BANK];
  92. u8 irq_trig_fall[MAX_BANK];
  93. #endif
  94. struct i2c_client *client;
  95. struct gpio_chip gpio_chip;
  96. const char *const *names;
  97. int chip_type;
  98. unsigned long driver_data;
  99. };
  100. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  101. int off)
  102. {
  103. int ret;
  104. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  105. int offset = off / BANK_SZ;
  106. ret = i2c_smbus_read_byte_data(chip->client,
  107. (reg << bank_shift) + offset);
  108. *val = ret;
  109. if (ret < 0) {
  110. dev_err(&chip->client->dev, "failed reading register\n");
  111. return ret;
  112. }
  113. return 0;
  114. }
  115. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  116. int off)
  117. {
  118. int ret = 0;
  119. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  120. int offset = off / BANK_SZ;
  121. ret = i2c_smbus_write_byte_data(chip->client,
  122. (reg << bank_shift) + offset, val);
  123. if (ret < 0) {
  124. dev_err(&chip->client->dev, "failed writing register\n");
  125. return ret;
  126. }
  127. return 0;
  128. }
  129. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  130. {
  131. int ret = 0;
  132. if (chip->gpio_chip.ngpio <= 8)
  133. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  134. else if (chip->gpio_chip.ngpio >= 24) {
  135. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  136. ret = i2c_smbus_write_i2c_block_data(chip->client,
  137. (reg << bank_shift) | REG_ADDR_AI,
  138. NBANK(chip), val);
  139. } else {
  140. switch (chip->chip_type) {
  141. case PCA953X_TYPE:
  142. ret = i2c_smbus_write_word_data(chip->client,
  143. reg << 1, cpu_to_le16(get_unaligned((u16 *)val)));
  144. break;
  145. case PCA957X_TYPE:
  146. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  147. val[0]);
  148. if (ret < 0)
  149. break;
  150. ret = i2c_smbus_write_byte_data(chip->client,
  151. (reg << 1) + 1,
  152. val[1]);
  153. break;
  154. }
  155. }
  156. if (ret < 0) {
  157. dev_err(&chip->client->dev, "failed writing register\n");
  158. return ret;
  159. }
  160. return 0;
  161. }
  162. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  163. {
  164. int ret;
  165. if (chip->gpio_chip.ngpio <= 8) {
  166. ret = i2c_smbus_read_byte_data(chip->client, reg);
  167. *val = ret;
  168. } else if (chip->gpio_chip.ngpio >= 24) {
  169. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  170. ret = i2c_smbus_read_i2c_block_data(chip->client,
  171. (reg << bank_shift) | REG_ADDR_AI,
  172. NBANK(chip), val);
  173. } else {
  174. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  175. val[0] = (u16)ret & 0xFF;
  176. val[1] = (u16)ret >> 8;
  177. }
  178. if (ret < 0) {
  179. dev_err(&chip->client->dev, "failed reading register\n");
  180. return ret;
  181. }
  182. return 0;
  183. }
  184. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  185. {
  186. struct pca953x_chip *chip = gpiochip_get_data(gc);
  187. u8 reg_val;
  188. int ret, offset = 0;
  189. mutex_lock(&chip->i2c_lock);
  190. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  191. switch (chip->chip_type) {
  192. case PCA953X_TYPE:
  193. offset = PCA953X_DIRECTION;
  194. break;
  195. case PCA957X_TYPE:
  196. offset = PCA957X_CFG;
  197. break;
  198. }
  199. ret = pca953x_write_single(chip, offset, reg_val, off);
  200. if (ret)
  201. goto exit;
  202. chip->reg_direction[off / BANK_SZ] = reg_val;
  203. ret = 0;
  204. exit:
  205. mutex_unlock(&chip->i2c_lock);
  206. return ret;
  207. }
  208. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  209. unsigned off, int val)
  210. {
  211. struct pca953x_chip *chip = gpiochip_get_data(gc);
  212. u8 reg_val;
  213. int ret, offset = 0;
  214. mutex_lock(&chip->i2c_lock);
  215. /* set output level */
  216. if (val)
  217. reg_val = chip->reg_output[off / BANK_SZ]
  218. | (1u << (off % BANK_SZ));
  219. else
  220. reg_val = chip->reg_output[off / BANK_SZ]
  221. & ~(1u << (off % BANK_SZ));
  222. switch (chip->chip_type) {
  223. case PCA953X_TYPE:
  224. offset = PCA953X_OUTPUT;
  225. break;
  226. case PCA957X_TYPE:
  227. offset = PCA957X_OUT;
  228. break;
  229. }
  230. ret = pca953x_write_single(chip, offset, reg_val, off);
  231. if (ret)
  232. goto exit;
  233. chip->reg_output[off / BANK_SZ] = reg_val;
  234. /* then direction */
  235. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  236. switch (chip->chip_type) {
  237. case PCA953X_TYPE:
  238. offset = PCA953X_DIRECTION;
  239. break;
  240. case PCA957X_TYPE:
  241. offset = PCA957X_CFG;
  242. break;
  243. }
  244. ret = pca953x_write_single(chip, offset, reg_val, off);
  245. if (ret)
  246. goto exit;
  247. chip->reg_direction[off / BANK_SZ] = reg_val;
  248. ret = 0;
  249. exit:
  250. mutex_unlock(&chip->i2c_lock);
  251. return ret;
  252. }
  253. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  254. {
  255. struct pca953x_chip *chip = gpiochip_get_data(gc);
  256. u32 reg_val;
  257. int ret, offset = 0;
  258. mutex_lock(&chip->i2c_lock);
  259. switch (chip->chip_type) {
  260. case PCA953X_TYPE:
  261. offset = PCA953X_INPUT;
  262. break;
  263. case PCA957X_TYPE:
  264. offset = PCA957X_IN;
  265. break;
  266. }
  267. ret = pca953x_read_single(chip, offset, &reg_val, off);
  268. mutex_unlock(&chip->i2c_lock);
  269. if (ret < 0) {
  270. /* NOTE: diagnostic already emitted; that's all we should
  271. * do unless gpio_*_value_cansleep() calls become different
  272. * from their nonsleeping siblings (and report faults).
  273. */
  274. return 0;
  275. }
  276. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  277. }
  278. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  279. {
  280. struct pca953x_chip *chip = gpiochip_get_data(gc);
  281. u8 reg_val;
  282. int ret, offset = 0;
  283. mutex_lock(&chip->i2c_lock);
  284. if (val)
  285. reg_val = chip->reg_output[off / BANK_SZ]
  286. | (1u << (off % BANK_SZ));
  287. else
  288. reg_val = chip->reg_output[off / BANK_SZ]
  289. & ~(1u << (off % BANK_SZ));
  290. switch (chip->chip_type) {
  291. case PCA953X_TYPE:
  292. offset = PCA953X_OUTPUT;
  293. break;
  294. case PCA957X_TYPE:
  295. offset = PCA957X_OUT;
  296. break;
  297. }
  298. ret = pca953x_write_single(chip, offset, reg_val, off);
  299. if (ret)
  300. goto exit;
  301. chip->reg_output[off / BANK_SZ] = reg_val;
  302. exit:
  303. mutex_unlock(&chip->i2c_lock);
  304. }
  305. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  306. unsigned long *mask, unsigned long *bits)
  307. {
  308. struct pca953x_chip *chip = gpiochip_get_data(gc);
  309. u8 reg_val[MAX_BANK];
  310. int ret, offset = 0;
  311. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  312. int bank;
  313. switch (chip->chip_type) {
  314. case PCA953X_TYPE:
  315. offset = PCA953X_OUTPUT;
  316. break;
  317. case PCA957X_TYPE:
  318. offset = PCA957X_OUT;
  319. break;
  320. }
  321. memcpy(reg_val, chip->reg_output, NBANK(chip));
  322. mutex_lock(&chip->i2c_lock);
  323. for(bank=0; bank<NBANK(chip); bank++) {
  324. unsigned bankmask = mask[bank / sizeof(*mask)] >>
  325. ((bank % sizeof(*mask)) * 8);
  326. if(bankmask) {
  327. unsigned bankval = bits[bank / sizeof(*bits)] >>
  328. ((bank % sizeof(*bits)) * 8);
  329. reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
  330. }
  331. }
  332. ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
  333. if (ret)
  334. goto exit;
  335. memcpy(chip->reg_output, reg_val, NBANK(chip));
  336. exit:
  337. mutex_unlock(&chip->i2c_lock);
  338. }
  339. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  340. {
  341. struct gpio_chip *gc;
  342. gc = &chip->gpio_chip;
  343. gc->direction_input = pca953x_gpio_direction_input;
  344. gc->direction_output = pca953x_gpio_direction_output;
  345. gc->get = pca953x_gpio_get_value;
  346. gc->set = pca953x_gpio_set_value;
  347. gc->set_multiple = pca953x_gpio_set_multiple;
  348. gc->can_sleep = true;
  349. gc->base = chip->gpio_start;
  350. gc->ngpio = gpios;
  351. gc->label = chip->client->name;
  352. gc->parent = &chip->client->dev;
  353. gc->owner = THIS_MODULE;
  354. gc->names = chip->names;
  355. }
  356. #ifdef CONFIG_GPIO_PCA953X_IRQ
  357. static void pca953x_irq_mask(struct irq_data *d)
  358. {
  359. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  360. struct pca953x_chip *chip = gpiochip_get_data(gc);
  361. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  362. }
  363. static void pca953x_irq_unmask(struct irq_data *d)
  364. {
  365. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  366. struct pca953x_chip *chip = gpiochip_get_data(gc);
  367. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  368. }
  369. static void pca953x_irq_bus_lock(struct irq_data *d)
  370. {
  371. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  372. struct pca953x_chip *chip = gpiochip_get_data(gc);
  373. mutex_lock(&chip->irq_lock);
  374. }
  375. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  376. {
  377. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  378. struct pca953x_chip *chip = gpiochip_get_data(gc);
  379. u8 new_irqs;
  380. int level, i;
  381. u8 invert_irq_mask[MAX_BANK];
  382. if (chip->driver_data & PCA_PCAL) {
  383. /* Enable latch on interrupt-enabled inputs */
  384. pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
  385. for (i = 0; i < NBANK(chip); i++)
  386. invert_irq_mask[i] = ~chip->irq_mask[i];
  387. /* Unmask enabled interrupts */
  388. pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
  389. }
  390. /* Look for any newly setup interrupt */
  391. for (i = 0; i < NBANK(chip); i++) {
  392. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  393. new_irqs &= ~chip->reg_direction[i];
  394. while (new_irqs) {
  395. level = __ffs(new_irqs);
  396. pca953x_gpio_direction_input(&chip->gpio_chip,
  397. level + (BANK_SZ * i));
  398. new_irqs &= ~(1 << level);
  399. }
  400. }
  401. mutex_unlock(&chip->irq_lock);
  402. }
  403. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  404. {
  405. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  406. struct pca953x_chip *chip = gpiochip_get_data(gc);
  407. int bank_nb = d->hwirq / BANK_SZ;
  408. u8 mask = 1 << (d->hwirq % BANK_SZ);
  409. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  410. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  411. d->irq, type);
  412. return -EINVAL;
  413. }
  414. if (type & IRQ_TYPE_EDGE_FALLING)
  415. chip->irq_trig_fall[bank_nb] |= mask;
  416. else
  417. chip->irq_trig_fall[bank_nb] &= ~mask;
  418. if (type & IRQ_TYPE_EDGE_RISING)
  419. chip->irq_trig_raise[bank_nb] |= mask;
  420. else
  421. chip->irq_trig_raise[bank_nb] &= ~mask;
  422. return 0;
  423. }
  424. static struct irq_chip pca953x_irq_chip = {
  425. .name = "pca953x",
  426. .irq_mask = pca953x_irq_mask,
  427. .irq_unmask = pca953x_irq_unmask,
  428. .irq_bus_lock = pca953x_irq_bus_lock,
  429. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  430. .irq_set_type = pca953x_irq_set_type,
  431. };
  432. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  433. {
  434. u8 cur_stat[MAX_BANK];
  435. u8 old_stat[MAX_BANK];
  436. bool pending_seen = false;
  437. bool trigger_seen = false;
  438. u8 trigger[MAX_BANK];
  439. int ret, i, offset = 0;
  440. if (chip->driver_data & PCA_PCAL) {
  441. /* Read the current interrupt status from the device */
  442. ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
  443. if (ret)
  444. return false;
  445. /* Check latched inputs and clear interrupt status */
  446. ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
  447. if (ret)
  448. return false;
  449. for (i = 0; i < NBANK(chip); i++) {
  450. /* Apply filter for rising/falling edge selection */
  451. pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
  452. (cur_stat[i] & chip->irq_trig_raise[i]);
  453. pending[i] &= trigger[i];
  454. if (pending[i])
  455. pending_seen = true;
  456. }
  457. return pending_seen;
  458. }
  459. switch (chip->chip_type) {
  460. case PCA953X_TYPE:
  461. offset = PCA953X_INPUT;
  462. break;
  463. case PCA957X_TYPE:
  464. offset = PCA957X_IN;
  465. break;
  466. }
  467. ret = pca953x_read_regs(chip, offset, cur_stat);
  468. if (ret)
  469. return false;
  470. /* Remove output pins from the equation */
  471. for (i = 0; i < NBANK(chip); i++)
  472. cur_stat[i] &= chip->reg_direction[i];
  473. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  474. for (i = 0; i < NBANK(chip); i++) {
  475. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  476. if (trigger[i])
  477. trigger_seen = true;
  478. }
  479. if (!trigger_seen)
  480. return false;
  481. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  482. for (i = 0; i < NBANK(chip); i++) {
  483. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  484. (cur_stat[i] & chip->irq_trig_raise[i]);
  485. pending[i] &= trigger[i];
  486. if (pending[i])
  487. pending_seen = true;
  488. }
  489. return pending_seen;
  490. }
  491. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  492. {
  493. struct pca953x_chip *chip = devid;
  494. u8 pending[MAX_BANK];
  495. u8 level;
  496. unsigned nhandled = 0;
  497. int i;
  498. if (!pca953x_irq_pending(chip, pending))
  499. return IRQ_NONE;
  500. for (i = 0; i < NBANK(chip); i++) {
  501. while (pending[i]) {
  502. level = __ffs(pending[i]);
  503. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  504. level + (BANK_SZ * i)));
  505. pending[i] &= ~(1 << level);
  506. nhandled++;
  507. }
  508. }
  509. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  510. }
  511. static int pca953x_irq_setup(struct pca953x_chip *chip,
  512. int irq_base)
  513. {
  514. struct i2c_client *client = chip->client;
  515. int ret, i, offset = 0;
  516. if (client->irq && irq_base != -1
  517. && (chip->driver_data & PCA_INT)) {
  518. switch (chip->chip_type) {
  519. case PCA953X_TYPE:
  520. offset = PCA953X_INPUT;
  521. break;
  522. case PCA957X_TYPE:
  523. offset = PCA957X_IN;
  524. break;
  525. }
  526. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  527. if (ret)
  528. return ret;
  529. /*
  530. * There is no way to know which GPIO line generated the
  531. * interrupt. We have to rely on the previous read for
  532. * this purpose.
  533. */
  534. for (i = 0; i < NBANK(chip); i++)
  535. chip->irq_stat[i] &= chip->reg_direction[i];
  536. mutex_init(&chip->irq_lock);
  537. ret = devm_request_threaded_irq(&client->dev,
  538. client->irq,
  539. NULL,
  540. pca953x_irq_handler,
  541. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  542. IRQF_SHARED,
  543. dev_name(&client->dev), chip);
  544. if (ret) {
  545. dev_err(&client->dev, "failed to request irq %d\n",
  546. client->irq);
  547. return ret;
  548. }
  549. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  550. &pca953x_irq_chip,
  551. irq_base,
  552. handle_simple_irq,
  553. IRQ_TYPE_NONE);
  554. if (ret) {
  555. dev_err(&client->dev,
  556. "could not connect irqchip to gpiochip\n");
  557. return ret;
  558. }
  559. gpiochip_set_chained_irqchip(&chip->gpio_chip,
  560. &pca953x_irq_chip,
  561. client->irq, NULL);
  562. }
  563. return 0;
  564. }
  565. #else /* CONFIG_GPIO_PCA953X_IRQ */
  566. static int pca953x_irq_setup(struct pca953x_chip *chip,
  567. int irq_base)
  568. {
  569. struct i2c_client *client = chip->client;
  570. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  571. dev_warn(&client->dev, "interrupt support not compiled in\n");
  572. return 0;
  573. }
  574. #endif
  575. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  576. {
  577. int ret;
  578. u8 val[MAX_BANK];
  579. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  580. if (ret)
  581. goto out;
  582. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  583. chip->reg_direction);
  584. if (ret)
  585. goto out;
  586. /* set platform specific polarity inversion */
  587. if (invert)
  588. memset(val, 0xFF, NBANK(chip));
  589. else
  590. memset(val, 0, NBANK(chip));
  591. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  592. out:
  593. return ret;
  594. }
  595. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  596. {
  597. int ret;
  598. u8 val[MAX_BANK];
  599. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  600. if (ret)
  601. goto out;
  602. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  603. if (ret)
  604. goto out;
  605. /* set platform specific polarity inversion */
  606. if (invert)
  607. memset(val, 0xFF, NBANK(chip));
  608. else
  609. memset(val, 0, NBANK(chip));
  610. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  611. if (ret)
  612. goto out;
  613. /* To enable register 6, 7 to control pull up and pull down */
  614. memset(val, 0x02, NBANK(chip));
  615. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  616. if (ret)
  617. goto out;
  618. return 0;
  619. out:
  620. return ret;
  621. }
  622. static const struct of_device_id pca953x_dt_ids[];
  623. static int pca953x_probe(struct i2c_client *client,
  624. const struct i2c_device_id *id)
  625. {
  626. struct pca953x_platform_data *pdata;
  627. struct pca953x_chip *chip;
  628. int irq_base = 0;
  629. int ret;
  630. u32 invert = 0;
  631. chip = devm_kzalloc(&client->dev,
  632. sizeof(struct pca953x_chip), GFP_KERNEL);
  633. if (chip == NULL)
  634. return -ENOMEM;
  635. pdata = dev_get_platdata(&client->dev);
  636. if (pdata) {
  637. irq_base = pdata->irq_base;
  638. chip->gpio_start = pdata->gpio_base;
  639. invert = pdata->invert;
  640. chip->names = pdata->names;
  641. } else {
  642. chip->gpio_start = -1;
  643. irq_base = 0;
  644. }
  645. chip->client = client;
  646. if (id) {
  647. chip->driver_data = id->driver_data;
  648. } else {
  649. const struct acpi_device_id *id;
  650. const struct of_device_id *match;
  651. match = of_match_device(pca953x_dt_ids, &client->dev);
  652. if (match) {
  653. chip->driver_data = (int)(uintptr_t)match->data;
  654. } else {
  655. id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  656. if (!id)
  657. return -ENODEV;
  658. chip->driver_data = id->driver_data;
  659. }
  660. }
  661. chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
  662. mutex_init(&chip->i2c_lock);
  663. /* initialize cached registers from their original values.
  664. * we can't share this chip with another i2c master.
  665. */
  666. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  667. if (chip->chip_type == PCA953X_TYPE)
  668. ret = device_pca953x_init(chip, invert);
  669. else
  670. ret = device_pca957x_init(chip, invert);
  671. if (ret)
  672. return ret;
  673. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  674. if (ret)
  675. return ret;
  676. ret = pca953x_irq_setup(chip, irq_base);
  677. if (ret)
  678. return ret;
  679. if (pdata && pdata->setup) {
  680. ret = pdata->setup(client, chip->gpio_chip.base,
  681. chip->gpio_chip.ngpio, pdata->context);
  682. if (ret < 0)
  683. dev_warn(&client->dev, "setup failed, %d\n", ret);
  684. }
  685. i2c_set_clientdata(client, chip);
  686. return 0;
  687. }
  688. static int pca953x_remove(struct i2c_client *client)
  689. {
  690. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  691. struct pca953x_chip *chip = i2c_get_clientdata(client);
  692. int ret = 0;
  693. if (pdata && pdata->teardown) {
  694. ret = pdata->teardown(client, chip->gpio_chip.base,
  695. chip->gpio_chip.ngpio, pdata->context);
  696. if (ret < 0) {
  697. dev_err(&client->dev, "%s failed, %d\n",
  698. "teardown", ret);
  699. return ret;
  700. }
  701. }
  702. return 0;
  703. }
  704. /* convenience to stop overlong match-table lines */
  705. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  706. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  707. static const struct of_device_id pca953x_dt_ids[] = {
  708. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  709. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  710. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  711. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  712. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  713. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  714. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  715. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  716. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  717. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  718. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  719. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  720. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  721. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  722. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  723. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  724. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  725. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  726. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  727. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  728. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  729. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  730. { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
  731. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  732. { }
  733. };
  734. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  735. static struct i2c_driver pca953x_driver = {
  736. .driver = {
  737. .name = "pca953x",
  738. .of_match_table = pca953x_dt_ids,
  739. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  740. },
  741. .probe = pca953x_probe,
  742. .remove = pca953x_remove,
  743. .id_table = pca953x_id,
  744. };
  745. static int __init pca953x_init(void)
  746. {
  747. return i2c_add_driver(&pca953x_driver);
  748. }
  749. /* register after i2c postcore initcall and before
  750. * subsys initcalls that may rely on these GPIOs
  751. */
  752. subsys_initcall(pca953x_init);
  753. static void __exit pca953x_exit(void)
  754. {
  755. i2c_del_driver(&pca953x_driver);
  756. }
  757. module_exit(pca953x_exit);
  758. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  759. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  760. MODULE_LICENSE("GPL");