imx6qdl-nitrogen6_max.dtsi 20 KB

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  1. /*
  2. * Copyright 2015 Boundary Devices, Inc.
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This file is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * version 2 as published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * Or, alternatively
  19. *
  20. * b) Permission is hereby granted, free of charge, to any person
  21. * obtaining a copy of this software and associated documentation
  22. * files (the "Software"), to deal in the Software without
  23. * restriction, including without limitation the rights to use
  24. * copy, modify, merge, publish, distribute, sublicense, and/or
  25. * sell copies of the Software, and to permit persons to whom the
  26. * Software is furnished to do so, subject to the following
  27. * conditions:
  28. *
  29. * The above copyright notice and this permission notice shall be
  30. * included in all copies or substantial portions of the Software.
  31. *
  32. * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  33. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  37. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39. * OTHER DEALINGS IN THE SOFTWARE.
  40. */
  41. #include <dt-bindings/gpio/gpio.h>
  42. #include <dt-bindings/input/input.h>
  43. / {
  44. chosen {
  45. stdout-path = &uart2;
  46. };
  47. memory {
  48. reg = <0x10000000 0xF0000000>;
  49. };
  50. regulators {
  51. compatible = "simple-bus";
  52. #address-cells = <1>;
  53. #size-cells = <0>;
  54. reg_1p8v: regulator@0 {
  55. compatible = "regulator-fixed";
  56. reg = <0>;
  57. regulator-name = "1P8V";
  58. regulator-min-microvolt = <1800000>;
  59. regulator-max-microvolt = <1800000>;
  60. regulator-always-on;
  61. };
  62. reg_2p5v: regulator@1 {
  63. compatible = "regulator-fixed";
  64. reg = <1>;
  65. regulator-name = "2P5V";
  66. regulator-min-microvolt = <2500000>;
  67. regulator-max-microvolt = <2500000>;
  68. regulator-always-on;
  69. };
  70. reg_3p3v: regulator@2 {
  71. compatible = "regulator-fixed";
  72. reg = <2>;
  73. regulator-name = "3P3V";
  74. regulator-min-microvolt = <3300000>;
  75. regulator-max-microvolt = <3300000>;
  76. regulator-always-on;
  77. };
  78. reg_usb_otg_vbus: regulator@3 {
  79. compatible = "regulator-fixed";
  80. reg = <3>;
  81. regulator-name = "usb_otg_vbus";
  82. regulator-min-microvolt = <5000000>;
  83. regulator-max-microvolt = <5000000>;
  84. gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  85. enable-active-high;
  86. };
  87. reg_usb_h1_vbus: regulator@4 {
  88. compatible = "regulator-fixed";
  89. reg = <4>;
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&pinctrl_usbh1>;
  92. regulator-name = "usb_h1_vbus";
  93. regulator-min-microvolt = <3300000>;
  94. regulator-max-microvolt = <3300000>;
  95. gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  96. enable-active-high;
  97. };
  98. reg_wlan_vmmc: regulator@5 {
  99. compatible = "regulator-fixed";
  100. reg = <5>;
  101. pinctrl-names = "default";
  102. pinctrl-0 = <&pinctrl_wlan_vmmc>;
  103. regulator-name = "reg_wlan_vmmc";
  104. regulator-min-microvolt = <3300000>;
  105. regulator-max-microvolt = <3300000>;
  106. gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
  107. startup-delay-us = <70000>;
  108. enable-active-high;
  109. };
  110. reg_can_xcvr: regulator@6 {
  111. compatible = "regulator-fixed";
  112. reg = <6>;
  113. regulator-name = "CAN XCVR";
  114. regulator-min-microvolt = <3300000>;
  115. regulator-max-microvolt = <3300000>;
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&pinctrl_can_xcvr>;
  118. gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
  119. };
  120. };
  121. gpio-keys {
  122. compatible = "gpio-keys";
  123. pinctrl-names = "default";
  124. pinctrl-0 = <&pinctrl_gpio_keys>;
  125. power {
  126. label = "Power Button";
  127. gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
  128. linux,code = <KEY_POWER>;
  129. wakeup-source;
  130. };
  131. menu {
  132. label = "Menu";
  133. gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  134. linux,code = <KEY_MENU>;
  135. };
  136. home {
  137. label = "Home";
  138. gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  139. linux,code = <KEY_HOME>;
  140. };
  141. back {
  142. label = "Back";
  143. gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  144. linux,code = <KEY_BACK>;
  145. };
  146. volume-up {
  147. label = "Volume Up";
  148. gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
  149. linux,code = <KEY_VOLUMEUP>;
  150. };
  151. volume-down {
  152. label = "Volume Down";
  153. gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
  154. linux,code = <KEY_VOLUMEDOWN>;
  155. };
  156. };
  157. i2cmux@2 {
  158. compatible = "i2c-mux-gpio";
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&pinctrl_i2c2mux>;
  161. #address-cells = <1>;
  162. #size-cells = <0>;
  163. mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH
  164. &gpio4 15 GPIO_ACTIVE_HIGH>;
  165. i2c-parent = <&i2c2>;
  166. idle-state = <0>;
  167. i2c2@1 {
  168. reg = <1>;
  169. #address-cells = <1>;
  170. #size-cells = <0>;
  171. };
  172. i2c2@2 {
  173. reg = <2>;
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. };
  177. };
  178. i2cmux@3 {
  179. compatible = "i2c-mux-gpio";
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&pinctrl_i2c3mux>;
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
  185. i2c-parent = <&i2c3>;
  186. idle-state = <0>;
  187. i2c3@1 {
  188. reg = <1>;
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. };
  192. };
  193. leds {
  194. compatible = "gpio-leds";
  195. speaker-enable {
  196. gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  197. retain-state-suspended;
  198. default-state = "off";
  199. };
  200. ttymxc4-rs232 {
  201. gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
  202. retain-state-suspended;
  203. default-state = "on";
  204. };
  205. };
  206. backlight_lcd: backlight-lcd {
  207. compatible = "pwm-backlight";
  208. pwms = <&pwm1 0 5000000>;
  209. brightness-levels = <0 4 8 16 32 64 128 255>;
  210. default-brightness-level = <7>;
  211. power-supply = <&reg_3p3v>;
  212. status = "okay";
  213. };
  214. backlight_lvds0: backlight-lvds0 {
  215. compatible = "pwm-backlight";
  216. pwms = <&pwm4 0 5000000>;
  217. brightness-levels = <0 4 8 16 32 64 128 255>;
  218. default-brightness-level = <7>;
  219. power-supply = <&reg_3p3v>;
  220. status = "okay";
  221. };
  222. backlight_lvds1: backlight-lvds1 {
  223. compatible = "pwm-backlight";
  224. pwms = <&pwm2 0 5000000>;
  225. brightness-levels = <0 4 8 16 32 64 128 255>;
  226. default-brightness-level = <7>;
  227. power-supply = <&reg_3p3v>;
  228. status = "okay";
  229. };
  230. lcd_display: display@di0 {
  231. compatible = "fsl,imx-parallel-display";
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. interface-pix-fmt = "bgr666";
  235. pinctrl-names = "default";
  236. pinctrl-0 = <&pinctrl_j15>;
  237. status = "okay";
  238. port@0 {
  239. reg = <0>;
  240. lcd_display_in: endpoint {
  241. remote-endpoint = <&ipu1_di0_disp0>;
  242. };
  243. };
  244. port@1 {
  245. reg = <1>;
  246. lcd_display_out: endpoint {
  247. remote-endpoint = <&lcd_panel_in>;
  248. };
  249. };
  250. };
  251. panel-lcd {
  252. compatible = "okaya,rs800480t-7x0gp";
  253. backlight = <&backlight_lcd>;
  254. port {
  255. lcd_panel_in: endpoint {
  256. remote-endpoint = <&lcd_display_out>;
  257. };
  258. };
  259. };
  260. panel-lvds0 {
  261. compatible = "hannstar,hsd100pxn1";
  262. backlight = <&backlight_lvds0>;
  263. port {
  264. panel_in_lvds0: endpoint {
  265. remote-endpoint = <&lvds0_out>;
  266. };
  267. };
  268. };
  269. panel-lvds1 {
  270. compatible = "hannstar,hsd100pxn1";
  271. backlight = <&backlight_lvds1>;
  272. port {
  273. panel_in_lvds1: endpoint {
  274. remote-endpoint = <&lvds1_out>;
  275. };
  276. };
  277. };
  278. sound {
  279. compatible = "fsl,imx6q-nitrogen6_max-sgtl5000",
  280. "fsl,imx-audio-sgtl5000";
  281. model = "imx6q-nitrogen6_max-sgtl5000";
  282. ssi-controller = <&ssi1>;
  283. audio-codec = <&codec>;
  284. audio-routing =
  285. "MIC_IN", "Mic Jack",
  286. "Mic Jack", "Mic Bias",
  287. "Headphone Jack", "HP_OUT";
  288. mux-int-port = <1>;
  289. mux-ext-port = <3>;
  290. };
  291. };
  292. &audmux {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_audmux>;
  295. status = "okay";
  296. };
  297. &can1 {
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_can1>;
  300. xceiver-supply = <&reg_can_xcvr>;
  301. status = "okay";
  302. };
  303. &clks {
  304. assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  305. <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  306. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  307. <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  308. };
  309. &ecspi1 {
  310. fsl,spi-num-chipselects = <1>;
  311. cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  312. pinctrl-names = "default";
  313. pinctrl-0 = <&pinctrl_ecspi1>;
  314. status = "okay";
  315. flash: m25p80@0 {
  316. compatible = "microchip,sst25vf016b";
  317. spi-max-frequency = <20000000>;
  318. reg = <0>;
  319. };
  320. };
  321. &fec {
  322. pinctrl-names = "default";
  323. pinctrl-0 = <&pinctrl_enet>;
  324. phy-mode = "rgmii";
  325. phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
  326. txen-skew-ps = <0>;
  327. txc-skew-ps = <3000>;
  328. rxdv-skew-ps = <0>;
  329. rxc-skew-ps = <3000>;
  330. rxd0-skew-ps = <0>;
  331. rxd1-skew-ps = <0>;
  332. rxd2-skew-ps = <0>;
  333. rxd3-skew-ps = <0>;
  334. txd0-skew-ps = <0>;
  335. txd1-skew-ps = <0>;
  336. txd2-skew-ps = <0>;
  337. txd3-skew-ps = <0>;
  338. interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  339. <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  340. fsl,err006687-workaround-present;
  341. status = "okay";
  342. };
  343. &hdmi {
  344. ddc-i2c-bus = <&i2c2>;
  345. status = "okay";
  346. };
  347. &i2c1 {
  348. clock-frequency = <100000>;
  349. pinctrl-names = "default";
  350. pinctrl-0 = <&pinctrl_i2c1>;
  351. status = "okay";
  352. codec: sgtl5000@0a {
  353. compatible = "fsl,sgtl5000";
  354. pinctrl-names = "default";
  355. pinctrl-0 = <&pinctrl_sgtl5000>;
  356. reg = <0x0a>;
  357. clocks = <&clks IMX6QDL_CLK_CKO>;
  358. VDDA-supply = <&reg_2p5v>;
  359. VDDIO-supply = <&reg_3p3v>;
  360. };
  361. rtc: rtc@68 {
  362. compatible = "st,rv4162";
  363. pinctrl-names = "default";
  364. pinctrl-0 = <&pinctrl_rv4162>;
  365. reg = <0x68>;
  366. interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>;
  367. };
  368. };
  369. &i2c2 {
  370. clock-frequency = <100000>;
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_i2c2>;
  373. status = "okay";
  374. };
  375. &i2c3 {
  376. clock-frequency = <100000>;
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_i2c3>;
  379. status = "okay";
  380. touchscreen@04 {
  381. compatible = "eeti,egalax_ts";
  382. reg = <0x04>;
  383. interrupt-parent = <&gpio1>;
  384. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  385. wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  386. };
  387. touchscreen@38 {
  388. compatible = "edt,edt-ft5x06";
  389. reg = <0x38>;
  390. interrupt-parent = <&gpio1>;
  391. interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  392. };
  393. };
  394. &iomuxc {
  395. imx6q-nitrogen6-max {
  396. pinctrl_audmux: audmuxgrp {
  397. fsl,pins = <
  398. MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  399. MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  400. MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  401. MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  402. >;
  403. };
  404. pinctrl_can1: can1grp {
  405. fsl,pins = <
  406. MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
  407. MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
  408. >;
  409. };
  410. pinctrl_can_xcvr: can-xcvrgrp {
  411. fsl,pins = <
  412. /* Flexcan XCVR enable */
  413. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  414. >;
  415. };
  416. pinctrl_ecspi1: ecspi1grp {
  417. fsl,pins = <
  418. MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  419. MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  420. MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  421. MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
  422. >;
  423. };
  424. pinctrl_enet: enetgrp {
  425. fsl,pins = <
  426. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
  427. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
  428. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
  429. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
  430. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
  431. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
  432. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
  433. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
  434. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
  435. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  436. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  437. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  438. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  439. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  440. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  441. /* Phy reset */
  442. MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
  443. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
  444. MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
  445. >;
  446. };
  447. pinctrl_gpio_keys: gpio-keysgrp {
  448. fsl,pins = <
  449. /* Power Button */
  450. MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
  451. /* Menu Button */
  452. MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
  453. /* Home Button */
  454. MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
  455. /* Back Button */
  456. MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
  457. /* Volume Up Button */
  458. MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
  459. /* Volume Down Button */
  460. MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
  461. >;
  462. };
  463. pinctrl_i2c1: i2c1grp {
  464. fsl,pins = <
  465. MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  466. MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  467. >;
  468. };
  469. pinctrl_i2c2: i2c2grp {
  470. fsl,pins = <
  471. MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  472. MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  473. >;
  474. };
  475. pinctrl_i2c2mux: i2c2muxgrp {
  476. fsl,pins = <
  477. /* ov5642 camera i2c enable */
  478. MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0
  479. /* ov5640_mipi camera i2c enable */
  480. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
  481. >;
  482. };
  483. pinctrl_i2c3: i2c3grp {
  484. fsl,pins = <
  485. MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  486. MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
  487. MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
  488. >;
  489. };
  490. pinctrl_i2c3mux: i2c3muxgrp {
  491. fsl,pins = <
  492. /* PCIe I2C enable */
  493. MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0
  494. >;
  495. };
  496. pinctrl_j15: j15grp {
  497. fsl,pins = <
  498. MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
  499. MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
  500. MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
  501. MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
  502. MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
  503. MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
  504. MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
  505. MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
  506. MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
  507. MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
  508. MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
  509. MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
  510. MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
  511. MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
  512. MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
  513. MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
  514. MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
  515. MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
  516. MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
  517. MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
  518. MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
  519. MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
  520. MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
  521. MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
  522. MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
  523. MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
  524. MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
  525. MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
  526. >;
  527. };
  528. pinctrl_pcie: pciegrp {
  529. fsl,pins = <
  530. /* PCIe reset */
  531. MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0
  532. >;
  533. };
  534. pinctrl_pwm1: pwm1grp {
  535. fsl,pins = <
  536. MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
  537. >;
  538. };
  539. pinctrl_pwm2: pwm2grp {
  540. fsl,pins = <
  541. MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  542. >;
  543. };
  544. pinctrl_pwm3: pwm3grp {
  545. fsl,pins = <
  546. MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  547. >;
  548. };
  549. pinctrl_pwm4: pwm4grp {
  550. fsl,pins = <
  551. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  552. >;
  553. };
  554. pinctrl_rv4162: rv4162grp {
  555. fsl,pins = <
  556. MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  557. >;
  558. };
  559. pinctrl_sgtl5000: sgtl5000grp {
  560. fsl,pins = <
  561. MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
  562. MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
  563. MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
  564. >;
  565. };
  566. pinctrl_uart1: uart1grp {
  567. fsl,pins = <
  568. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  569. MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
  570. >;
  571. };
  572. pinctrl_uart2: uart2grp {
  573. fsl,pins = <
  574. MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  575. MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  576. >;
  577. };
  578. pinctrl_uart5: uart5grp {
  579. fsl,pins = <
  580. MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1
  581. MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1
  582. /* RS485 RX Enable: pull up */
  583. MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1
  584. /* RS485 DEN: pull down */
  585. MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1
  586. /* RS485/!RS232 Select: pull down (rs232) */
  587. MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1
  588. /* ON: pull down */
  589. MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1
  590. >;
  591. };
  592. pinctrl_usbh1: usbh1grp {
  593. fsl,pins = <
  594. MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0
  595. >;
  596. };
  597. pinctrl_usbotg: usbotggrp {
  598. fsl,pins = <
  599. MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  600. MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
  601. /* power enable, high active */
  602. MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
  603. >;
  604. };
  605. pinctrl_usdhc2: usdhc2grp {
  606. fsl,pins = <
  607. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  608. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  609. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  610. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  611. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  612. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  613. >;
  614. };
  615. pinctrl_usdhc3: usdhc3grp {
  616. fsl,pins = <
  617. MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  618. MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  619. MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  620. MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  621. MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  622. MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  623. MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0
  624. MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
  625. >;
  626. };
  627. pinctrl_usdhc4: usdhc4grp {
  628. fsl,pins = <
  629. MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  630. MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  631. MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  632. MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  633. MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  634. MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  635. MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  636. MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  637. MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  638. MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  639. >;
  640. };
  641. pinctrl_wlan_vmmc: wlan-vmmcgrp {
  642. fsl,pins = <
  643. MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0
  644. MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0
  645. MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0
  646. MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
  647. >;
  648. };
  649. };
  650. };
  651. &ipu1_di0_disp0 {
  652. remote-endpoint = <&lcd_display_in>;
  653. };
  654. &ldb {
  655. status = "okay";
  656. lvds-channel@0 {
  657. fsl,data-mapping = "spwg";
  658. fsl,data-width = <18>;
  659. status = "okay";
  660. port@4 {
  661. reg = <4>;
  662. lvds0_out: endpoint {
  663. remote-endpoint = <&panel_in_lvds0>;
  664. };
  665. };
  666. };
  667. lvds-channel@1 {
  668. fsl,data-mapping = "spwg";
  669. fsl,data-width = <18>;
  670. status = "okay";
  671. port@4 {
  672. reg = <4>;
  673. lvds1_out: endpoint {
  674. remote-endpoint = <&panel_in_lvds1>;
  675. };
  676. };
  677. };
  678. };
  679. &pcie {
  680. pinctrl-names = "default";
  681. pinctrl-0 = <&pinctrl_pcie>;
  682. reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
  683. status = "okay";
  684. };
  685. &pwm1 {
  686. pinctrl-names = "default";
  687. pinctrl-0 = <&pinctrl_pwm1>;
  688. status = "okay";
  689. };
  690. &pwm2 {
  691. pinctrl-names = "default";
  692. pinctrl-0 = <&pinctrl_pwm2>;
  693. status = "okay";
  694. };
  695. &pwm3 {
  696. pinctrl-names = "default";
  697. pinctrl-0 = <&pinctrl_pwm3>;
  698. status = "okay";
  699. };
  700. &pwm4 {
  701. pinctrl-names = "default";
  702. pinctrl-0 = <&pinctrl_pwm4>;
  703. status = "okay";
  704. };
  705. &ssi1 {
  706. status = "okay";
  707. };
  708. &uart1 {
  709. pinctrl-names = "default";
  710. pinctrl-0 = <&pinctrl_uart1>;
  711. status = "okay";
  712. };
  713. &uart2 {
  714. pinctrl-names = "default";
  715. pinctrl-0 = <&pinctrl_uart2>;
  716. status = "okay";
  717. };
  718. &uart5 {
  719. pinctrl-names = "default";
  720. pinctrl-0 = <&pinctrl_uart5>;
  721. status = "okay";
  722. };
  723. &usbh1 {
  724. vbus-supply = <&reg_usb_h1_vbus>;
  725. status = "okay";
  726. };
  727. &usbotg {
  728. vbus-supply = <&reg_usb_otg_vbus>;
  729. pinctrl-names = "default";
  730. pinctrl-0 = <&pinctrl_usbotg>;
  731. disable-over-current;
  732. status = "okay";
  733. };
  734. &usdhc2 {
  735. pinctrl-names = "default";
  736. pinctrl-0 = <&pinctrl_usdhc2>;
  737. bus-width = <4>;
  738. non-removable;
  739. vmmc-supply = <&reg_wlan_vmmc>;
  740. cap-power-off-card;
  741. keep-power-in-suspend;
  742. status = "okay";
  743. #address-cells = <1>;
  744. #size-cells = <0>;
  745. wlcore: wlcore@2 {
  746. compatible = "ti,wl1271";
  747. reg = <2>;
  748. interrupt-parent = <&gpio6>;
  749. interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
  750. ref-clock-frequency = <38400000>;
  751. };
  752. };
  753. &usdhc3 {
  754. pinctrl-names = "default";
  755. pinctrl-0 = <&pinctrl_usdhc3>;
  756. cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  757. bus-width = <4>;
  758. vmmc-supply = <&reg_3p3v>;
  759. status = "okay";
  760. };
  761. &usdhc4 {
  762. pinctrl-names = "default";
  763. pinctrl-0 = <&pinctrl_usdhc4>;
  764. bus-width = <8>;
  765. non-removable;
  766. vmmc-supply = <&reg_1p8v>;
  767. keep-power-in-suspend;
  768. status = "okay";
  769. };