dwc3-pci.c 9.8 KB

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  1. /**
  2. * dwc3-pci.c - PCI Specific glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * This program is free software: you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 of
  11. * the License as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/pci.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/acpi.h>
  26. #include <linux/delay.h>
  27. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
  28. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
  29. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
  30. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  31. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  32. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  33. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  34. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  35. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  36. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  37. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  38. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  39. #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
  40. #define PCI_INTEL_BXT_DSM_UUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  41. #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
  42. #define PCI_INTEL_BXT_STATE_D0 0
  43. #define PCI_INTEL_BXT_STATE_D3 3
  44. /**
  45. * struct dwc3_pci - Driver private structure
  46. * @dwc3: child dwc3 platform_device
  47. * @pci: our link to PCI bus
  48. * @uuid: _DSM UUID
  49. * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  50. */
  51. struct dwc3_pci {
  52. struct platform_device *dwc3;
  53. struct pci_dev *pci;
  54. u8 uuid[16];
  55. unsigned int has_dsm_for_pm:1;
  56. };
  57. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  58. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  59. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  60. { "reset-gpios", &reset_gpios, 1 },
  61. { "cs-gpios", &cs_gpios, 1 },
  62. { },
  63. };
  64. static int dwc3_pci_quirks(struct dwc3_pci *dwc)
  65. {
  66. struct platform_device *dwc3 = dwc->dwc3;
  67. struct pci_dev *pdev = dwc->pci;
  68. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  69. pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
  70. struct property_entry properties[] = {
  71. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  72. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  73. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  74. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  75. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  76. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  77. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  78. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  79. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  80. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  81. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  82. /*
  83. * FIXME these quirks should be removed when AMD NL
  84. * tapes out
  85. */
  86. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  87. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  88. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  89. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  90. { },
  91. };
  92. return platform_device_add_properties(dwc3, properties);
  93. }
  94. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  95. int ret;
  96. struct property_entry properties[] = {
  97. PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
  98. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  99. { }
  100. };
  101. ret = platform_device_add_properties(dwc3, properties);
  102. if (ret < 0)
  103. return ret;
  104. if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
  105. pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
  106. acpi_str_to_uuid(PCI_INTEL_BXT_DSM_UUID, dwc->uuid);
  107. dwc->has_dsm_for_pm = true;
  108. }
  109. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  110. struct gpio_desc *gpio;
  111. ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
  112. acpi_dwc3_byt_gpios);
  113. if (ret)
  114. dev_dbg(&pdev->dev, "failed to add mapping table\n");
  115. /*
  116. * These GPIOs will turn on the USB2 PHY. Note that we have to
  117. * put the gpio descriptors again here because the phy driver
  118. * might want to grab them, too.
  119. */
  120. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  121. if (IS_ERR(gpio))
  122. return PTR_ERR(gpio);
  123. gpiod_set_value_cansleep(gpio, 1);
  124. gpiod_put(gpio);
  125. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  126. if (IS_ERR(gpio))
  127. return PTR_ERR(gpio);
  128. if (gpio) {
  129. gpiod_set_value_cansleep(gpio, 1);
  130. gpiod_put(gpio);
  131. usleep_range(10000, 11000);
  132. }
  133. }
  134. }
  135. if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
  136. (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
  137. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
  138. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
  139. struct property_entry properties[] = {
  140. PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
  141. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  142. PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
  143. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  144. { },
  145. };
  146. return platform_device_add_properties(dwc3, properties);
  147. }
  148. return 0;
  149. }
  150. static int dwc3_pci_probe(struct pci_dev *pci,
  151. const struct pci_device_id *id)
  152. {
  153. struct dwc3_pci *dwc;
  154. struct resource res[2];
  155. int ret;
  156. struct device *dev = &pci->dev;
  157. ret = pcim_enable_device(pci);
  158. if (ret) {
  159. dev_err(dev, "failed to enable pci device\n");
  160. return -ENODEV;
  161. }
  162. pci_set_master(pci);
  163. dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  164. if (!dwc)
  165. return -ENOMEM;
  166. dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  167. if (!dwc->dwc3)
  168. return -ENOMEM;
  169. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  170. res[0].start = pci_resource_start(pci, 0);
  171. res[0].end = pci_resource_end(pci, 0);
  172. res[0].name = "dwc_usb3";
  173. res[0].flags = IORESOURCE_MEM;
  174. res[1].start = pci->irq;
  175. res[1].name = "dwc_usb3";
  176. res[1].flags = IORESOURCE_IRQ;
  177. ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
  178. if (ret) {
  179. dev_err(dev, "couldn't add resources to dwc3 device\n");
  180. return ret;
  181. }
  182. dwc->pci = pci;
  183. dwc->dwc3->dev.parent = dev;
  184. ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
  185. ret = dwc3_pci_quirks(dwc);
  186. if (ret)
  187. goto err;
  188. ret = platform_device_add(dwc->dwc3);
  189. if (ret) {
  190. dev_err(dev, "failed to register dwc3 device\n");
  191. goto err;
  192. }
  193. device_init_wakeup(dev, true);
  194. device_set_run_wake(dev, true);
  195. pci_set_drvdata(pci, dwc);
  196. pm_runtime_put(dev);
  197. return 0;
  198. err:
  199. platform_device_put(dwc->dwc3);
  200. return ret;
  201. }
  202. static void dwc3_pci_remove(struct pci_dev *pci)
  203. {
  204. struct dwc3_pci *dwc = pci_get_drvdata(pci);
  205. device_init_wakeup(&pci->dev, false);
  206. pm_runtime_get(&pci->dev);
  207. platform_device_unregister(dwc->dwc3);
  208. }
  209. static const struct pci_device_id dwc3_pci_id_table[] = {
  210. {
  211. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  212. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
  213. },
  214. {
  215. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  216. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
  217. },
  218. {
  219. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  220. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
  221. },
  222. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
  223. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
  224. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
  225. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
  226. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
  227. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
  228. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
  229. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
  230. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
  231. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), },
  232. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
  233. { } /* Terminating Entry */
  234. };
  235. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  236. #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
  237. static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
  238. {
  239. union acpi_object *obj;
  240. union acpi_object tmp;
  241. union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
  242. if (!dwc->has_dsm_for_pm)
  243. return 0;
  244. tmp.type = ACPI_TYPE_INTEGER;
  245. tmp.integer.value = param;
  246. obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), dwc->uuid,
  247. 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
  248. if (!obj) {
  249. dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
  250. return -EIO;
  251. }
  252. ACPI_FREE(obj);
  253. return 0;
  254. }
  255. #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
  256. #ifdef CONFIG_PM
  257. static int dwc3_pci_runtime_suspend(struct device *dev)
  258. {
  259. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  260. if (device_run_wake(dev))
  261. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  262. return -EBUSY;
  263. }
  264. static int dwc3_pci_runtime_resume(struct device *dev)
  265. {
  266. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  267. struct platform_device *dwc3 = dwc->dwc3;
  268. int ret;
  269. ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  270. if (ret)
  271. return ret;
  272. return pm_runtime_get(&dwc3->dev);
  273. }
  274. #endif /* CONFIG_PM */
  275. #ifdef CONFIG_PM_SLEEP
  276. static int dwc3_pci_suspend(struct device *dev)
  277. {
  278. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  279. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  280. }
  281. static int dwc3_pci_resume(struct device *dev)
  282. {
  283. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  284. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  285. }
  286. #endif /* CONFIG_PM_SLEEP */
  287. static struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  288. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
  289. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
  290. NULL)
  291. };
  292. static struct pci_driver dwc3_pci_driver = {
  293. .name = "dwc3-pci",
  294. .id_table = dwc3_pci_id_table,
  295. .probe = dwc3_pci_probe,
  296. .remove = dwc3_pci_remove,
  297. .driver = {
  298. .pm = &dwc3_pci_dev_pm_ops,
  299. }
  300. };
  301. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  302. MODULE_LICENSE("GPL v2");
  303. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  304. module_pci_driver(dwc3_pci_driver);