msm_drv.c 23 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "msm_drv.h"
  18. #include "msm_gpu.h"
  19. #include "msm_kms.h"
  20. static void msm_fb_output_poll_changed(struct drm_device *dev)
  21. {
  22. struct msm_drm_private *priv = dev->dev_private;
  23. if (priv->fbdev)
  24. drm_fb_helper_hotplug_event(priv->fbdev);
  25. }
  26. static const struct drm_mode_config_funcs mode_config_funcs = {
  27. .fb_create = msm_framebuffer_create,
  28. .output_poll_changed = msm_fb_output_poll_changed,
  29. };
  30. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
  31. {
  32. struct msm_drm_private *priv = dev->dev_private;
  33. int idx = priv->num_mmus++;
  34. if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
  35. return -EINVAL;
  36. priv->mmus[idx] = mmu;
  37. return idx;
  38. }
  39. #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
  40. static bool reglog = false;
  41. MODULE_PARM_DESC(reglog, "Enable register read/write logging");
  42. module_param(reglog, bool, 0600);
  43. #else
  44. #define reglog 0
  45. #endif
  46. static char *vram;
  47. MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
  48. module_param(vram, charp, 0);
  49. /*
  50. * Util/helpers:
  51. */
  52. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  53. const char *dbgname)
  54. {
  55. struct resource *res;
  56. unsigned long size;
  57. void __iomem *ptr;
  58. if (name)
  59. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  60. else
  61. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  62. if (!res) {
  63. dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
  64. return ERR_PTR(-EINVAL);
  65. }
  66. size = resource_size(res);
  67. ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
  68. if (!ptr) {
  69. dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
  70. return ERR_PTR(-ENOMEM);
  71. }
  72. if (reglog)
  73. printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
  74. return ptr;
  75. }
  76. void msm_writel(u32 data, void __iomem *addr)
  77. {
  78. if (reglog)
  79. printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
  80. writel(data, addr);
  81. }
  82. u32 msm_readl(const void __iomem *addr)
  83. {
  84. u32 val = readl(addr);
  85. if (reglog)
  86. printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
  87. return val;
  88. }
  89. /*
  90. * DRM operations:
  91. */
  92. static int msm_unload(struct drm_device *dev)
  93. {
  94. struct msm_drm_private *priv = dev->dev_private;
  95. struct msm_kms *kms = priv->kms;
  96. struct msm_gpu *gpu = priv->gpu;
  97. drm_kms_helper_poll_fini(dev);
  98. drm_mode_config_cleanup(dev);
  99. drm_vblank_cleanup(dev);
  100. pm_runtime_get_sync(dev->dev);
  101. drm_irq_uninstall(dev);
  102. pm_runtime_put_sync(dev->dev);
  103. flush_workqueue(priv->wq);
  104. destroy_workqueue(priv->wq);
  105. if (kms) {
  106. pm_runtime_disable(dev->dev);
  107. kms->funcs->destroy(kms);
  108. }
  109. if (gpu) {
  110. mutex_lock(&dev->struct_mutex);
  111. gpu->funcs->pm_suspend(gpu);
  112. gpu->funcs->destroy(gpu);
  113. mutex_unlock(&dev->struct_mutex);
  114. }
  115. if (priv->vram.paddr) {
  116. DEFINE_DMA_ATTRS(attrs);
  117. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  118. drm_mm_takedown(&priv->vram.mm);
  119. dma_free_attrs(dev->dev, priv->vram.size, NULL,
  120. priv->vram.paddr, &attrs);
  121. }
  122. component_unbind_all(dev->dev, dev);
  123. dev->dev_private = NULL;
  124. kfree(priv);
  125. return 0;
  126. }
  127. static int get_mdp_ver(struct platform_device *pdev)
  128. {
  129. #ifdef CONFIG_OF
  130. const static struct of_device_id match_types[] = { {
  131. .compatible = "qcom,mdss_mdp",
  132. .data = (void *)5,
  133. }, {
  134. /* end node */
  135. } };
  136. struct device *dev = &pdev->dev;
  137. const struct of_device_id *match;
  138. match = of_match_node(match_types, dev->of_node);
  139. if (match)
  140. return (int)match->data;
  141. #endif
  142. return 4;
  143. }
  144. static int msm_load(struct drm_device *dev, unsigned long flags)
  145. {
  146. struct platform_device *pdev = dev->platformdev;
  147. struct msm_drm_private *priv;
  148. struct msm_kms *kms;
  149. int ret;
  150. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  151. if (!priv) {
  152. dev_err(dev->dev, "failed to allocate private data\n");
  153. return -ENOMEM;
  154. }
  155. dev->dev_private = priv;
  156. priv->wq = alloc_ordered_workqueue("msm", 0);
  157. init_waitqueue_head(&priv->fence_event);
  158. INIT_LIST_HEAD(&priv->inactive_list);
  159. INIT_LIST_HEAD(&priv->fence_cbs);
  160. drm_mode_config_init(dev);
  161. /* if we have no IOMMU, then we need to use carveout allocator.
  162. * Grab the entire CMA chunk carved out in early startup in
  163. * mach-msm:
  164. */
  165. if (!iommu_present(&platform_bus_type)) {
  166. DEFINE_DMA_ATTRS(attrs);
  167. unsigned long size;
  168. void *p;
  169. DBG("using %s VRAM carveout", vram);
  170. size = memparse(vram, NULL);
  171. priv->vram.size = size;
  172. drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
  173. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  174. dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
  175. /* note that for no-kernel-mapping, the vaddr returned
  176. * is bogus, but non-null if allocation succeeded:
  177. */
  178. p = dma_alloc_attrs(dev->dev, size,
  179. &priv->vram.paddr, 0, &attrs);
  180. if (!p) {
  181. dev_err(dev->dev, "failed to allocate VRAM\n");
  182. priv->vram.paddr = 0;
  183. ret = -ENOMEM;
  184. goto fail;
  185. }
  186. dev_info(dev->dev, "VRAM: %08x->%08x\n",
  187. (uint32_t)priv->vram.paddr,
  188. (uint32_t)(priv->vram.paddr + size));
  189. }
  190. platform_set_drvdata(pdev, dev);
  191. /* Bind all our sub-components: */
  192. ret = component_bind_all(dev->dev, dev);
  193. if (ret)
  194. return ret;
  195. switch (get_mdp_ver(pdev)) {
  196. case 4:
  197. kms = mdp4_kms_init(dev);
  198. break;
  199. case 5:
  200. kms = mdp5_kms_init(dev);
  201. break;
  202. default:
  203. kms = ERR_PTR(-ENODEV);
  204. break;
  205. }
  206. if (IS_ERR(kms)) {
  207. /*
  208. * NOTE: once we have GPU support, having no kms should not
  209. * be considered fatal.. ideally we would still support gpu
  210. * and (for example) use dmabuf/prime to share buffers with
  211. * imx drm driver on iMX5
  212. */
  213. dev_err(dev->dev, "failed to load kms\n");
  214. ret = PTR_ERR(kms);
  215. goto fail;
  216. }
  217. priv->kms = kms;
  218. if (kms) {
  219. pm_runtime_enable(dev->dev);
  220. ret = kms->funcs->hw_init(kms);
  221. if (ret) {
  222. dev_err(dev->dev, "kms hw init failed: %d\n", ret);
  223. goto fail;
  224. }
  225. }
  226. dev->mode_config.min_width = 0;
  227. dev->mode_config.min_height = 0;
  228. dev->mode_config.max_width = 2048;
  229. dev->mode_config.max_height = 2048;
  230. dev->mode_config.funcs = &mode_config_funcs;
  231. ret = drm_vblank_init(dev, 1);
  232. if (ret < 0) {
  233. dev_err(dev->dev, "failed to initialize vblank\n");
  234. goto fail;
  235. }
  236. pm_runtime_get_sync(dev->dev);
  237. ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
  238. pm_runtime_put_sync(dev->dev);
  239. if (ret < 0) {
  240. dev_err(dev->dev, "failed to install IRQ handler\n");
  241. goto fail;
  242. }
  243. #ifdef CONFIG_DRM_MSM_FBDEV
  244. priv->fbdev = msm_fbdev_init(dev);
  245. #endif
  246. drm_kms_helper_poll_init(dev);
  247. return 0;
  248. fail:
  249. msm_unload(dev);
  250. return ret;
  251. }
  252. static void load_gpu(struct drm_device *dev)
  253. {
  254. struct msm_drm_private *priv = dev->dev_private;
  255. struct msm_gpu *gpu;
  256. if (priv->gpu)
  257. return;
  258. mutex_lock(&dev->struct_mutex);
  259. gpu = a3xx_gpu_init(dev);
  260. if (IS_ERR(gpu)) {
  261. dev_warn(dev->dev, "failed to load a3xx gpu\n");
  262. gpu = NULL;
  263. /* not fatal */
  264. }
  265. if (gpu) {
  266. int ret;
  267. gpu->funcs->pm_resume(gpu);
  268. ret = gpu->funcs->hw_init(gpu);
  269. if (ret) {
  270. dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
  271. gpu->funcs->destroy(gpu);
  272. gpu = NULL;
  273. } else {
  274. /* give inactive pm a chance to kick in: */
  275. msm_gpu_retire(gpu);
  276. }
  277. }
  278. priv->gpu = gpu;
  279. mutex_unlock(&dev->struct_mutex);
  280. }
  281. static int msm_open(struct drm_device *dev, struct drm_file *file)
  282. {
  283. struct msm_file_private *ctx;
  284. /* For now, load gpu on open.. to avoid the requirement of having
  285. * firmware in the initrd.
  286. */
  287. load_gpu(dev);
  288. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  289. if (!ctx)
  290. return -ENOMEM;
  291. file->driver_priv = ctx;
  292. return 0;
  293. }
  294. static void msm_preclose(struct drm_device *dev, struct drm_file *file)
  295. {
  296. struct msm_drm_private *priv = dev->dev_private;
  297. struct msm_file_private *ctx = file->driver_priv;
  298. struct msm_kms *kms = priv->kms;
  299. if (kms)
  300. kms->funcs->preclose(kms, file);
  301. mutex_lock(&dev->struct_mutex);
  302. if (ctx == priv->lastctx)
  303. priv->lastctx = NULL;
  304. mutex_unlock(&dev->struct_mutex);
  305. kfree(ctx);
  306. }
  307. static void msm_lastclose(struct drm_device *dev)
  308. {
  309. struct msm_drm_private *priv = dev->dev_private;
  310. if (priv->fbdev) {
  311. drm_modeset_lock_all(dev);
  312. drm_fb_helper_restore_fbdev_mode(priv->fbdev);
  313. drm_modeset_unlock_all(dev);
  314. }
  315. }
  316. static irqreturn_t msm_irq(int irq, void *arg)
  317. {
  318. struct drm_device *dev = arg;
  319. struct msm_drm_private *priv = dev->dev_private;
  320. struct msm_kms *kms = priv->kms;
  321. BUG_ON(!kms);
  322. return kms->funcs->irq(kms);
  323. }
  324. static void msm_irq_preinstall(struct drm_device *dev)
  325. {
  326. struct msm_drm_private *priv = dev->dev_private;
  327. struct msm_kms *kms = priv->kms;
  328. BUG_ON(!kms);
  329. kms->funcs->irq_preinstall(kms);
  330. }
  331. static int msm_irq_postinstall(struct drm_device *dev)
  332. {
  333. struct msm_drm_private *priv = dev->dev_private;
  334. struct msm_kms *kms = priv->kms;
  335. BUG_ON(!kms);
  336. return kms->funcs->irq_postinstall(kms);
  337. }
  338. static void msm_irq_uninstall(struct drm_device *dev)
  339. {
  340. struct msm_drm_private *priv = dev->dev_private;
  341. struct msm_kms *kms = priv->kms;
  342. BUG_ON(!kms);
  343. kms->funcs->irq_uninstall(kms);
  344. }
  345. static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
  346. {
  347. struct msm_drm_private *priv = dev->dev_private;
  348. struct msm_kms *kms = priv->kms;
  349. if (!kms)
  350. return -ENXIO;
  351. DBG("dev=%p, crtc=%d", dev, crtc_id);
  352. return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
  353. }
  354. static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
  355. {
  356. struct msm_drm_private *priv = dev->dev_private;
  357. struct msm_kms *kms = priv->kms;
  358. if (!kms)
  359. return;
  360. DBG("dev=%p, crtc=%d", dev, crtc_id);
  361. kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
  362. }
  363. /*
  364. * DRM debugfs:
  365. */
  366. #ifdef CONFIG_DEBUG_FS
  367. static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
  368. {
  369. struct msm_drm_private *priv = dev->dev_private;
  370. struct msm_gpu *gpu = priv->gpu;
  371. if (gpu) {
  372. seq_printf(m, "%s Status:\n", gpu->name);
  373. gpu->funcs->show(gpu, m);
  374. }
  375. return 0;
  376. }
  377. static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
  378. {
  379. struct msm_drm_private *priv = dev->dev_private;
  380. struct msm_gpu *gpu = priv->gpu;
  381. if (gpu) {
  382. seq_printf(m, "Active Objects (%s):\n", gpu->name);
  383. msm_gem_describe_objects(&gpu->active_list, m);
  384. }
  385. seq_printf(m, "Inactive Objects:\n");
  386. msm_gem_describe_objects(&priv->inactive_list, m);
  387. return 0;
  388. }
  389. static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
  390. {
  391. return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
  392. }
  393. static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
  394. {
  395. struct msm_drm_private *priv = dev->dev_private;
  396. struct drm_framebuffer *fb, *fbdev_fb = NULL;
  397. if (priv->fbdev) {
  398. seq_printf(m, "fbcon ");
  399. fbdev_fb = priv->fbdev->fb;
  400. msm_framebuffer_describe(fbdev_fb, m);
  401. }
  402. mutex_lock(&dev->mode_config.fb_lock);
  403. list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
  404. if (fb == fbdev_fb)
  405. continue;
  406. seq_printf(m, "user ");
  407. msm_framebuffer_describe(fb, m);
  408. }
  409. mutex_unlock(&dev->mode_config.fb_lock);
  410. return 0;
  411. }
  412. static int show_locked(struct seq_file *m, void *arg)
  413. {
  414. struct drm_info_node *node = (struct drm_info_node *) m->private;
  415. struct drm_device *dev = node->minor->dev;
  416. int (*show)(struct drm_device *dev, struct seq_file *m) =
  417. node->info_ent->data;
  418. int ret;
  419. ret = mutex_lock_interruptible(&dev->struct_mutex);
  420. if (ret)
  421. return ret;
  422. ret = show(dev, m);
  423. mutex_unlock(&dev->struct_mutex);
  424. return ret;
  425. }
  426. static struct drm_info_list msm_debugfs_list[] = {
  427. {"gpu", show_locked, 0, msm_gpu_show},
  428. {"gem", show_locked, 0, msm_gem_show},
  429. { "mm", show_locked, 0, msm_mm_show },
  430. { "fb", show_locked, 0, msm_fb_show },
  431. };
  432. static int msm_debugfs_init(struct drm_minor *minor)
  433. {
  434. struct drm_device *dev = minor->dev;
  435. int ret;
  436. ret = drm_debugfs_create_files(msm_debugfs_list,
  437. ARRAY_SIZE(msm_debugfs_list),
  438. minor->debugfs_root, minor);
  439. if (ret) {
  440. dev_err(dev->dev, "could not install msm_debugfs_list\n");
  441. return ret;
  442. }
  443. return ret;
  444. }
  445. static void msm_debugfs_cleanup(struct drm_minor *minor)
  446. {
  447. drm_debugfs_remove_files(msm_debugfs_list,
  448. ARRAY_SIZE(msm_debugfs_list), minor);
  449. }
  450. #endif
  451. /*
  452. * Fences:
  453. */
  454. int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
  455. struct timespec *timeout)
  456. {
  457. struct msm_drm_private *priv = dev->dev_private;
  458. int ret;
  459. if (!priv->gpu)
  460. return 0;
  461. if (fence > priv->gpu->submitted_fence) {
  462. DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
  463. fence, priv->gpu->submitted_fence);
  464. return -EINVAL;
  465. }
  466. if (!timeout) {
  467. /* no-wait: */
  468. ret = fence_completed(dev, fence) ? 0 : -EBUSY;
  469. } else {
  470. unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
  471. unsigned long start_jiffies = jiffies;
  472. unsigned long remaining_jiffies;
  473. if (time_after(start_jiffies, timeout_jiffies))
  474. remaining_jiffies = 0;
  475. else
  476. remaining_jiffies = timeout_jiffies - start_jiffies;
  477. ret = wait_event_interruptible_timeout(priv->fence_event,
  478. fence_completed(dev, fence),
  479. remaining_jiffies);
  480. if (ret == 0) {
  481. DBG("timeout waiting for fence: %u (completed: %u)",
  482. fence, priv->completed_fence);
  483. ret = -ETIMEDOUT;
  484. } else if (ret != -ERESTARTSYS) {
  485. ret = 0;
  486. }
  487. }
  488. return ret;
  489. }
  490. /* called from workqueue */
  491. void msm_update_fence(struct drm_device *dev, uint32_t fence)
  492. {
  493. struct msm_drm_private *priv = dev->dev_private;
  494. mutex_lock(&dev->struct_mutex);
  495. priv->completed_fence = max(fence, priv->completed_fence);
  496. while (!list_empty(&priv->fence_cbs)) {
  497. struct msm_fence_cb *cb;
  498. cb = list_first_entry(&priv->fence_cbs,
  499. struct msm_fence_cb, work.entry);
  500. if (cb->fence > priv->completed_fence)
  501. break;
  502. list_del_init(&cb->work.entry);
  503. queue_work(priv->wq, &cb->work);
  504. }
  505. mutex_unlock(&dev->struct_mutex);
  506. wake_up_all(&priv->fence_event);
  507. }
  508. void __msm_fence_worker(struct work_struct *work)
  509. {
  510. struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
  511. cb->func(cb);
  512. }
  513. /*
  514. * DRM ioctls:
  515. */
  516. static int msm_ioctl_get_param(struct drm_device *dev, void *data,
  517. struct drm_file *file)
  518. {
  519. struct msm_drm_private *priv = dev->dev_private;
  520. struct drm_msm_param *args = data;
  521. struct msm_gpu *gpu;
  522. /* for now, we just have 3d pipe.. eventually this would need to
  523. * be more clever to dispatch to appropriate gpu module:
  524. */
  525. if (args->pipe != MSM_PIPE_3D0)
  526. return -EINVAL;
  527. gpu = priv->gpu;
  528. if (!gpu)
  529. return -ENXIO;
  530. return gpu->funcs->get_param(gpu, args->param, &args->value);
  531. }
  532. static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
  533. struct drm_file *file)
  534. {
  535. struct drm_msm_gem_new *args = data;
  536. if (args->flags & ~MSM_BO_FLAGS) {
  537. DRM_ERROR("invalid flags: %08x\n", args->flags);
  538. return -EINVAL;
  539. }
  540. return msm_gem_new_handle(dev, file, args->size,
  541. args->flags, &args->handle);
  542. }
  543. #define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
  544. static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  545. struct drm_file *file)
  546. {
  547. struct drm_msm_gem_cpu_prep *args = data;
  548. struct drm_gem_object *obj;
  549. int ret;
  550. if (args->op & ~MSM_PREP_FLAGS) {
  551. DRM_ERROR("invalid op: %08x\n", args->op);
  552. return -EINVAL;
  553. }
  554. obj = drm_gem_object_lookup(dev, file, args->handle);
  555. if (!obj)
  556. return -ENOENT;
  557. ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
  558. drm_gem_object_unreference_unlocked(obj);
  559. return ret;
  560. }
  561. static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  562. struct drm_file *file)
  563. {
  564. struct drm_msm_gem_cpu_fini *args = data;
  565. struct drm_gem_object *obj;
  566. int ret;
  567. obj = drm_gem_object_lookup(dev, file, args->handle);
  568. if (!obj)
  569. return -ENOENT;
  570. ret = msm_gem_cpu_fini(obj);
  571. drm_gem_object_unreference_unlocked(obj);
  572. return ret;
  573. }
  574. static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
  575. struct drm_file *file)
  576. {
  577. struct drm_msm_gem_info *args = data;
  578. struct drm_gem_object *obj;
  579. int ret = 0;
  580. if (args->pad)
  581. return -EINVAL;
  582. obj = drm_gem_object_lookup(dev, file, args->handle);
  583. if (!obj)
  584. return -ENOENT;
  585. args->offset = msm_gem_mmap_offset(obj);
  586. drm_gem_object_unreference_unlocked(obj);
  587. return ret;
  588. }
  589. static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
  590. struct drm_file *file)
  591. {
  592. struct drm_msm_wait_fence *args = data;
  593. if (args->pad) {
  594. DRM_ERROR("invalid pad: %08x\n", args->pad);
  595. return -EINVAL;
  596. }
  597. return msm_wait_fence_interruptable(dev, args->fence,
  598. &TS(args->timeout));
  599. }
  600. static const struct drm_ioctl_desc msm_ioctls[] = {
  601. DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  602. DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  603. DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  604. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  605. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  606. DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  607. DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  608. };
  609. static const struct vm_operations_struct vm_ops = {
  610. .fault = msm_gem_fault,
  611. .open = drm_gem_vm_open,
  612. .close = drm_gem_vm_close,
  613. };
  614. static const struct file_operations fops = {
  615. .owner = THIS_MODULE,
  616. .open = drm_open,
  617. .release = drm_release,
  618. .unlocked_ioctl = drm_ioctl,
  619. #ifdef CONFIG_COMPAT
  620. .compat_ioctl = drm_compat_ioctl,
  621. #endif
  622. .poll = drm_poll,
  623. .read = drm_read,
  624. .llseek = no_llseek,
  625. .mmap = msm_gem_mmap,
  626. };
  627. static struct drm_driver msm_driver = {
  628. .driver_features = DRIVER_HAVE_IRQ |
  629. DRIVER_GEM |
  630. DRIVER_PRIME |
  631. DRIVER_RENDER |
  632. DRIVER_MODESET,
  633. .load = msm_load,
  634. .unload = msm_unload,
  635. .open = msm_open,
  636. .preclose = msm_preclose,
  637. .lastclose = msm_lastclose,
  638. .irq_handler = msm_irq,
  639. .irq_preinstall = msm_irq_preinstall,
  640. .irq_postinstall = msm_irq_postinstall,
  641. .irq_uninstall = msm_irq_uninstall,
  642. .get_vblank_counter = drm_vblank_count,
  643. .enable_vblank = msm_enable_vblank,
  644. .disable_vblank = msm_disable_vblank,
  645. .gem_free_object = msm_gem_free_object,
  646. .gem_vm_ops = &vm_ops,
  647. .dumb_create = msm_gem_dumb_create,
  648. .dumb_map_offset = msm_gem_dumb_map_offset,
  649. .dumb_destroy = drm_gem_dumb_destroy,
  650. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  651. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  652. .gem_prime_export = drm_gem_prime_export,
  653. .gem_prime_import = drm_gem_prime_import,
  654. .gem_prime_pin = msm_gem_prime_pin,
  655. .gem_prime_unpin = msm_gem_prime_unpin,
  656. .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
  657. .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
  658. .gem_prime_vmap = msm_gem_prime_vmap,
  659. .gem_prime_vunmap = msm_gem_prime_vunmap,
  660. #ifdef CONFIG_DEBUG_FS
  661. .debugfs_init = msm_debugfs_init,
  662. .debugfs_cleanup = msm_debugfs_cleanup,
  663. #endif
  664. .ioctls = msm_ioctls,
  665. .num_ioctls = DRM_MSM_NUM_IOCTLS,
  666. .fops = &fops,
  667. .name = "msm",
  668. .desc = "MSM Snapdragon DRM",
  669. .date = "20130625",
  670. .major = 1,
  671. .minor = 0,
  672. };
  673. #ifdef CONFIG_PM_SLEEP
  674. static int msm_pm_suspend(struct device *dev)
  675. {
  676. struct drm_device *ddev = dev_get_drvdata(dev);
  677. drm_kms_helper_poll_disable(ddev);
  678. return 0;
  679. }
  680. static int msm_pm_resume(struct device *dev)
  681. {
  682. struct drm_device *ddev = dev_get_drvdata(dev);
  683. drm_kms_helper_poll_enable(ddev);
  684. return 0;
  685. }
  686. #endif
  687. static const struct dev_pm_ops msm_pm_ops = {
  688. SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
  689. };
  690. /*
  691. * Componentized driver support:
  692. */
  693. #ifdef CONFIG_OF
  694. /* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx
  695. * (or probably any other).. so probably some room for some helpers
  696. */
  697. static int compare_of(struct device *dev, void *data)
  698. {
  699. return dev->of_node == data;
  700. }
  701. static int msm_drm_add_components(struct device *master, struct master *m)
  702. {
  703. struct device_node *np = master->of_node;
  704. unsigned i;
  705. int ret;
  706. for (i = 0; ; i++) {
  707. struct device_node *node;
  708. node = of_parse_phandle(np, "connectors", i);
  709. if (!node)
  710. break;
  711. ret = component_master_add_child(m, compare_of, node);
  712. of_node_put(node);
  713. if (ret)
  714. return ret;
  715. }
  716. return 0;
  717. }
  718. #else
  719. static int compare_dev(struct device *dev, void *data)
  720. {
  721. return dev == data;
  722. }
  723. static int msm_drm_add_components(struct device *master, struct master *m)
  724. {
  725. /* For non-DT case, it kinda sucks. We don't actually have a way
  726. * to know whether or not we are waiting for certain devices (or if
  727. * they are simply not present). But for non-DT we only need to
  728. * care about apq8064/apq8060/etc (all mdp4/a3xx):
  729. */
  730. static const char *devnames[] = {
  731. "hdmi_msm.0", "kgsl-3d0.0",
  732. };
  733. int i;
  734. DBG("Adding components..");
  735. for (i = 0; i < ARRAY_SIZE(devnames); i++) {
  736. struct device *dev;
  737. int ret;
  738. dev = bus_find_device_by_name(&platform_bus_type,
  739. NULL, devnames[i]);
  740. if (!dev) {
  741. dev_info(master, "still waiting for %s\n", devnames[i]);
  742. return -EPROBE_DEFER;
  743. }
  744. ret = component_master_add_child(m, compare_dev, dev);
  745. if (ret) {
  746. DBG("could not add child: %d", ret);
  747. return ret;
  748. }
  749. }
  750. return 0;
  751. }
  752. #endif
  753. static int msm_drm_bind(struct device *dev)
  754. {
  755. return drm_platform_init(&msm_driver, to_platform_device(dev));
  756. }
  757. static void msm_drm_unbind(struct device *dev)
  758. {
  759. drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
  760. }
  761. static const struct component_master_ops msm_drm_ops = {
  762. .add_components = msm_drm_add_components,
  763. .bind = msm_drm_bind,
  764. .unbind = msm_drm_unbind,
  765. };
  766. /*
  767. * Platform driver:
  768. */
  769. static int msm_pdev_probe(struct platform_device *pdev)
  770. {
  771. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  772. return component_master_add(&pdev->dev, &msm_drm_ops);
  773. }
  774. static int msm_pdev_remove(struct platform_device *pdev)
  775. {
  776. component_master_del(&pdev->dev, &msm_drm_ops);
  777. return 0;
  778. }
  779. static const struct platform_device_id msm_id[] = {
  780. { "mdp", 0 },
  781. { }
  782. };
  783. static const struct of_device_id dt_match[] = {
  784. { .compatible = "qcom,mdss_mdp" },
  785. {}
  786. };
  787. MODULE_DEVICE_TABLE(of, dt_match);
  788. static struct platform_driver msm_platform_driver = {
  789. .probe = msm_pdev_probe,
  790. .remove = msm_pdev_remove,
  791. .driver = {
  792. .owner = THIS_MODULE,
  793. .name = "msm",
  794. .of_match_table = dt_match,
  795. .pm = &msm_pm_ops,
  796. },
  797. .id_table = msm_id,
  798. };
  799. static int __init msm_drm_register(void)
  800. {
  801. DBG("init");
  802. hdmi_register();
  803. a3xx_register();
  804. return platform_driver_register(&msm_platform_driver);
  805. }
  806. static void __exit msm_drm_unregister(void)
  807. {
  808. DBG("fini");
  809. platform_driver_unregister(&msm_platform_driver);
  810. hdmi_unregister();
  811. a3xx_unregister();
  812. }
  813. module_init(msm_drm_register);
  814. module_exit(msm_drm_unregister);
  815. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  816. MODULE_DESCRIPTION("MSM DRM Driver");
  817. MODULE_LICENSE("GPL");