xhci-pci.c 12 KB

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  1. /*
  2. * xHCI host controller driver PCI Bus Glue.
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/slab.h>
  24. #include <linux/module.h>
  25. #include "xhci.h"
  26. #include "xhci-trace.h"
  27. /* Device for a quirk */
  28. #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
  29. #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
  30. #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
  31. #define PCI_VENDOR_ID_ETRON 0x1b6f
  32. #define PCI_DEVICE_ID_ASROCK_P67 0x7023
  33. #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
  34. #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
  35. static const char hcd_name[] = "xhci_hcd";
  36. /* called after powerup, by probe or system-pm "wakeup" */
  37. static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  38. {
  39. /*
  40. * TODO: Implement finding debug ports later.
  41. * TODO: see if there are any quirks that need to be added to handle
  42. * new extended capabilities.
  43. */
  44. /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  45. if (!pci_set_mwi(pdev))
  46. xhci_dbg(xhci, "MWI active\n");
  47. xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  48. return 0;
  49. }
  50. static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  51. {
  52. struct pci_dev *pdev = to_pci_dev(dev);
  53. /* Look for vendor-specific quirks */
  54. if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  55. (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  56. pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  57. if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  58. pdev->revision == 0x0) {
  59. xhci->quirks |= XHCI_RESET_EP_QUIRK;
  60. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  61. "QUIRK: Fresco Logic xHC needs configure"
  62. " endpoint cmd after reset endpoint");
  63. }
  64. if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  65. pdev->revision == 0x4) {
  66. xhci->quirks |= XHCI_SLOW_SUSPEND;
  67. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  68. "QUIRK: Fresco Logic xHC revision %u"
  69. "must be suspended extra slowly",
  70. pdev->revision);
  71. }
  72. /* Fresco Logic confirms: all revisions of this chip do not
  73. * support MSI, even though some of them claim to in their PCI
  74. * capabilities.
  75. */
  76. xhci->quirks |= XHCI_BROKEN_MSI;
  77. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  78. "QUIRK: Fresco Logic revision %u "
  79. "has broken MSI implementation",
  80. pdev->revision);
  81. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  82. }
  83. if (pdev->vendor == PCI_VENDOR_ID_NEC)
  84. xhci->quirks |= XHCI_NEC_HOST;
  85. if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
  86. xhci->quirks |= XHCI_AMD_0x96_HOST;
  87. /* AMD PLL quirk */
  88. if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
  89. xhci->quirks |= XHCI_AMD_PLL_FIX;
  90. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  91. xhci->quirks |= XHCI_LPM_SUPPORT;
  92. xhci->quirks |= XHCI_INTEL_HOST;
  93. }
  94. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  95. pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
  96. xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
  97. xhci->limit_active_eps = 64;
  98. xhci->quirks |= XHCI_SW_BW_CHECKING;
  99. /*
  100. * PPT desktop boards DH77EB and DH77DF will power back on after
  101. * a few seconds of being shutdown. The fix for this is to
  102. * switch the ports from xHCI to EHCI on shutdown. We can't use
  103. * DMI information to find those particular boards (since each
  104. * vendor will change the board name), so we have to key off all
  105. * PPT chipsets.
  106. */
  107. xhci->quirks |= XHCI_SPURIOUS_REBOOT;
  108. xhci->quirks |= XHCI_AVOID_BEI;
  109. }
  110. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  111. (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI ||
  112. pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) {
  113. /* Workaround for occasional spurious wakeups from S5 (or
  114. * any other sleep) on Haswell machines with LPT and LPT-LP
  115. * with the new Intel BIOS
  116. */
  117. /* Limit the quirk to only known vendors, as this triggers
  118. * yet another BIOS bug on some other machines
  119. * https://bugzilla.kernel.org/show_bug.cgi?id=66171
  120. */
  121. if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)
  122. xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
  123. }
  124. if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
  125. pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
  126. xhci->quirks |= XHCI_RESET_ON_RESUME;
  127. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  128. "QUIRK: Resetting on resume");
  129. xhci->quirks |= XHCI_TRUST_TX_LENGTH;
  130. }
  131. if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
  132. pdev->device == 0x0015 &&
  133. pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
  134. pdev->subsystem_device == 0xc0cd)
  135. xhci->quirks |= XHCI_RESET_ON_RESUME;
  136. if (pdev->vendor == PCI_VENDOR_ID_VIA)
  137. xhci->quirks |= XHCI_RESET_ON_RESUME;
  138. }
  139. /* called during probe() after chip reset completes */
  140. static int xhci_pci_setup(struct usb_hcd *hcd)
  141. {
  142. struct xhci_hcd *xhci;
  143. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  144. int retval;
  145. retval = xhci_gen_setup(hcd, xhci_pci_quirks);
  146. if (retval)
  147. return retval;
  148. xhci = hcd_to_xhci(hcd);
  149. if (!usb_hcd_is_primary_hcd(hcd))
  150. return 0;
  151. pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
  152. xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
  153. /* Find any debug ports */
  154. retval = xhci_pci_reinit(xhci, pdev);
  155. if (!retval)
  156. return retval;
  157. kfree(xhci);
  158. return retval;
  159. }
  160. /*
  161. * We need to register our own PCI probe function (instead of the USB core's
  162. * function) in order to create a second roothub under xHCI.
  163. */
  164. static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  165. {
  166. int retval;
  167. struct xhci_hcd *xhci;
  168. struct hc_driver *driver;
  169. struct usb_hcd *hcd;
  170. driver = (struct hc_driver *)id->driver_data;
  171. /* Prevent runtime suspending between USB-2 and USB-3 initialization */
  172. pm_runtime_get_noresume(&dev->dev);
  173. /* Register the USB 2.0 roothub.
  174. * FIXME: USB core must know to register the USB 2.0 roothub first.
  175. * This is sort of silly, because we could just set the HCD driver flags
  176. * to say USB 2.0, but I'm not sure what the implications would be in
  177. * the other parts of the HCD code.
  178. */
  179. retval = usb_hcd_pci_probe(dev, id);
  180. if (retval)
  181. goto put_runtime_pm;
  182. /* USB 2.0 roothub is stored in the PCI device now. */
  183. hcd = dev_get_drvdata(&dev->dev);
  184. xhci = hcd_to_xhci(hcd);
  185. xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
  186. pci_name(dev), hcd);
  187. if (!xhci->shared_hcd) {
  188. retval = -ENOMEM;
  189. goto dealloc_usb2_hcd;
  190. }
  191. /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
  192. * is called by usb_add_hcd().
  193. */
  194. *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
  195. retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
  196. IRQF_SHARED);
  197. if (retval)
  198. goto put_usb3_hcd;
  199. /* Roothub already marked as USB 3.0 speed */
  200. if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
  201. xhci->shared_hcd->can_do_streams = 1;
  202. /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
  203. pm_runtime_put_noidle(&dev->dev);
  204. return 0;
  205. put_usb3_hcd:
  206. usb_put_hcd(xhci->shared_hcd);
  207. dealloc_usb2_hcd:
  208. usb_hcd_pci_remove(dev);
  209. put_runtime_pm:
  210. pm_runtime_put_noidle(&dev->dev);
  211. return retval;
  212. }
  213. static void xhci_pci_remove(struct pci_dev *dev)
  214. {
  215. struct xhci_hcd *xhci;
  216. xhci = hcd_to_xhci(pci_get_drvdata(dev));
  217. if (xhci->shared_hcd) {
  218. usb_remove_hcd(xhci->shared_hcd);
  219. usb_put_hcd(xhci->shared_hcd);
  220. }
  221. usb_hcd_pci_remove(dev);
  222. /* Workaround for spurious wakeups at shutdown with HSW */
  223. if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
  224. pci_set_power_state(dev, PCI_D3hot);
  225. kfree(xhci);
  226. }
  227. #ifdef CONFIG_PM
  228. static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
  229. {
  230. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  231. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  232. /*
  233. * Systems with the TI redriver that loses port status change events
  234. * need to have the registers polled during D3, so avoid D3cold.
  235. */
  236. if (xhci_compliance_mode_recovery_timer_quirk_check())
  237. pdev->no_d3cold = true;
  238. return xhci_suspend(xhci);
  239. }
  240. static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
  241. {
  242. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  243. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  244. int retval = 0;
  245. /* The BIOS on systems with the Intel Panther Point chipset may or may
  246. * not support xHCI natively. That means that during system resume, it
  247. * may switch the ports back to EHCI so that users can use their
  248. * keyboard to select a kernel from GRUB after resume from hibernate.
  249. *
  250. * The BIOS is supposed to remember whether the OS had xHCI ports
  251. * enabled before resume, and switch the ports back to xHCI when the
  252. * BIOS/OS semaphore is written, but we all know we can't trust BIOS
  253. * writers.
  254. *
  255. * Unconditionally switch the ports back to xHCI after a system resume.
  256. * It should not matter whether the EHCI or xHCI controller is
  257. * resumed first. It's enough to do the switchover in xHCI because
  258. * USB core won't notice anything as the hub driver doesn't start
  259. * running again until after all the devices (including both EHCI and
  260. * xHCI host controllers) have been resumed.
  261. */
  262. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  263. usb_enable_intel_xhci_ports(pdev);
  264. retval = xhci_resume(xhci, hibernated);
  265. return retval;
  266. }
  267. #endif /* CONFIG_PM */
  268. static const struct hc_driver xhci_pci_hc_driver = {
  269. .description = hcd_name,
  270. .product_desc = "xHCI Host Controller",
  271. .hcd_priv_size = sizeof(struct xhci_hcd *),
  272. /*
  273. * generic hardware linkage
  274. */
  275. .irq = xhci_irq,
  276. .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
  277. /*
  278. * basic lifecycle operations
  279. */
  280. .reset = xhci_pci_setup,
  281. .start = xhci_run,
  282. #ifdef CONFIG_PM
  283. .pci_suspend = xhci_pci_suspend,
  284. .pci_resume = xhci_pci_resume,
  285. #endif
  286. .stop = xhci_stop,
  287. .shutdown = xhci_shutdown,
  288. /*
  289. * managing i/o requests and associated device resources
  290. */
  291. .urb_enqueue = xhci_urb_enqueue,
  292. .urb_dequeue = xhci_urb_dequeue,
  293. .alloc_dev = xhci_alloc_dev,
  294. .free_dev = xhci_free_dev,
  295. .alloc_streams = xhci_alloc_streams,
  296. .free_streams = xhci_free_streams,
  297. .add_endpoint = xhci_add_endpoint,
  298. .drop_endpoint = xhci_drop_endpoint,
  299. .endpoint_reset = xhci_endpoint_reset,
  300. .check_bandwidth = xhci_check_bandwidth,
  301. .reset_bandwidth = xhci_reset_bandwidth,
  302. .address_device = xhci_address_device,
  303. .enable_device = xhci_enable_device,
  304. .update_hub_device = xhci_update_hub_device,
  305. .reset_device = xhci_discover_or_reset_device,
  306. /*
  307. * scheduling support
  308. */
  309. .get_frame_number = xhci_get_frame,
  310. /* Root hub support */
  311. .hub_control = xhci_hub_control,
  312. .hub_status_data = xhci_hub_status_data,
  313. .bus_suspend = xhci_bus_suspend,
  314. .bus_resume = xhci_bus_resume,
  315. /*
  316. * call back when device connected and addressed
  317. */
  318. .update_device = xhci_update_device,
  319. .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
  320. .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
  321. .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
  322. .find_raw_port_number = xhci_find_raw_port_number,
  323. };
  324. /*-------------------------------------------------------------------------*/
  325. /* PCI driver selection metadata; PCI hotplugging uses this */
  326. static const struct pci_device_id pci_ids[] = { {
  327. /* handle any USB 3.0 xHCI controller */
  328. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
  329. .driver_data = (unsigned long) &xhci_pci_hc_driver,
  330. },
  331. { /* end: all zeroes */ }
  332. };
  333. MODULE_DEVICE_TABLE(pci, pci_ids);
  334. /* pci driver glue; this is a "new style" PCI driver module */
  335. static struct pci_driver xhci_pci_driver = {
  336. .name = (char *) hcd_name,
  337. .id_table = pci_ids,
  338. .probe = xhci_pci_probe,
  339. .remove = xhci_pci_remove,
  340. /* suspend and resume implemented later */
  341. .shutdown = usb_hcd_pci_shutdown,
  342. #ifdef CONFIG_PM
  343. .driver = {
  344. .pm = &usb_hcd_pci_pm_ops
  345. },
  346. #endif
  347. };
  348. int __init xhci_register_pci(void)
  349. {
  350. return pci_register_driver(&xhci_pci_driver);
  351. }
  352. void xhci_unregister_pci(void)
  353. {
  354. pci_unregister_driver(&xhci_pci_driver);
  355. }