omap_drv.c 19 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/sys_soc.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include "omap_dmm_tiler.h"
  25. #include "omap_drv.h"
  26. #define DRIVER_NAME MODULE_NAME
  27. #define DRIVER_DESC "OMAP DRM"
  28. #define DRIVER_DATE "20110917"
  29. #define DRIVER_MAJOR 1
  30. #define DRIVER_MINOR 0
  31. #define DRIVER_PATCHLEVEL 0
  32. /*
  33. * mode config funcs
  34. */
  35. /* Notes about mapping DSS and DRM entities:
  36. * CRTC: overlay
  37. * encoder: manager.. with some extension to allow one primary CRTC
  38. * and zero or more video CRTC's to be mapped to one encoder?
  39. * connector: dssdev.. manager can be attached/detached from different
  40. * devices
  41. */
  42. static void omap_fb_output_poll_changed(struct drm_device *dev)
  43. {
  44. struct omap_drm_private *priv = dev->dev_private;
  45. DBG("dev=%p", dev);
  46. if (priv->fbdev)
  47. drm_fb_helper_hotplug_event(priv->fbdev);
  48. }
  49. static void omap_atomic_wait_for_completion(struct drm_device *dev,
  50. struct drm_atomic_state *old_state)
  51. {
  52. struct drm_crtc_state *new_crtc_state;
  53. struct drm_crtc *crtc;
  54. unsigned int i;
  55. int ret;
  56. for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
  57. if (!new_crtc_state->active)
  58. continue;
  59. ret = omap_crtc_wait_pending(crtc);
  60. if (!ret)
  61. dev_warn(dev->dev,
  62. "atomic complete timeout (pipe %u)!\n", i);
  63. }
  64. }
  65. static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  66. {
  67. struct drm_device *dev = old_state->dev;
  68. struct omap_drm_private *priv = dev->dev_private;
  69. priv->dispc_ops->runtime_get();
  70. /* Apply the atomic update. */
  71. drm_atomic_helper_commit_modeset_disables(dev, old_state);
  72. /* With the current dss dispc implementation we have to enable
  73. * the new modeset before we can commit planes. The dispc ovl
  74. * configuration relies on the video mode configuration been
  75. * written into the HW when the ovl configuration is
  76. * calculated.
  77. *
  78. * This approach is not ideal because after a mode change the
  79. * plane update is executed only after the first vblank
  80. * interrupt. The dispc implementation should be fixed so that
  81. * it is able use uncommitted drm state information.
  82. */
  83. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  84. omap_atomic_wait_for_completion(dev, old_state);
  85. drm_atomic_helper_commit_planes(dev, old_state, 0);
  86. drm_atomic_helper_commit_hw_done(old_state);
  87. /*
  88. * Wait for completion of the page flips to ensure that old buffers
  89. * can't be touched by the hardware anymore before cleaning up planes.
  90. */
  91. omap_atomic_wait_for_completion(dev, old_state);
  92. drm_atomic_helper_cleanup_planes(dev, old_state);
  93. priv->dispc_ops->runtime_put();
  94. }
  95. static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
  96. .atomic_commit_tail = omap_atomic_commit_tail,
  97. };
  98. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  99. .fb_create = omap_framebuffer_create,
  100. .output_poll_changed = omap_fb_output_poll_changed,
  101. .atomic_check = drm_atomic_helper_check,
  102. .atomic_commit = drm_atomic_helper_commit,
  103. };
  104. static int get_connector_type(struct omap_dss_device *dssdev)
  105. {
  106. switch (dssdev->type) {
  107. case OMAP_DISPLAY_TYPE_HDMI:
  108. return DRM_MODE_CONNECTOR_HDMIA;
  109. case OMAP_DISPLAY_TYPE_DVI:
  110. return DRM_MODE_CONNECTOR_DVID;
  111. case OMAP_DISPLAY_TYPE_DSI:
  112. return DRM_MODE_CONNECTOR_DSI;
  113. case OMAP_DISPLAY_TYPE_DPI:
  114. case OMAP_DISPLAY_TYPE_DBI:
  115. return DRM_MODE_CONNECTOR_DPI;
  116. case OMAP_DISPLAY_TYPE_VENC:
  117. /* TODO: This could also be composite */
  118. return DRM_MODE_CONNECTOR_SVIDEO;
  119. case OMAP_DISPLAY_TYPE_SDI:
  120. return DRM_MODE_CONNECTOR_LVDS;
  121. default:
  122. return DRM_MODE_CONNECTOR_Unknown;
  123. }
  124. }
  125. static void omap_disconnect_dssdevs(void)
  126. {
  127. struct omap_dss_device *dssdev = NULL;
  128. for_each_dss_dev(dssdev)
  129. dssdev->driver->disconnect(dssdev);
  130. }
  131. static int omap_connect_dssdevs(void)
  132. {
  133. int r;
  134. struct omap_dss_device *dssdev = NULL;
  135. if (!omapdss_stack_is_ready())
  136. return -EPROBE_DEFER;
  137. for_each_dss_dev(dssdev) {
  138. r = dssdev->driver->connect(dssdev);
  139. if (r == -EPROBE_DEFER) {
  140. omap_dss_put_device(dssdev);
  141. goto cleanup;
  142. } else if (r) {
  143. dev_warn(dssdev->dev, "could not connect display: %s\n",
  144. dssdev->name);
  145. }
  146. }
  147. return 0;
  148. cleanup:
  149. /*
  150. * if we are deferring probe, we disconnect the devices we previously
  151. * connected
  152. */
  153. omap_disconnect_dssdevs();
  154. return r;
  155. }
  156. static int omap_modeset_init_properties(struct drm_device *dev)
  157. {
  158. struct omap_drm_private *priv = dev->dev_private;
  159. unsigned int num_planes = priv->dispc_ops->get_num_ovls();
  160. priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
  161. num_planes - 1);
  162. if (!priv->zorder_prop)
  163. return -ENOMEM;
  164. return 0;
  165. }
  166. static int omap_modeset_init(struct drm_device *dev)
  167. {
  168. struct omap_drm_private *priv = dev->dev_private;
  169. struct omap_dss_device *dssdev = NULL;
  170. int num_ovls = priv->dispc_ops->get_num_ovls();
  171. int num_mgrs = priv->dispc_ops->get_num_mgrs();
  172. int num_crtcs, crtc_idx, plane_idx;
  173. int ret;
  174. u32 plane_crtc_mask;
  175. drm_mode_config_init(dev);
  176. ret = omap_modeset_init_properties(dev);
  177. if (ret < 0)
  178. return ret;
  179. /*
  180. * This function creates exactly one connector, encoder, crtc,
  181. * and primary plane per each connected dss-device. Each
  182. * connector->encoder->crtc chain is expected to be separate
  183. * and each crtc is connect to a single dss-channel. If the
  184. * configuration does not match the expectations or exceeds
  185. * the available resources, the configuration is rejected.
  186. */
  187. num_crtcs = 0;
  188. for_each_dss_dev(dssdev)
  189. if (omapdss_device_is_connected(dssdev))
  190. num_crtcs++;
  191. if (num_crtcs > num_mgrs || num_crtcs > num_ovls ||
  192. num_crtcs > ARRAY_SIZE(priv->crtcs) ||
  193. num_crtcs > ARRAY_SIZE(priv->planes) ||
  194. num_crtcs > ARRAY_SIZE(priv->encoders) ||
  195. num_crtcs > ARRAY_SIZE(priv->connectors)) {
  196. dev_err(dev->dev, "%s(): Too many connected displays\n",
  197. __func__);
  198. return -EINVAL;
  199. }
  200. /* All planes can be put to any CRTC */
  201. plane_crtc_mask = (1 << num_crtcs) - 1;
  202. dssdev = NULL;
  203. crtc_idx = 0;
  204. plane_idx = 0;
  205. for_each_dss_dev(dssdev) {
  206. struct drm_connector *connector;
  207. struct drm_encoder *encoder;
  208. struct drm_plane *plane;
  209. struct drm_crtc *crtc;
  210. if (!omapdss_device_is_connected(dssdev))
  211. continue;
  212. encoder = omap_encoder_init(dev, dssdev);
  213. if (!encoder)
  214. return -ENOMEM;
  215. connector = omap_connector_init(dev,
  216. get_connector_type(dssdev), dssdev, encoder);
  217. if (!connector)
  218. return -ENOMEM;
  219. plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY,
  220. plane_crtc_mask);
  221. if (IS_ERR(plane))
  222. return PTR_ERR(plane);
  223. crtc = omap_crtc_init(dev, plane, dssdev);
  224. if (IS_ERR(crtc))
  225. return PTR_ERR(crtc);
  226. drm_mode_connector_attach_encoder(connector, encoder);
  227. encoder->possible_crtcs = (1 << crtc_idx);
  228. priv->crtcs[priv->num_crtcs++] = crtc;
  229. priv->planes[priv->num_planes++] = plane;
  230. priv->encoders[priv->num_encoders++] = encoder;
  231. priv->connectors[priv->num_connectors++] = connector;
  232. plane_idx++;
  233. crtc_idx++;
  234. }
  235. /*
  236. * Create normal planes for the remaining overlays:
  237. */
  238. for (; plane_idx < num_ovls; plane_idx++) {
  239. struct drm_plane *plane;
  240. if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
  241. return -EINVAL;
  242. plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY,
  243. plane_crtc_mask);
  244. if (IS_ERR(plane))
  245. return PTR_ERR(plane);
  246. priv->planes[priv->num_planes++] = plane;
  247. }
  248. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  249. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  250. priv->num_connectors);
  251. dev->mode_config.min_width = 8;
  252. dev->mode_config.min_height = 2;
  253. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  254. * to fill in these limits properly on different OMAP generations..
  255. */
  256. dev->mode_config.max_width = 2048;
  257. dev->mode_config.max_height = 2048;
  258. dev->mode_config.funcs = &omap_mode_config_funcs;
  259. dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
  260. drm_mode_config_reset(dev);
  261. omap_drm_irq_install(dev);
  262. return 0;
  263. }
  264. /*
  265. * Enable the HPD in external components if supported
  266. */
  267. static void omap_modeset_enable_external_hpd(void)
  268. {
  269. struct omap_dss_device *dssdev = NULL;
  270. for_each_dss_dev(dssdev) {
  271. if (dssdev->driver->enable_hpd)
  272. dssdev->driver->enable_hpd(dssdev);
  273. }
  274. }
  275. /*
  276. * Disable the HPD in external components if supported
  277. */
  278. static void omap_modeset_disable_external_hpd(void)
  279. {
  280. struct omap_dss_device *dssdev = NULL;
  281. for_each_dss_dev(dssdev) {
  282. if (dssdev->driver->disable_hpd)
  283. dssdev->driver->disable_hpd(dssdev);
  284. }
  285. }
  286. /*
  287. * drm ioctl funcs
  288. */
  289. static int ioctl_get_param(struct drm_device *dev, void *data,
  290. struct drm_file *file_priv)
  291. {
  292. struct omap_drm_private *priv = dev->dev_private;
  293. struct drm_omap_param *args = data;
  294. DBG("%p: param=%llu", dev, args->param);
  295. switch (args->param) {
  296. case OMAP_PARAM_CHIPSET_ID:
  297. args->value = priv->omaprev;
  298. break;
  299. default:
  300. DBG("unknown parameter %lld", args->param);
  301. return -EINVAL;
  302. }
  303. return 0;
  304. }
  305. static int ioctl_set_param(struct drm_device *dev, void *data,
  306. struct drm_file *file_priv)
  307. {
  308. struct drm_omap_param *args = data;
  309. switch (args->param) {
  310. default:
  311. DBG("unknown parameter %lld", args->param);
  312. return -EINVAL;
  313. }
  314. return 0;
  315. }
  316. #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
  317. static int ioctl_gem_new(struct drm_device *dev, void *data,
  318. struct drm_file *file_priv)
  319. {
  320. struct drm_omap_gem_new *args = data;
  321. u32 flags = args->flags & OMAP_BO_USER_MASK;
  322. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  323. args->size.bytes, flags);
  324. return omap_gem_new_handle(dev, file_priv, args->size, flags,
  325. &args->handle);
  326. }
  327. static int ioctl_gem_info(struct drm_device *dev, void *data,
  328. struct drm_file *file_priv)
  329. {
  330. struct drm_omap_gem_info *args = data;
  331. struct drm_gem_object *obj;
  332. int ret = 0;
  333. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  334. obj = drm_gem_object_lookup(file_priv, args->handle);
  335. if (!obj)
  336. return -ENOENT;
  337. args->size = omap_gem_mmap_size(obj);
  338. args->offset = omap_gem_mmap_offset(obj);
  339. drm_gem_object_unreference_unlocked(obj);
  340. return ret;
  341. }
  342. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  343. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
  344. DRM_AUTH | DRM_RENDER_ALLOW),
  345. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
  346. DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
  347. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
  348. DRM_AUTH | DRM_RENDER_ALLOW),
  349. /* Deprecated, to be removed. */
  350. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
  351. DRM_AUTH | DRM_RENDER_ALLOW),
  352. /* Deprecated, to be removed. */
  353. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
  354. DRM_AUTH | DRM_RENDER_ALLOW),
  355. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
  356. DRM_AUTH | DRM_RENDER_ALLOW),
  357. };
  358. /*
  359. * drm driver funcs
  360. */
  361. static int dev_open(struct drm_device *dev, struct drm_file *file)
  362. {
  363. file->driver_priv = NULL;
  364. DBG("open: dev=%p, file=%p", dev, file);
  365. return 0;
  366. }
  367. /**
  368. * lastclose - clean up after all DRM clients have exited
  369. * @dev: DRM device
  370. *
  371. * Take care of cleaning up after all DRM clients have exited. In the
  372. * mode setting case, we want to restore the kernel's initial mode (just
  373. * in case the last client left us in a bad state).
  374. */
  375. static void dev_lastclose(struct drm_device *dev)
  376. {
  377. int i;
  378. /* we don't support vga_switcheroo.. so just make sure the fbdev
  379. * mode is active
  380. */
  381. struct omap_drm_private *priv = dev->dev_private;
  382. int ret;
  383. DBG("lastclose: dev=%p", dev);
  384. /* need to restore default rotation state.. not sure
  385. * if there is a cleaner way to restore properties to
  386. * default state? Maybe a flag that properties should
  387. * automatically be restored to default state on
  388. * lastclose?
  389. */
  390. for (i = 0; i < priv->num_crtcs; i++) {
  391. struct drm_crtc *crtc = priv->crtcs[i];
  392. if (!crtc->primary->rotation_property)
  393. continue;
  394. drm_object_property_set_value(&crtc->base,
  395. crtc->primary->rotation_property,
  396. DRM_MODE_ROTATE_0);
  397. }
  398. for (i = 0; i < priv->num_planes; i++) {
  399. struct drm_plane *plane = priv->planes[i];
  400. if (!plane->rotation_property)
  401. continue;
  402. drm_object_property_set_value(&plane->base,
  403. plane->rotation_property,
  404. DRM_MODE_ROTATE_0);
  405. }
  406. if (priv->fbdev) {
  407. ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  408. if (ret)
  409. DBG("failed to restore crtc mode");
  410. }
  411. }
  412. static const struct vm_operations_struct omap_gem_vm_ops = {
  413. .fault = omap_gem_fault,
  414. .open = drm_gem_vm_open,
  415. .close = drm_gem_vm_close,
  416. };
  417. static const struct file_operations omapdriver_fops = {
  418. .owner = THIS_MODULE,
  419. .open = drm_open,
  420. .unlocked_ioctl = drm_ioctl,
  421. .compat_ioctl = drm_compat_ioctl,
  422. .release = drm_release,
  423. .mmap = omap_gem_mmap,
  424. .poll = drm_poll,
  425. .read = drm_read,
  426. .llseek = noop_llseek,
  427. };
  428. static struct drm_driver omap_drm_driver = {
  429. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  430. DRIVER_ATOMIC | DRIVER_RENDER,
  431. .open = dev_open,
  432. .lastclose = dev_lastclose,
  433. #ifdef CONFIG_DEBUG_FS
  434. .debugfs_init = omap_debugfs_init,
  435. #endif
  436. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  437. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  438. .gem_prime_export = omap_gem_prime_export,
  439. .gem_prime_import = omap_gem_prime_import,
  440. .gem_free_object = omap_gem_free_object,
  441. .gem_vm_ops = &omap_gem_vm_ops,
  442. .dumb_create = omap_gem_dumb_create,
  443. .dumb_map_offset = omap_gem_dumb_map_offset,
  444. .ioctls = ioctls,
  445. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  446. .fops = &omapdriver_fops,
  447. .name = DRIVER_NAME,
  448. .desc = DRIVER_DESC,
  449. .date = DRIVER_DATE,
  450. .major = DRIVER_MAJOR,
  451. .minor = DRIVER_MINOR,
  452. .patchlevel = DRIVER_PATCHLEVEL,
  453. };
  454. static const struct soc_device_attribute omapdrm_soc_devices[] = {
  455. { .family = "OMAP3", .data = (void *)0x3430 },
  456. { .family = "OMAP4", .data = (void *)0x4430 },
  457. { .family = "OMAP5", .data = (void *)0x5430 },
  458. { .family = "DRA7", .data = (void *)0x0752 },
  459. { /* sentinel */ }
  460. };
  461. static int pdev_probe(struct platform_device *pdev)
  462. {
  463. const struct soc_device_attribute *soc;
  464. struct omap_drm_private *priv;
  465. struct drm_device *ddev;
  466. unsigned int i;
  467. int ret;
  468. DBG("%s", pdev->name);
  469. if (omapdss_is_initialized() == false)
  470. return -EPROBE_DEFER;
  471. omap_crtc_pre_init();
  472. ret = omap_connect_dssdevs();
  473. if (ret)
  474. goto err_crtc_uninit;
  475. /* Allocate and initialize the driver private structure. */
  476. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  477. if (!priv) {
  478. ret = -ENOMEM;
  479. goto err_disconnect_dssdevs;
  480. }
  481. priv->dispc_ops = dispc_get_ops();
  482. soc = soc_device_match(omapdrm_soc_devices);
  483. priv->omaprev = soc ? (unsigned int)soc->data : 0;
  484. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  485. spin_lock_init(&priv->list_lock);
  486. INIT_LIST_HEAD(&priv->obj_list);
  487. /* Allocate and initialize the DRM device. */
  488. ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev);
  489. if (IS_ERR(ddev)) {
  490. ret = PTR_ERR(ddev);
  491. goto err_free_priv;
  492. }
  493. ddev->dev_private = priv;
  494. platform_set_drvdata(pdev, ddev);
  495. omap_gem_init(ddev);
  496. ret = omap_modeset_init(ddev);
  497. if (ret) {
  498. dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  499. goto err_free_drm_dev;
  500. }
  501. /* Initialize vblank handling, start with all CRTCs disabled. */
  502. ret = drm_vblank_init(ddev, priv->num_crtcs);
  503. if (ret) {
  504. dev_err(&pdev->dev, "could not init vblank\n");
  505. goto err_cleanup_modeset;
  506. }
  507. for (i = 0; i < priv->num_crtcs; i++)
  508. drm_crtc_vblank_off(priv->crtcs[i]);
  509. priv->fbdev = omap_fbdev_init(ddev);
  510. drm_kms_helper_poll_init(ddev);
  511. omap_modeset_enable_external_hpd();
  512. /*
  513. * Register the DRM device with the core and the connectors with
  514. * sysfs.
  515. */
  516. ret = drm_dev_register(ddev, 0);
  517. if (ret)
  518. goto err_cleanup_helpers;
  519. return 0;
  520. err_cleanup_helpers:
  521. omap_modeset_disable_external_hpd();
  522. drm_kms_helper_poll_fini(ddev);
  523. if (priv->fbdev)
  524. omap_fbdev_free(ddev);
  525. err_cleanup_modeset:
  526. drm_mode_config_cleanup(ddev);
  527. omap_drm_irq_uninstall(ddev);
  528. err_free_drm_dev:
  529. omap_gem_deinit(ddev);
  530. drm_dev_unref(ddev);
  531. err_free_priv:
  532. destroy_workqueue(priv->wq);
  533. kfree(priv);
  534. err_disconnect_dssdevs:
  535. omap_disconnect_dssdevs();
  536. err_crtc_uninit:
  537. omap_crtc_pre_uninit();
  538. return ret;
  539. }
  540. static int pdev_remove(struct platform_device *pdev)
  541. {
  542. struct drm_device *ddev = platform_get_drvdata(pdev);
  543. struct omap_drm_private *priv = ddev->dev_private;
  544. DBG("");
  545. drm_dev_unregister(ddev);
  546. omap_modeset_disable_external_hpd();
  547. drm_kms_helper_poll_fini(ddev);
  548. if (priv->fbdev)
  549. omap_fbdev_free(ddev);
  550. drm_atomic_helper_shutdown(ddev);
  551. drm_mode_config_cleanup(ddev);
  552. omap_drm_irq_uninstall(ddev);
  553. omap_gem_deinit(ddev);
  554. drm_dev_unref(ddev);
  555. destroy_workqueue(priv->wq);
  556. kfree(priv);
  557. omap_disconnect_dssdevs();
  558. omap_crtc_pre_uninit();
  559. return 0;
  560. }
  561. #ifdef CONFIG_PM_SLEEP
  562. static int omap_drm_suspend_all_displays(void)
  563. {
  564. struct omap_dss_device *dssdev = NULL;
  565. for_each_dss_dev(dssdev) {
  566. if (!dssdev->driver)
  567. continue;
  568. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  569. dssdev->driver->disable(dssdev);
  570. dssdev->activate_after_resume = true;
  571. } else {
  572. dssdev->activate_after_resume = false;
  573. }
  574. }
  575. return 0;
  576. }
  577. static int omap_drm_resume_all_displays(void)
  578. {
  579. struct omap_dss_device *dssdev = NULL;
  580. for_each_dss_dev(dssdev) {
  581. if (!dssdev->driver)
  582. continue;
  583. if (dssdev->activate_after_resume) {
  584. dssdev->driver->enable(dssdev);
  585. dssdev->activate_after_resume = false;
  586. }
  587. }
  588. return 0;
  589. }
  590. static int omap_drm_suspend(struct device *dev)
  591. {
  592. struct drm_device *drm_dev = dev_get_drvdata(dev);
  593. drm_kms_helper_poll_disable(drm_dev);
  594. drm_modeset_lock_all(drm_dev);
  595. omap_drm_suspend_all_displays();
  596. drm_modeset_unlock_all(drm_dev);
  597. return 0;
  598. }
  599. static int omap_drm_resume(struct device *dev)
  600. {
  601. struct drm_device *drm_dev = dev_get_drvdata(dev);
  602. drm_modeset_lock_all(drm_dev);
  603. omap_drm_resume_all_displays();
  604. drm_modeset_unlock_all(drm_dev);
  605. drm_kms_helper_poll_enable(drm_dev);
  606. return omap_gem_resume(dev);
  607. }
  608. #endif
  609. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  610. static struct platform_driver pdev = {
  611. .driver = {
  612. .name = DRIVER_NAME,
  613. .pm = &omapdrm_pm_ops,
  614. },
  615. .probe = pdev_probe,
  616. .remove = pdev_remove,
  617. };
  618. static struct platform_driver * const drivers[] = {
  619. &omap_dmm_driver,
  620. &pdev,
  621. };
  622. static int __init omap_drm_init(void)
  623. {
  624. DBG("init");
  625. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  626. }
  627. static void __exit omap_drm_fini(void)
  628. {
  629. DBG("fini");
  630. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  631. }
  632. /* need late_initcall() so we load after dss_driver's are loaded */
  633. late_initcall(omap_drm_init);
  634. module_exit(omap_drm_fini);
  635. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  636. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  637. MODULE_ALIAS("platform:" DRIVER_NAME);
  638. MODULE_LICENSE("GPL v2");