kmcoge4.dts 3.6 KB

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  1. /*
  2. * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
  3. *
  4. * (C) Copyright 2014
  5. * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
  6. *
  7. * Copyright 2011 Freescale Semiconductor Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. /include/ "p2041si-pre.dtsi"
  15. / {
  16. model = "keymile,kmcoge4";
  17. compatible = "keymile,kmcoge4", "keymile,kmp204x";
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20. interrupt-parent = <&mpic>;
  21. memory {
  22. device_type = "memory";
  23. };
  24. reserved-memory {
  25. #address-cells = <2>;
  26. #size-cells = <2>;
  27. ranges;
  28. bman_fbpr: bman-fbpr {
  29. size = <0 0x1000000>;
  30. alignment = <0 0x1000000>;
  31. };
  32. qman_fqd: qman-fqd {
  33. size = <0 0x400000>;
  34. alignment = <0 0x400000>;
  35. };
  36. qman_pfdr: qman-pfdr {
  37. size = <0 0x2000000>;
  38. alignment = <0 0x2000000>;
  39. };
  40. };
  41. dcsr: dcsr@f00000000 {
  42. ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  43. };
  44. bportals: bman-portals@ff4000000 {
  45. ranges = <0x0 0xf 0xf4000000 0x200000>;
  46. };
  47. qportals: qman-portals@ff4200000 {
  48. ranges = <0x0 0xf 0xf4200000 0x200000>;
  49. };
  50. soc: soc@ffe000000 {
  51. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  52. reg = <0xf 0xfe000000 0 0x00001000>;
  53. spi@110000 {
  54. flash@0 {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "spansion,s25fl256s1";
  58. reg = <0>;
  59. spi-max-frequency = <20000000>; /* input clock */
  60. };
  61. network_clock@1 {
  62. compatible = "zarlink,zl30343";
  63. reg = <1>;
  64. spi-max-frequency = <8000000>;
  65. };
  66. flash@2 {
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. compatible = "micron,m25p32";
  70. reg = <2>;
  71. spi-max-frequency = <15000000>;
  72. };
  73. };
  74. i2c@119000 {
  75. status = "disabled";
  76. };
  77. i2c@119100 {
  78. status = "disabled";
  79. };
  80. usb0: usb@210000 {
  81. status = "disabled";
  82. };
  83. usb1: usb@211000 {
  84. status = "disabled";
  85. };
  86. sata@220000 {
  87. status = "disabled";
  88. };
  89. sata@221000 {
  90. status = "disabled";
  91. };
  92. };
  93. rio: rapidio@ffe0c0000 {
  94. status = "disabled";
  95. };
  96. lbc: localbus@ffe124000 {
  97. reg = <0xf 0xfe124000 0 0x1000>;
  98. ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
  99. 1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
  100. 2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
  101. 3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
  102. nand@0,0 {
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. compatible = "fsl,elbc-fcm-nand";
  106. reg = <0 0 0x40000>;
  107. };
  108. board-control@1,0 {
  109. compatible = "keymile,qriox";
  110. reg = <1 0 0x80>;
  111. };
  112. chassis-mgmt@3,0 {
  113. compatible = "keymile,bfticu";
  114. interrupt-controller;
  115. #interrupt-cells = <2>;
  116. reg = <3 0 0x100>;
  117. interrupt-parent = <&mpic>;
  118. interrupts = <6 1 0 0>;
  119. };
  120. };
  121. pci0: pcie@ffe200000 {
  122. reg = <0xf 0xfe200000 0 0x1000>;
  123. ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
  124. 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
  125. pcie@0 {
  126. ranges = <0x02000000 0 0xe0000000
  127. 0x02000000 0 0xe0000000
  128. 0 0x20000000
  129. 0x01000000 0 0x00000000
  130. 0x01000000 0 0x00000000
  131. 0 0x00010000>;
  132. };
  133. };
  134. pci1: pcie@ffe201000 {
  135. status = "disabled";
  136. };
  137. pci2: pcie@ffe202000 {
  138. reg = <0xf 0xfe202000 0 0x1000>;
  139. ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
  140. 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
  141. pcie@0 {
  142. ranges = <0x02000000 0 0xe0000000
  143. 0x02000000 0 0xe0000000
  144. 0 0x20000000
  145. 0x01000000 0 0x00000000
  146. 0x01000000 0 0x00000000
  147. 0 0x00010000>;
  148. };
  149. };
  150. };
  151. /include/ "p2041si-post.dtsi"