r8152.c 97 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. /* Information for net-next */
  28. #define NETNEXT_VERSION "08"
  29. /* Information for net */
  30. #define NET_VERSION "2"
  31. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  32. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  33. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  34. #define MODULENAME "r8152"
  35. #define R8152_PHY_ID 32
  36. #define PLA_IDR 0xc000
  37. #define PLA_RCR 0xc010
  38. #define PLA_RMS 0xc016
  39. #define PLA_RXFIFO_CTRL0 0xc0a0
  40. #define PLA_RXFIFO_CTRL1 0xc0a4
  41. #define PLA_RXFIFO_CTRL2 0xc0a8
  42. #define PLA_DMY_REG0 0xc0b0
  43. #define PLA_FMC 0xc0b4
  44. #define PLA_CFG_WOL 0xc0b6
  45. #define PLA_TEREDO_CFG 0xc0bc
  46. #define PLA_MAR 0xcd00
  47. #define PLA_BACKUP 0xd000
  48. #define PAL_BDC_CR 0xd1a0
  49. #define PLA_TEREDO_TIMER 0xd2cc
  50. #define PLA_REALWOW_TIMER 0xd2e8
  51. #define PLA_LEDSEL 0xdd90
  52. #define PLA_LED_FEATURE 0xdd92
  53. #define PLA_PHYAR 0xde00
  54. #define PLA_BOOT_CTRL 0xe004
  55. #define PLA_GPHY_INTR_IMR 0xe022
  56. #define PLA_EEE_CR 0xe040
  57. #define PLA_EEEP_CR 0xe080
  58. #define PLA_MAC_PWR_CTRL 0xe0c0
  59. #define PLA_MAC_PWR_CTRL2 0xe0ca
  60. #define PLA_MAC_PWR_CTRL3 0xe0cc
  61. #define PLA_MAC_PWR_CTRL4 0xe0ce
  62. #define PLA_WDT6_CTRL 0xe428
  63. #define PLA_TCR0 0xe610
  64. #define PLA_TCR1 0xe612
  65. #define PLA_MTPS 0xe615
  66. #define PLA_TXFIFO_CTRL 0xe618
  67. #define PLA_RSTTALLY 0xe800
  68. #define PLA_CR 0xe813
  69. #define PLA_CRWECR 0xe81c
  70. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  71. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  72. #define PLA_CONFIG5 0xe822
  73. #define PLA_PHY_PWR 0xe84c
  74. #define PLA_OOB_CTRL 0xe84f
  75. #define PLA_CPCR 0xe854
  76. #define PLA_MISC_0 0xe858
  77. #define PLA_MISC_1 0xe85a
  78. #define PLA_OCP_GPHY_BASE 0xe86c
  79. #define PLA_TALLYCNT 0xe890
  80. #define PLA_SFF_STS_7 0xe8de
  81. #define PLA_PHYSTATUS 0xe908
  82. #define PLA_BP_BA 0xfc26
  83. #define PLA_BP_0 0xfc28
  84. #define PLA_BP_1 0xfc2a
  85. #define PLA_BP_2 0xfc2c
  86. #define PLA_BP_3 0xfc2e
  87. #define PLA_BP_4 0xfc30
  88. #define PLA_BP_5 0xfc32
  89. #define PLA_BP_6 0xfc34
  90. #define PLA_BP_7 0xfc36
  91. #define PLA_BP_EN 0xfc38
  92. #define USB_USB2PHY 0xb41e
  93. #define USB_SSPHYLINK2 0xb428
  94. #define USB_U2P3_CTRL 0xb460
  95. #define USB_CSR_DUMMY1 0xb464
  96. #define USB_CSR_DUMMY2 0xb466
  97. #define USB_DEV_STAT 0xb808
  98. #define USB_CONNECT_TIMER 0xcbf8
  99. #define USB_BURST_SIZE 0xcfc0
  100. #define USB_USB_CTRL 0xd406
  101. #define USB_PHY_CTRL 0xd408
  102. #define USB_TX_AGG 0xd40a
  103. #define USB_RX_BUF_TH 0xd40c
  104. #define USB_USB_TIMER 0xd428
  105. #define USB_RX_EARLY_TIMEOUT 0xd42c
  106. #define USB_RX_EARLY_SIZE 0xd42e
  107. #define USB_PM_CTRL_STATUS 0xd432
  108. #define USB_TX_DMA 0xd434
  109. #define USB_TOLERANCE 0xd490
  110. #define USB_LPM_CTRL 0xd41a
  111. #define USB_UPS_CTRL 0xd800
  112. #define USB_MISC_0 0xd81a
  113. #define USB_POWER_CUT 0xd80a
  114. #define USB_AFE_CTRL2 0xd824
  115. #define USB_WDT11_CTRL 0xe43c
  116. #define USB_BP_BA 0xfc26
  117. #define USB_BP_0 0xfc28
  118. #define USB_BP_1 0xfc2a
  119. #define USB_BP_2 0xfc2c
  120. #define USB_BP_3 0xfc2e
  121. #define USB_BP_4 0xfc30
  122. #define USB_BP_5 0xfc32
  123. #define USB_BP_6 0xfc34
  124. #define USB_BP_7 0xfc36
  125. #define USB_BP_EN 0xfc38
  126. /* OCP Registers */
  127. #define OCP_ALDPS_CONFIG 0x2010
  128. #define OCP_EEE_CONFIG1 0x2080
  129. #define OCP_EEE_CONFIG2 0x2092
  130. #define OCP_EEE_CONFIG3 0x2094
  131. #define OCP_BASE_MII 0xa400
  132. #define OCP_EEE_AR 0xa41a
  133. #define OCP_EEE_DATA 0xa41c
  134. #define OCP_PHY_STATUS 0xa420
  135. #define OCP_POWER_CFG 0xa430
  136. #define OCP_EEE_CFG 0xa432
  137. #define OCP_SRAM_ADDR 0xa436
  138. #define OCP_SRAM_DATA 0xa438
  139. #define OCP_DOWN_SPEED 0xa442
  140. #define OCP_EEE_ABLE 0xa5c4
  141. #define OCP_EEE_ADV 0xa5d0
  142. #define OCP_EEE_LPABLE 0xa5d2
  143. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  144. #define OCP_ADC_CFG 0xbc06
  145. /* SRAM Register */
  146. #define SRAM_LPF_CFG 0x8012
  147. #define SRAM_10M_AMP1 0x8080
  148. #define SRAM_10M_AMP2 0x8082
  149. #define SRAM_IMPEDANCE 0x8084
  150. /* PLA_RCR */
  151. #define RCR_AAP 0x00000001
  152. #define RCR_APM 0x00000002
  153. #define RCR_AM 0x00000004
  154. #define RCR_AB 0x00000008
  155. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  156. /* PLA_RXFIFO_CTRL0 */
  157. #define RXFIFO_THR1_NORMAL 0x00080002
  158. #define RXFIFO_THR1_OOB 0x01800003
  159. /* PLA_RXFIFO_CTRL1 */
  160. #define RXFIFO_THR2_FULL 0x00000060
  161. #define RXFIFO_THR2_HIGH 0x00000038
  162. #define RXFIFO_THR2_OOB 0x0000004a
  163. #define RXFIFO_THR2_NORMAL 0x00a0
  164. /* PLA_RXFIFO_CTRL2 */
  165. #define RXFIFO_THR3_FULL 0x00000078
  166. #define RXFIFO_THR3_HIGH 0x00000048
  167. #define RXFIFO_THR3_OOB 0x0000005a
  168. #define RXFIFO_THR3_NORMAL 0x0110
  169. /* PLA_TXFIFO_CTRL */
  170. #define TXFIFO_THR_NORMAL 0x00400008
  171. #define TXFIFO_THR_NORMAL2 0x01000008
  172. /* PLA_DMY_REG0 */
  173. #define ECM_ALDPS 0x0002
  174. /* PLA_FMC */
  175. #define FMC_FCR_MCU_EN 0x0001
  176. /* PLA_EEEP_CR */
  177. #define EEEP_CR_EEEP_TX 0x0002
  178. /* PLA_WDT6_CTRL */
  179. #define WDT6_SET_MODE 0x0010
  180. /* PLA_TCR0 */
  181. #define TCR0_TX_EMPTY 0x0800
  182. #define TCR0_AUTO_FIFO 0x0080
  183. /* PLA_TCR1 */
  184. #define VERSION_MASK 0x7cf0
  185. /* PLA_MTPS */
  186. #define MTPS_JUMBO (12 * 1024 / 64)
  187. #define MTPS_DEFAULT (6 * 1024 / 64)
  188. /* PLA_RSTTALLY */
  189. #define TALLY_RESET 0x0001
  190. /* PLA_CR */
  191. #define CR_RST 0x10
  192. #define CR_RE 0x08
  193. #define CR_TE 0x04
  194. /* PLA_CRWECR */
  195. #define CRWECR_NORAML 0x00
  196. #define CRWECR_CONFIG 0xc0
  197. /* PLA_OOB_CTRL */
  198. #define NOW_IS_OOB 0x80
  199. #define TXFIFO_EMPTY 0x20
  200. #define RXFIFO_EMPTY 0x10
  201. #define LINK_LIST_READY 0x02
  202. #define DIS_MCU_CLROOB 0x01
  203. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  204. /* PLA_MISC_1 */
  205. #define RXDY_GATED_EN 0x0008
  206. /* PLA_SFF_STS_7 */
  207. #define RE_INIT_LL 0x8000
  208. #define MCU_BORW_EN 0x4000
  209. /* PLA_CPCR */
  210. #define CPCR_RX_VLAN 0x0040
  211. /* PLA_CFG_WOL */
  212. #define MAGIC_EN 0x0001
  213. /* PLA_TEREDO_CFG */
  214. #define TEREDO_SEL 0x8000
  215. #define TEREDO_WAKE_MASK 0x7f00
  216. #define TEREDO_RS_EVENT_MASK 0x00fe
  217. #define OOB_TEREDO_EN 0x0001
  218. /* PAL_BDC_CR */
  219. #define ALDPS_PROXY_MODE 0x0001
  220. /* PLA_CONFIG34 */
  221. #define LINK_ON_WAKE_EN 0x0010
  222. #define LINK_OFF_WAKE_EN 0x0008
  223. /* PLA_CONFIG5 */
  224. #define BWF_EN 0x0040
  225. #define MWF_EN 0x0020
  226. #define UWF_EN 0x0010
  227. #define LAN_WAKE_EN 0x0002
  228. /* PLA_LED_FEATURE */
  229. #define LED_MODE_MASK 0x0700
  230. /* PLA_PHY_PWR */
  231. #define TX_10M_IDLE_EN 0x0080
  232. #define PFM_PWM_SWITCH 0x0040
  233. /* PLA_MAC_PWR_CTRL */
  234. #define D3_CLK_GATED_EN 0x00004000
  235. #define MCU_CLK_RATIO 0x07010f07
  236. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  237. #define ALDPS_SPDWN_RATIO 0x0f87
  238. /* PLA_MAC_PWR_CTRL2 */
  239. #define EEE_SPDWN_RATIO 0x8007
  240. /* PLA_MAC_PWR_CTRL3 */
  241. #define PKT_AVAIL_SPDWN_EN 0x0100
  242. #define SUSPEND_SPDWN_EN 0x0004
  243. #define U1U2_SPDWN_EN 0x0002
  244. #define L1_SPDWN_EN 0x0001
  245. /* PLA_MAC_PWR_CTRL4 */
  246. #define PWRSAVE_SPDWN_EN 0x1000
  247. #define RXDV_SPDWN_EN 0x0800
  248. #define TX10MIDLE_EN 0x0100
  249. #define TP100_SPDWN_EN 0x0020
  250. #define TP500_SPDWN_EN 0x0010
  251. #define TP1000_SPDWN_EN 0x0008
  252. #define EEE_SPDWN_EN 0x0001
  253. /* PLA_GPHY_INTR_IMR */
  254. #define GPHY_STS_MSK 0x0001
  255. #define SPEED_DOWN_MSK 0x0002
  256. #define SPDWN_RXDV_MSK 0x0004
  257. #define SPDWN_LINKCHG_MSK 0x0008
  258. /* PLA_PHYAR */
  259. #define PHYAR_FLAG 0x80000000
  260. /* PLA_EEE_CR */
  261. #define EEE_RX_EN 0x0001
  262. #define EEE_TX_EN 0x0002
  263. /* PLA_BOOT_CTRL */
  264. #define AUTOLOAD_DONE 0x0002
  265. /* USB_USB2PHY */
  266. #define USB2PHY_SUSPEND 0x0001
  267. #define USB2PHY_L1 0x0002
  268. /* USB_SSPHYLINK2 */
  269. #define pwd_dn_scale_mask 0x3ffe
  270. #define pwd_dn_scale(x) ((x) << 1)
  271. /* USB_CSR_DUMMY1 */
  272. #define DYNAMIC_BURST 0x0001
  273. /* USB_CSR_DUMMY2 */
  274. #define EP4_FULL_FC 0x0001
  275. /* USB_DEV_STAT */
  276. #define STAT_SPEED_MASK 0x0006
  277. #define STAT_SPEED_HIGH 0x0000
  278. #define STAT_SPEED_FULL 0x0002
  279. /* USB_TX_AGG */
  280. #define TX_AGG_MAX_THRESHOLD 0x03
  281. /* USB_RX_BUF_TH */
  282. #define RX_THR_SUPPER 0x0c350180
  283. #define RX_THR_HIGH 0x7a120180
  284. #define RX_THR_SLOW 0xffff0180
  285. /* USB_TX_DMA */
  286. #define TEST_MODE_DISABLE 0x00000001
  287. #define TX_SIZE_ADJUST1 0x00000100
  288. /* USB_UPS_CTRL */
  289. #define POWER_CUT 0x0100
  290. /* USB_PM_CTRL_STATUS */
  291. #define RESUME_INDICATE 0x0001
  292. /* USB_USB_CTRL */
  293. #define RX_AGG_DISABLE 0x0010
  294. #define RX_ZERO_EN 0x0080
  295. /* USB_U2P3_CTRL */
  296. #define U2P3_ENABLE 0x0001
  297. /* USB_POWER_CUT */
  298. #define PWR_EN 0x0001
  299. #define PHASE2_EN 0x0008
  300. /* USB_MISC_0 */
  301. #define PCUT_STATUS 0x0001
  302. /* USB_RX_EARLY_TIMEOUT */
  303. #define COALESCE_SUPER 85000U
  304. #define COALESCE_HIGH 250000U
  305. #define COALESCE_SLOW 524280U
  306. /* USB_WDT11_CTRL */
  307. #define TIMER11_EN 0x0001
  308. /* USB_LPM_CTRL */
  309. /* bit 4 ~ 5: fifo empty boundary */
  310. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  311. /* bit 2 ~ 3: LMP timer */
  312. #define LPM_TIMER_MASK 0x0c
  313. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  314. #define LPM_TIMER_500US 0x0c /* 500 us */
  315. #define ROK_EXIT_LPM 0x02
  316. /* USB_AFE_CTRL2 */
  317. #define SEN_VAL_MASK 0xf800
  318. #define SEN_VAL_NORMAL 0xa000
  319. #define SEL_RXIDLE 0x0100
  320. /* OCP_ALDPS_CONFIG */
  321. #define ENPWRSAVE 0x8000
  322. #define ENPDNPS 0x0200
  323. #define LINKENA 0x0100
  324. #define DIS_SDSAVE 0x0010
  325. /* OCP_PHY_STATUS */
  326. #define PHY_STAT_MASK 0x0007
  327. #define PHY_STAT_LAN_ON 3
  328. #define PHY_STAT_PWRDN 5
  329. /* OCP_POWER_CFG */
  330. #define EEE_CLKDIV_EN 0x8000
  331. #define EN_ALDPS 0x0004
  332. #define EN_10M_PLLOFF 0x0001
  333. /* OCP_EEE_CONFIG1 */
  334. #define RG_TXLPI_MSK_HFDUP 0x8000
  335. #define RG_MATCLR_EN 0x4000
  336. #define EEE_10_CAP 0x2000
  337. #define EEE_NWAY_EN 0x1000
  338. #define TX_QUIET_EN 0x0200
  339. #define RX_QUIET_EN 0x0100
  340. #define sd_rise_time_mask 0x0070
  341. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  342. #define RG_RXLPI_MSK_HFDUP 0x0008
  343. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  344. /* OCP_EEE_CONFIG2 */
  345. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  346. #define RG_DACQUIET_EN 0x0400
  347. #define RG_LDVQUIET_EN 0x0200
  348. #define RG_CKRSEL 0x0020
  349. #define RG_EEEPRG_EN 0x0010
  350. /* OCP_EEE_CONFIG3 */
  351. #define fast_snr_mask 0xff80
  352. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  353. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  354. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  355. /* OCP_EEE_AR */
  356. /* bit[15:14] function */
  357. #define FUN_ADDR 0x0000
  358. #define FUN_DATA 0x4000
  359. /* bit[4:0] device addr */
  360. /* OCP_EEE_CFG */
  361. #define CTAP_SHORT_EN 0x0040
  362. #define EEE10_EN 0x0010
  363. /* OCP_DOWN_SPEED */
  364. #define EN_10M_BGOFF 0x0080
  365. /* OCP_PHY_STATE */
  366. #define TXDIS_STATE 0x01
  367. #define ABD_STATE 0x02
  368. /* OCP_ADC_CFG */
  369. #define CKADSEL_L 0x0100
  370. #define ADC_EN 0x0080
  371. #define EN_EMI_L 0x0040
  372. /* SRAM_LPF_CFG */
  373. #define LPF_AUTO_TUNE 0x8000
  374. /* SRAM_10M_AMP1 */
  375. #define GDAC_IB_UPALL 0x0008
  376. /* SRAM_10M_AMP2 */
  377. #define AMP_DN 0x0200
  378. /* SRAM_IMPEDANCE */
  379. #define RX_DRIVING_MASK 0x6000
  380. enum rtl_register_content {
  381. _1000bps = 0x10,
  382. _100bps = 0x08,
  383. _10bps = 0x04,
  384. LINK_STATUS = 0x02,
  385. FULL_DUP = 0x01,
  386. };
  387. #define RTL8152_MAX_TX 4
  388. #define RTL8152_MAX_RX 10
  389. #define INTBUFSIZE 2
  390. #define CRC_SIZE 4
  391. #define TX_ALIGN 4
  392. #define RX_ALIGN 8
  393. #define INTR_LINK 0x0004
  394. #define RTL8152_REQT_READ 0xc0
  395. #define RTL8152_REQT_WRITE 0x40
  396. #define RTL8152_REQ_GET_REGS 0x05
  397. #define RTL8152_REQ_SET_REGS 0x05
  398. #define BYTE_EN_DWORD 0xff
  399. #define BYTE_EN_WORD 0x33
  400. #define BYTE_EN_BYTE 0x11
  401. #define BYTE_EN_SIX_BYTES 0x3f
  402. #define BYTE_EN_START_MASK 0x0f
  403. #define BYTE_EN_END_MASK 0xf0
  404. #define RTL8153_MAX_PACKET 9216 /* 9K */
  405. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  406. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  407. #define RTL8153_RMS RTL8153_MAX_PACKET
  408. #define RTL8152_TX_TIMEOUT (5 * HZ)
  409. #define RTL8152_NAPI_WEIGHT 64
  410. /* rtl8152 flags */
  411. enum rtl8152_flags {
  412. RTL8152_UNPLUG = 0,
  413. RTL8152_SET_RX_MODE,
  414. WORK_ENABLE,
  415. RTL8152_LINK_CHG,
  416. SELECTIVE_SUSPEND,
  417. PHY_RESET,
  418. SCHEDULE_NAPI,
  419. };
  420. /* Define these values to match your device */
  421. #define VENDOR_ID_REALTEK 0x0bda
  422. #define VENDOR_ID_SAMSUNG 0x04e8
  423. #define VENDOR_ID_LENOVO 0x17ef
  424. #define VENDOR_ID_NVIDIA 0x0955
  425. #define MCU_TYPE_PLA 0x0100
  426. #define MCU_TYPE_USB 0x0000
  427. struct tally_counter {
  428. __le64 tx_packets;
  429. __le64 rx_packets;
  430. __le64 tx_errors;
  431. __le32 rx_errors;
  432. __le16 rx_missed;
  433. __le16 align_errors;
  434. __le32 tx_one_collision;
  435. __le32 tx_multi_collision;
  436. __le64 rx_unicast;
  437. __le64 rx_broadcast;
  438. __le32 rx_multicast;
  439. __le16 tx_aborted;
  440. __le16 tx_underrun;
  441. };
  442. struct rx_desc {
  443. __le32 opts1;
  444. #define RX_LEN_MASK 0x7fff
  445. __le32 opts2;
  446. #define RD_UDP_CS BIT(23)
  447. #define RD_TCP_CS BIT(22)
  448. #define RD_IPV6_CS BIT(20)
  449. #define RD_IPV4_CS BIT(19)
  450. __le32 opts3;
  451. #define IPF BIT(23) /* IP checksum fail */
  452. #define UDPF BIT(22) /* UDP checksum fail */
  453. #define TCPF BIT(21) /* TCP checksum fail */
  454. #define RX_VLAN_TAG BIT(16)
  455. __le32 opts4;
  456. __le32 opts5;
  457. __le32 opts6;
  458. };
  459. struct tx_desc {
  460. __le32 opts1;
  461. #define TX_FS BIT(31) /* First segment of a packet */
  462. #define TX_LS BIT(30) /* Final segment of a packet */
  463. #define GTSENDV4 BIT(28)
  464. #define GTSENDV6 BIT(27)
  465. #define GTTCPHO_SHIFT 18
  466. #define GTTCPHO_MAX 0x7fU
  467. #define TX_LEN_MAX 0x3ffffU
  468. __le32 opts2;
  469. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  470. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  471. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  472. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  473. #define MSS_SHIFT 17
  474. #define MSS_MAX 0x7ffU
  475. #define TCPHO_SHIFT 17
  476. #define TCPHO_MAX 0x7ffU
  477. #define TX_VLAN_TAG BIT(16)
  478. };
  479. struct r8152;
  480. struct rx_agg {
  481. struct list_head list;
  482. struct urb *urb;
  483. struct r8152 *context;
  484. void *buffer;
  485. void *head;
  486. };
  487. struct tx_agg {
  488. struct list_head list;
  489. struct urb *urb;
  490. struct r8152 *context;
  491. void *buffer;
  492. void *head;
  493. u32 skb_num;
  494. u32 skb_len;
  495. };
  496. struct r8152 {
  497. unsigned long flags;
  498. struct usb_device *udev;
  499. struct napi_struct napi;
  500. struct usb_interface *intf;
  501. struct net_device *netdev;
  502. struct urb *intr_urb;
  503. struct tx_agg tx_info[RTL8152_MAX_TX];
  504. struct rx_agg rx_info[RTL8152_MAX_RX];
  505. struct list_head rx_done, tx_free;
  506. struct sk_buff_head tx_queue, rx_queue;
  507. spinlock_t rx_lock, tx_lock;
  508. struct delayed_work schedule;
  509. struct mii_if_info mii;
  510. struct mutex control; /* use for hw setting */
  511. struct rtl_ops {
  512. void (*init)(struct r8152 *);
  513. int (*enable)(struct r8152 *);
  514. void (*disable)(struct r8152 *);
  515. void (*up)(struct r8152 *);
  516. void (*down)(struct r8152 *);
  517. void (*unload)(struct r8152 *);
  518. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  519. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  520. bool (*in_nway)(struct r8152 *);
  521. } rtl_ops;
  522. int intr_interval;
  523. u32 saved_wolopts;
  524. u32 msg_enable;
  525. u32 tx_qlen;
  526. u32 coalesce;
  527. u16 ocp_base;
  528. u8 *intr_buff;
  529. u8 version;
  530. };
  531. enum rtl_version {
  532. RTL_VER_UNKNOWN = 0,
  533. RTL_VER_01,
  534. RTL_VER_02,
  535. RTL_VER_03,
  536. RTL_VER_04,
  537. RTL_VER_05,
  538. RTL_VER_06,
  539. RTL_VER_MAX
  540. };
  541. enum tx_csum_stat {
  542. TX_CSUM_SUCCESS = 0,
  543. TX_CSUM_TSO,
  544. TX_CSUM_NONE
  545. };
  546. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  547. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  548. */
  549. static const int multicast_filter_limit = 32;
  550. static unsigned int agg_buf_sz = 16384;
  551. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  552. VLAN_ETH_HLEN - VLAN_HLEN)
  553. static
  554. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  555. {
  556. int ret;
  557. void *tmp;
  558. tmp = kmalloc(size, GFP_KERNEL);
  559. if (!tmp)
  560. return -ENOMEM;
  561. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  562. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  563. value, index, tmp, size, 500);
  564. memcpy(data, tmp, size);
  565. kfree(tmp);
  566. return ret;
  567. }
  568. static
  569. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  570. {
  571. int ret;
  572. void *tmp;
  573. tmp = kmemdup(data, size, GFP_KERNEL);
  574. if (!tmp)
  575. return -ENOMEM;
  576. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  577. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  578. value, index, tmp, size, 500);
  579. kfree(tmp);
  580. return ret;
  581. }
  582. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  583. void *data, u16 type)
  584. {
  585. u16 limit = 64;
  586. int ret = 0;
  587. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  588. return -ENODEV;
  589. /* both size and indix must be 4 bytes align */
  590. if ((size & 3) || !size || (index & 3) || !data)
  591. return -EPERM;
  592. if ((u32)index + (u32)size > 0xffff)
  593. return -EPERM;
  594. while (size) {
  595. if (size > limit) {
  596. ret = get_registers(tp, index, type, limit, data);
  597. if (ret < 0)
  598. break;
  599. index += limit;
  600. data += limit;
  601. size -= limit;
  602. } else {
  603. ret = get_registers(tp, index, type, size, data);
  604. if (ret < 0)
  605. break;
  606. index += size;
  607. data += size;
  608. size = 0;
  609. break;
  610. }
  611. }
  612. if (ret == -ENODEV)
  613. set_bit(RTL8152_UNPLUG, &tp->flags);
  614. return ret;
  615. }
  616. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  617. u16 size, void *data, u16 type)
  618. {
  619. int ret;
  620. u16 byteen_start, byteen_end, byen;
  621. u16 limit = 512;
  622. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  623. return -ENODEV;
  624. /* both size and indix must be 4 bytes align */
  625. if ((size & 3) || !size || (index & 3) || !data)
  626. return -EPERM;
  627. if ((u32)index + (u32)size > 0xffff)
  628. return -EPERM;
  629. byteen_start = byteen & BYTE_EN_START_MASK;
  630. byteen_end = byteen & BYTE_EN_END_MASK;
  631. byen = byteen_start | (byteen_start << 4);
  632. ret = set_registers(tp, index, type | byen, 4, data);
  633. if (ret < 0)
  634. goto error1;
  635. index += 4;
  636. data += 4;
  637. size -= 4;
  638. if (size) {
  639. size -= 4;
  640. while (size) {
  641. if (size > limit) {
  642. ret = set_registers(tp, index,
  643. type | BYTE_EN_DWORD,
  644. limit, data);
  645. if (ret < 0)
  646. goto error1;
  647. index += limit;
  648. data += limit;
  649. size -= limit;
  650. } else {
  651. ret = set_registers(tp, index,
  652. type | BYTE_EN_DWORD,
  653. size, data);
  654. if (ret < 0)
  655. goto error1;
  656. index += size;
  657. data += size;
  658. size = 0;
  659. break;
  660. }
  661. }
  662. byen = byteen_end | (byteen_end >> 4);
  663. ret = set_registers(tp, index, type | byen, 4, data);
  664. if (ret < 0)
  665. goto error1;
  666. }
  667. error1:
  668. if (ret == -ENODEV)
  669. set_bit(RTL8152_UNPLUG, &tp->flags);
  670. return ret;
  671. }
  672. static inline
  673. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  674. {
  675. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  676. }
  677. static inline
  678. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  679. {
  680. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  681. }
  682. static inline
  683. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  684. {
  685. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  686. }
  687. static inline
  688. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  689. {
  690. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  691. }
  692. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  693. {
  694. __le32 data;
  695. generic_ocp_read(tp, index, sizeof(data), &data, type);
  696. return __le32_to_cpu(data);
  697. }
  698. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  699. {
  700. __le32 tmp = __cpu_to_le32(data);
  701. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  702. }
  703. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  704. {
  705. u32 data;
  706. __le32 tmp;
  707. u8 shift = index & 2;
  708. index &= ~3;
  709. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  710. data = __le32_to_cpu(tmp);
  711. data >>= (shift * 8);
  712. data &= 0xffff;
  713. return (u16)data;
  714. }
  715. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  716. {
  717. u32 mask = 0xffff;
  718. __le32 tmp;
  719. u16 byen = BYTE_EN_WORD;
  720. u8 shift = index & 2;
  721. data &= mask;
  722. if (index & 2) {
  723. byen <<= shift;
  724. mask <<= (shift * 8);
  725. data <<= (shift * 8);
  726. index &= ~3;
  727. }
  728. tmp = __cpu_to_le32(data);
  729. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  730. }
  731. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  732. {
  733. u32 data;
  734. __le32 tmp;
  735. u8 shift = index & 3;
  736. index &= ~3;
  737. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  738. data = __le32_to_cpu(tmp);
  739. data >>= (shift * 8);
  740. data &= 0xff;
  741. return (u8)data;
  742. }
  743. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  744. {
  745. u32 mask = 0xff;
  746. __le32 tmp;
  747. u16 byen = BYTE_EN_BYTE;
  748. u8 shift = index & 3;
  749. data &= mask;
  750. if (index & 3) {
  751. byen <<= shift;
  752. mask <<= (shift * 8);
  753. data <<= (shift * 8);
  754. index &= ~3;
  755. }
  756. tmp = __cpu_to_le32(data);
  757. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  758. }
  759. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  760. {
  761. u16 ocp_base, ocp_index;
  762. ocp_base = addr & 0xf000;
  763. if (ocp_base != tp->ocp_base) {
  764. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  765. tp->ocp_base = ocp_base;
  766. }
  767. ocp_index = (addr & 0x0fff) | 0xb000;
  768. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  769. }
  770. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  771. {
  772. u16 ocp_base, ocp_index;
  773. ocp_base = addr & 0xf000;
  774. if (ocp_base != tp->ocp_base) {
  775. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  776. tp->ocp_base = ocp_base;
  777. }
  778. ocp_index = (addr & 0x0fff) | 0xb000;
  779. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  780. }
  781. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  782. {
  783. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  784. }
  785. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  786. {
  787. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  788. }
  789. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  790. {
  791. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  792. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  793. }
  794. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  795. {
  796. struct r8152 *tp = netdev_priv(netdev);
  797. int ret;
  798. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  799. return -ENODEV;
  800. if (phy_id != R8152_PHY_ID)
  801. return -EINVAL;
  802. ret = r8152_mdio_read(tp, reg);
  803. return ret;
  804. }
  805. static
  806. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  807. {
  808. struct r8152 *tp = netdev_priv(netdev);
  809. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  810. return;
  811. if (phy_id != R8152_PHY_ID)
  812. return;
  813. r8152_mdio_write(tp, reg, val);
  814. }
  815. static int
  816. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  817. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  818. {
  819. struct r8152 *tp = netdev_priv(netdev);
  820. struct sockaddr *addr = p;
  821. int ret = -EADDRNOTAVAIL;
  822. if (!is_valid_ether_addr(addr->sa_data))
  823. goto out1;
  824. ret = usb_autopm_get_interface(tp->intf);
  825. if (ret < 0)
  826. goto out1;
  827. mutex_lock(&tp->control);
  828. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  829. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  830. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  831. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  832. mutex_unlock(&tp->control);
  833. usb_autopm_put_interface(tp->intf);
  834. out1:
  835. return ret;
  836. }
  837. static int set_ethernet_addr(struct r8152 *tp)
  838. {
  839. struct net_device *dev = tp->netdev;
  840. struct sockaddr sa;
  841. int ret;
  842. if (tp->version == RTL_VER_01)
  843. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  844. else
  845. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  846. if (ret < 0) {
  847. netif_err(tp, probe, dev, "Get ether addr fail\n");
  848. } else if (!is_valid_ether_addr(sa.sa_data)) {
  849. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  850. sa.sa_data);
  851. eth_hw_addr_random(dev);
  852. ether_addr_copy(sa.sa_data, dev->dev_addr);
  853. ret = rtl8152_set_mac_address(dev, &sa);
  854. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  855. sa.sa_data);
  856. } else {
  857. if (tp->version == RTL_VER_01)
  858. ether_addr_copy(dev->dev_addr, sa.sa_data);
  859. else
  860. ret = rtl8152_set_mac_address(dev, &sa);
  861. }
  862. return ret;
  863. }
  864. static void read_bulk_callback(struct urb *urb)
  865. {
  866. struct net_device *netdev;
  867. int status = urb->status;
  868. struct rx_agg *agg;
  869. struct r8152 *tp;
  870. agg = urb->context;
  871. if (!agg)
  872. return;
  873. tp = agg->context;
  874. if (!tp)
  875. return;
  876. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  877. return;
  878. if (!test_bit(WORK_ENABLE, &tp->flags))
  879. return;
  880. netdev = tp->netdev;
  881. /* When link down, the driver would cancel all bulks. */
  882. /* This avoid the re-submitting bulk */
  883. if (!netif_carrier_ok(netdev))
  884. return;
  885. usb_mark_last_busy(tp->udev);
  886. switch (status) {
  887. case 0:
  888. if (urb->actual_length < ETH_ZLEN)
  889. break;
  890. spin_lock(&tp->rx_lock);
  891. list_add_tail(&agg->list, &tp->rx_done);
  892. spin_unlock(&tp->rx_lock);
  893. napi_schedule(&tp->napi);
  894. return;
  895. case -ESHUTDOWN:
  896. set_bit(RTL8152_UNPLUG, &tp->flags);
  897. netif_device_detach(tp->netdev);
  898. return;
  899. case -ENOENT:
  900. return; /* the urb is in unlink state */
  901. case -ETIME:
  902. if (net_ratelimit())
  903. netdev_warn(netdev, "maybe reset is needed?\n");
  904. break;
  905. default:
  906. if (net_ratelimit())
  907. netdev_warn(netdev, "Rx status %d\n", status);
  908. break;
  909. }
  910. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  911. }
  912. static void write_bulk_callback(struct urb *urb)
  913. {
  914. struct net_device_stats *stats;
  915. struct net_device *netdev;
  916. struct tx_agg *agg;
  917. struct r8152 *tp;
  918. int status = urb->status;
  919. agg = urb->context;
  920. if (!agg)
  921. return;
  922. tp = agg->context;
  923. if (!tp)
  924. return;
  925. netdev = tp->netdev;
  926. stats = &netdev->stats;
  927. if (status) {
  928. if (net_ratelimit())
  929. netdev_warn(netdev, "Tx status %d\n", status);
  930. stats->tx_errors += agg->skb_num;
  931. } else {
  932. stats->tx_packets += agg->skb_num;
  933. stats->tx_bytes += agg->skb_len;
  934. }
  935. spin_lock(&tp->tx_lock);
  936. list_add_tail(&agg->list, &tp->tx_free);
  937. spin_unlock(&tp->tx_lock);
  938. usb_autopm_put_interface_async(tp->intf);
  939. if (!netif_carrier_ok(netdev))
  940. return;
  941. if (!test_bit(WORK_ENABLE, &tp->flags))
  942. return;
  943. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  944. return;
  945. if (!skb_queue_empty(&tp->tx_queue))
  946. napi_schedule(&tp->napi);
  947. }
  948. static void intr_callback(struct urb *urb)
  949. {
  950. struct r8152 *tp;
  951. __le16 *d;
  952. int status = urb->status;
  953. int res;
  954. tp = urb->context;
  955. if (!tp)
  956. return;
  957. if (!test_bit(WORK_ENABLE, &tp->flags))
  958. return;
  959. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  960. return;
  961. switch (status) {
  962. case 0: /* success */
  963. break;
  964. case -ECONNRESET: /* unlink */
  965. case -ESHUTDOWN:
  966. netif_device_detach(tp->netdev);
  967. case -ENOENT:
  968. case -EPROTO:
  969. netif_info(tp, intr, tp->netdev,
  970. "Stop submitting intr, status %d\n", status);
  971. return;
  972. case -EOVERFLOW:
  973. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  974. goto resubmit;
  975. /* -EPIPE: should clear the halt */
  976. default:
  977. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  978. goto resubmit;
  979. }
  980. d = urb->transfer_buffer;
  981. if (INTR_LINK & __le16_to_cpu(d[0])) {
  982. if (!netif_carrier_ok(tp->netdev)) {
  983. set_bit(RTL8152_LINK_CHG, &tp->flags);
  984. schedule_delayed_work(&tp->schedule, 0);
  985. }
  986. } else {
  987. if (netif_carrier_ok(tp->netdev)) {
  988. set_bit(RTL8152_LINK_CHG, &tp->flags);
  989. schedule_delayed_work(&tp->schedule, 0);
  990. }
  991. }
  992. resubmit:
  993. res = usb_submit_urb(urb, GFP_ATOMIC);
  994. if (res == -ENODEV) {
  995. set_bit(RTL8152_UNPLUG, &tp->flags);
  996. netif_device_detach(tp->netdev);
  997. } else if (res) {
  998. netif_err(tp, intr, tp->netdev,
  999. "can't resubmit intr, status %d\n", res);
  1000. }
  1001. }
  1002. static inline void *rx_agg_align(void *data)
  1003. {
  1004. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1005. }
  1006. static inline void *tx_agg_align(void *data)
  1007. {
  1008. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1009. }
  1010. static void free_all_mem(struct r8152 *tp)
  1011. {
  1012. int i;
  1013. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1014. usb_free_urb(tp->rx_info[i].urb);
  1015. tp->rx_info[i].urb = NULL;
  1016. kfree(tp->rx_info[i].buffer);
  1017. tp->rx_info[i].buffer = NULL;
  1018. tp->rx_info[i].head = NULL;
  1019. }
  1020. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1021. usb_free_urb(tp->tx_info[i].urb);
  1022. tp->tx_info[i].urb = NULL;
  1023. kfree(tp->tx_info[i].buffer);
  1024. tp->tx_info[i].buffer = NULL;
  1025. tp->tx_info[i].head = NULL;
  1026. }
  1027. usb_free_urb(tp->intr_urb);
  1028. tp->intr_urb = NULL;
  1029. kfree(tp->intr_buff);
  1030. tp->intr_buff = NULL;
  1031. }
  1032. static int alloc_all_mem(struct r8152 *tp)
  1033. {
  1034. struct net_device *netdev = tp->netdev;
  1035. struct usb_interface *intf = tp->intf;
  1036. struct usb_host_interface *alt = intf->cur_altsetting;
  1037. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1038. struct urb *urb;
  1039. int node, i;
  1040. u8 *buf;
  1041. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1042. spin_lock_init(&tp->rx_lock);
  1043. spin_lock_init(&tp->tx_lock);
  1044. INIT_LIST_HEAD(&tp->tx_free);
  1045. skb_queue_head_init(&tp->tx_queue);
  1046. skb_queue_head_init(&tp->rx_queue);
  1047. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1048. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1049. if (!buf)
  1050. goto err1;
  1051. if (buf != rx_agg_align(buf)) {
  1052. kfree(buf);
  1053. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1054. node);
  1055. if (!buf)
  1056. goto err1;
  1057. }
  1058. urb = usb_alloc_urb(0, GFP_KERNEL);
  1059. if (!urb) {
  1060. kfree(buf);
  1061. goto err1;
  1062. }
  1063. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1064. tp->rx_info[i].context = tp;
  1065. tp->rx_info[i].urb = urb;
  1066. tp->rx_info[i].buffer = buf;
  1067. tp->rx_info[i].head = rx_agg_align(buf);
  1068. }
  1069. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1070. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1071. if (!buf)
  1072. goto err1;
  1073. if (buf != tx_agg_align(buf)) {
  1074. kfree(buf);
  1075. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1076. node);
  1077. if (!buf)
  1078. goto err1;
  1079. }
  1080. urb = usb_alloc_urb(0, GFP_KERNEL);
  1081. if (!urb) {
  1082. kfree(buf);
  1083. goto err1;
  1084. }
  1085. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1086. tp->tx_info[i].context = tp;
  1087. tp->tx_info[i].urb = urb;
  1088. tp->tx_info[i].buffer = buf;
  1089. tp->tx_info[i].head = tx_agg_align(buf);
  1090. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1091. }
  1092. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1093. if (!tp->intr_urb)
  1094. goto err1;
  1095. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1096. if (!tp->intr_buff)
  1097. goto err1;
  1098. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1099. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1100. tp->intr_buff, INTBUFSIZE, intr_callback,
  1101. tp, tp->intr_interval);
  1102. return 0;
  1103. err1:
  1104. free_all_mem(tp);
  1105. return -ENOMEM;
  1106. }
  1107. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1108. {
  1109. struct tx_agg *agg = NULL;
  1110. unsigned long flags;
  1111. if (list_empty(&tp->tx_free))
  1112. return NULL;
  1113. spin_lock_irqsave(&tp->tx_lock, flags);
  1114. if (!list_empty(&tp->tx_free)) {
  1115. struct list_head *cursor;
  1116. cursor = tp->tx_free.next;
  1117. list_del_init(cursor);
  1118. agg = list_entry(cursor, struct tx_agg, list);
  1119. }
  1120. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1121. return agg;
  1122. }
  1123. /* r8152_csum_workaround()
  1124. * The hw limites the value the transport offset. When the offset is out of the
  1125. * range, calculate the checksum by sw.
  1126. */
  1127. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1128. struct sk_buff_head *list)
  1129. {
  1130. if (skb_shinfo(skb)->gso_size) {
  1131. netdev_features_t features = tp->netdev->features;
  1132. struct sk_buff_head seg_list;
  1133. struct sk_buff *segs, *nskb;
  1134. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1135. segs = skb_gso_segment(skb, features);
  1136. if (IS_ERR(segs) || !segs)
  1137. goto drop;
  1138. __skb_queue_head_init(&seg_list);
  1139. do {
  1140. nskb = segs;
  1141. segs = segs->next;
  1142. nskb->next = NULL;
  1143. __skb_queue_tail(&seg_list, nskb);
  1144. } while (segs);
  1145. skb_queue_splice(&seg_list, list);
  1146. dev_kfree_skb(skb);
  1147. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1148. if (skb_checksum_help(skb) < 0)
  1149. goto drop;
  1150. __skb_queue_head(list, skb);
  1151. } else {
  1152. struct net_device_stats *stats;
  1153. drop:
  1154. stats = &tp->netdev->stats;
  1155. stats->tx_dropped++;
  1156. dev_kfree_skb(skb);
  1157. }
  1158. }
  1159. /* msdn_giant_send_check()
  1160. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1161. * packet length for IPv6 TCP large packets.
  1162. */
  1163. static int msdn_giant_send_check(struct sk_buff *skb)
  1164. {
  1165. const struct ipv6hdr *ipv6h;
  1166. struct tcphdr *th;
  1167. int ret;
  1168. ret = skb_cow_head(skb, 0);
  1169. if (ret)
  1170. return ret;
  1171. ipv6h = ipv6_hdr(skb);
  1172. th = tcp_hdr(skb);
  1173. th->check = 0;
  1174. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1175. return ret;
  1176. }
  1177. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1178. {
  1179. if (skb_vlan_tag_present(skb)) {
  1180. u32 opts2;
  1181. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1182. desc->opts2 |= cpu_to_le32(opts2);
  1183. }
  1184. }
  1185. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1186. {
  1187. u32 opts2 = le32_to_cpu(desc->opts2);
  1188. if (opts2 & RX_VLAN_TAG)
  1189. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1190. swab16(opts2 & 0xffff));
  1191. }
  1192. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1193. struct sk_buff *skb, u32 len, u32 transport_offset)
  1194. {
  1195. u32 mss = skb_shinfo(skb)->gso_size;
  1196. u32 opts1, opts2 = 0;
  1197. int ret = TX_CSUM_SUCCESS;
  1198. WARN_ON_ONCE(len > TX_LEN_MAX);
  1199. opts1 = len | TX_FS | TX_LS;
  1200. if (mss) {
  1201. if (transport_offset > GTTCPHO_MAX) {
  1202. netif_warn(tp, tx_err, tp->netdev,
  1203. "Invalid transport offset 0x%x for TSO\n",
  1204. transport_offset);
  1205. ret = TX_CSUM_TSO;
  1206. goto unavailable;
  1207. }
  1208. switch (vlan_get_protocol(skb)) {
  1209. case htons(ETH_P_IP):
  1210. opts1 |= GTSENDV4;
  1211. break;
  1212. case htons(ETH_P_IPV6):
  1213. if (msdn_giant_send_check(skb)) {
  1214. ret = TX_CSUM_TSO;
  1215. goto unavailable;
  1216. }
  1217. opts1 |= GTSENDV6;
  1218. break;
  1219. default:
  1220. WARN_ON_ONCE(1);
  1221. break;
  1222. }
  1223. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1224. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1225. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1226. u8 ip_protocol;
  1227. if (transport_offset > TCPHO_MAX) {
  1228. netif_warn(tp, tx_err, tp->netdev,
  1229. "Invalid transport offset 0x%x\n",
  1230. transport_offset);
  1231. ret = TX_CSUM_NONE;
  1232. goto unavailable;
  1233. }
  1234. switch (vlan_get_protocol(skb)) {
  1235. case htons(ETH_P_IP):
  1236. opts2 |= IPV4_CS;
  1237. ip_protocol = ip_hdr(skb)->protocol;
  1238. break;
  1239. case htons(ETH_P_IPV6):
  1240. opts2 |= IPV6_CS;
  1241. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1242. break;
  1243. default:
  1244. ip_protocol = IPPROTO_RAW;
  1245. break;
  1246. }
  1247. if (ip_protocol == IPPROTO_TCP)
  1248. opts2 |= TCP_CS;
  1249. else if (ip_protocol == IPPROTO_UDP)
  1250. opts2 |= UDP_CS;
  1251. else
  1252. WARN_ON_ONCE(1);
  1253. opts2 |= transport_offset << TCPHO_SHIFT;
  1254. }
  1255. desc->opts2 = cpu_to_le32(opts2);
  1256. desc->opts1 = cpu_to_le32(opts1);
  1257. unavailable:
  1258. return ret;
  1259. }
  1260. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1261. {
  1262. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1263. int remain, ret;
  1264. u8 *tx_data;
  1265. __skb_queue_head_init(&skb_head);
  1266. spin_lock(&tx_queue->lock);
  1267. skb_queue_splice_init(tx_queue, &skb_head);
  1268. spin_unlock(&tx_queue->lock);
  1269. tx_data = agg->head;
  1270. agg->skb_num = 0;
  1271. agg->skb_len = 0;
  1272. remain = agg_buf_sz;
  1273. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1274. struct tx_desc *tx_desc;
  1275. struct sk_buff *skb;
  1276. unsigned int len;
  1277. u32 offset;
  1278. skb = __skb_dequeue(&skb_head);
  1279. if (!skb)
  1280. break;
  1281. len = skb->len + sizeof(*tx_desc);
  1282. if (len > remain) {
  1283. __skb_queue_head(&skb_head, skb);
  1284. break;
  1285. }
  1286. tx_data = tx_agg_align(tx_data);
  1287. tx_desc = (struct tx_desc *)tx_data;
  1288. offset = (u32)skb_transport_offset(skb);
  1289. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1290. r8152_csum_workaround(tp, skb, &skb_head);
  1291. continue;
  1292. }
  1293. rtl_tx_vlan_tag(tx_desc, skb);
  1294. tx_data += sizeof(*tx_desc);
  1295. len = skb->len;
  1296. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1297. struct net_device_stats *stats = &tp->netdev->stats;
  1298. stats->tx_dropped++;
  1299. dev_kfree_skb_any(skb);
  1300. tx_data -= sizeof(*tx_desc);
  1301. continue;
  1302. }
  1303. tx_data += len;
  1304. agg->skb_len += len;
  1305. agg->skb_num++;
  1306. dev_kfree_skb_any(skb);
  1307. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1308. }
  1309. if (!skb_queue_empty(&skb_head)) {
  1310. spin_lock(&tx_queue->lock);
  1311. skb_queue_splice(&skb_head, tx_queue);
  1312. spin_unlock(&tx_queue->lock);
  1313. }
  1314. netif_tx_lock(tp->netdev);
  1315. if (netif_queue_stopped(tp->netdev) &&
  1316. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1317. netif_wake_queue(tp->netdev);
  1318. netif_tx_unlock(tp->netdev);
  1319. ret = usb_autopm_get_interface_async(tp->intf);
  1320. if (ret < 0)
  1321. goto out_tx_fill;
  1322. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1323. agg->head, (int)(tx_data - (u8 *)agg->head),
  1324. (usb_complete_t)write_bulk_callback, agg);
  1325. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1326. if (ret < 0)
  1327. usb_autopm_put_interface_async(tp->intf);
  1328. out_tx_fill:
  1329. return ret;
  1330. }
  1331. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1332. {
  1333. u8 checksum = CHECKSUM_NONE;
  1334. u32 opts2, opts3;
  1335. if (tp->version == RTL_VER_01)
  1336. goto return_result;
  1337. opts2 = le32_to_cpu(rx_desc->opts2);
  1338. opts3 = le32_to_cpu(rx_desc->opts3);
  1339. if (opts2 & RD_IPV4_CS) {
  1340. if (opts3 & IPF)
  1341. checksum = CHECKSUM_NONE;
  1342. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1343. checksum = CHECKSUM_NONE;
  1344. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1345. checksum = CHECKSUM_NONE;
  1346. else
  1347. checksum = CHECKSUM_UNNECESSARY;
  1348. } else if (RD_IPV6_CS) {
  1349. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1350. checksum = CHECKSUM_UNNECESSARY;
  1351. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1352. checksum = CHECKSUM_UNNECESSARY;
  1353. }
  1354. return_result:
  1355. return checksum;
  1356. }
  1357. static int rx_bottom(struct r8152 *tp, int budget)
  1358. {
  1359. unsigned long flags;
  1360. struct list_head *cursor, *next, rx_queue;
  1361. int ret = 0, work_done = 0;
  1362. if (!skb_queue_empty(&tp->rx_queue)) {
  1363. while (work_done < budget) {
  1364. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1365. struct net_device *netdev = tp->netdev;
  1366. struct net_device_stats *stats = &netdev->stats;
  1367. unsigned int pkt_len;
  1368. if (!skb)
  1369. break;
  1370. pkt_len = skb->len;
  1371. napi_gro_receive(&tp->napi, skb);
  1372. work_done++;
  1373. stats->rx_packets++;
  1374. stats->rx_bytes += pkt_len;
  1375. }
  1376. }
  1377. if (list_empty(&tp->rx_done))
  1378. goto out1;
  1379. INIT_LIST_HEAD(&rx_queue);
  1380. spin_lock_irqsave(&tp->rx_lock, flags);
  1381. list_splice_init(&tp->rx_done, &rx_queue);
  1382. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1383. list_for_each_safe(cursor, next, &rx_queue) {
  1384. struct rx_desc *rx_desc;
  1385. struct rx_agg *agg;
  1386. int len_used = 0;
  1387. struct urb *urb;
  1388. u8 *rx_data;
  1389. list_del_init(cursor);
  1390. agg = list_entry(cursor, struct rx_agg, list);
  1391. urb = agg->urb;
  1392. if (urb->actual_length < ETH_ZLEN)
  1393. goto submit;
  1394. rx_desc = agg->head;
  1395. rx_data = agg->head;
  1396. len_used += sizeof(struct rx_desc);
  1397. while (urb->actual_length > len_used) {
  1398. struct net_device *netdev = tp->netdev;
  1399. struct net_device_stats *stats = &netdev->stats;
  1400. unsigned int pkt_len;
  1401. struct sk_buff *skb;
  1402. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1403. if (pkt_len < ETH_ZLEN)
  1404. break;
  1405. len_used += pkt_len;
  1406. if (urb->actual_length < len_used)
  1407. break;
  1408. pkt_len -= CRC_SIZE;
  1409. rx_data += sizeof(struct rx_desc);
  1410. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1411. if (!skb) {
  1412. stats->rx_dropped++;
  1413. goto find_next_rx;
  1414. }
  1415. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1416. memcpy(skb->data, rx_data, pkt_len);
  1417. skb_put(skb, pkt_len);
  1418. skb->protocol = eth_type_trans(skb, netdev);
  1419. rtl_rx_vlan_tag(rx_desc, skb);
  1420. if (work_done < budget) {
  1421. napi_gro_receive(&tp->napi, skb);
  1422. work_done++;
  1423. stats->rx_packets++;
  1424. stats->rx_bytes += pkt_len;
  1425. } else {
  1426. __skb_queue_tail(&tp->rx_queue, skb);
  1427. }
  1428. find_next_rx:
  1429. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1430. rx_desc = (struct rx_desc *)rx_data;
  1431. len_used = (int)(rx_data - (u8 *)agg->head);
  1432. len_used += sizeof(struct rx_desc);
  1433. }
  1434. submit:
  1435. if (!ret) {
  1436. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1437. } else {
  1438. urb->actual_length = 0;
  1439. list_add_tail(&agg->list, next);
  1440. }
  1441. }
  1442. if (!list_empty(&rx_queue)) {
  1443. spin_lock_irqsave(&tp->rx_lock, flags);
  1444. list_splice_tail(&rx_queue, &tp->rx_done);
  1445. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1446. }
  1447. out1:
  1448. return work_done;
  1449. }
  1450. static void tx_bottom(struct r8152 *tp)
  1451. {
  1452. int res;
  1453. do {
  1454. struct tx_agg *agg;
  1455. if (skb_queue_empty(&tp->tx_queue))
  1456. break;
  1457. agg = r8152_get_tx_agg(tp);
  1458. if (!agg)
  1459. break;
  1460. res = r8152_tx_agg_fill(tp, agg);
  1461. if (res) {
  1462. struct net_device *netdev = tp->netdev;
  1463. if (res == -ENODEV) {
  1464. set_bit(RTL8152_UNPLUG, &tp->flags);
  1465. netif_device_detach(netdev);
  1466. } else {
  1467. struct net_device_stats *stats = &netdev->stats;
  1468. unsigned long flags;
  1469. netif_warn(tp, tx_err, netdev,
  1470. "failed tx_urb %d\n", res);
  1471. stats->tx_dropped += agg->skb_num;
  1472. spin_lock_irqsave(&tp->tx_lock, flags);
  1473. list_add_tail(&agg->list, &tp->tx_free);
  1474. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1475. }
  1476. }
  1477. } while (res == 0);
  1478. }
  1479. static void bottom_half(struct r8152 *tp)
  1480. {
  1481. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1482. return;
  1483. if (!test_bit(WORK_ENABLE, &tp->flags))
  1484. return;
  1485. /* When link down, the driver would cancel all bulks. */
  1486. /* This avoid the re-submitting bulk */
  1487. if (!netif_carrier_ok(tp->netdev))
  1488. return;
  1489. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1490. tx_bottom(tp);
  1491. }
  1492. static int r8152_poll(struct napi_struct *napi, int budget)
  1493. {
  1494. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1495. int work_done;
  1496. work_done = rx_bottom(tp, budget);
  1497. bottom_half(tp);
  1498. if (work_done < budget) {
  1499. napi_complete(napi);
  1500. if (!list_empty(&tp->rx_done))
  1501. napi_schedule(napi);
  1502. }
  1503. return work_done;
  1504. }
  1505. static
  1506. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1507. {
  1508. int ret;
  1509. /* The rx would be stopped, so skip submitting */
  1510. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1511. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1512. return 0;
  1513. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1514. agg->head, agg_buf_sz,
  1515. (usb_complete_t)read_bulk_callback, agg);
  1516. ret = usb_submit_urb(agg->urb, mem_flags);
  1517. if (ret == -ENODEV) {
  1518. set_bit(RTL8152_UNPLUG, &tp->flags);
  1519. netif_device_detach(tp->netdev);
  1520. } else if (ret) {
  1521. struct urb *urb = agg->urb;
  1522. unsigned long flags;
  1523. urb->actual_length = 0;
  1524. spin_lock_irqsave(&tp->rx_lock, flags);
  1525. list_add_tail(&agg->list, &tp->rx_done);
  1526. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1527. netif_err(tp, rx_err, tp->netdev,
  1528. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1529. napi_schedule(&tp->napi);
  1530. }
  1531. return ret;
  1532. }
  1533. static void rtl_drop_queued_tx(struct r8152 *tp)
  1534. {
  1535. struct net_device_stats *stats = &tp->netdev->stats;
  1536. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1537. struct sk_buff *skb;
  1538. if (skb_queue_empty(tx_queue))
  1539. return;
  1540. __skb_queue_head_init(&skb_head);
  1541. spin_lock_bh(&tx_queue->lock);
  1542. skb_queue_splice_init(tx_queue, &skb_head);
  1543. spin_unlock_bh(&tx_queue->lock);
  1544. while ((skb = __skb_dequeue(&skb_head))) {
  1545. dev_kfree_skb(skb);
  1546. stats->tx_dropped++;
  1547. }
  1548. }
  1549. static void rtl8152_tx_timeout(struct net_device *netdev)
  1550. {
  1551. struct r8152 *tp = netdev_priv(netdev);
  1552. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1553. usb_queue_reset_device(tp->intf);
  1554. }
  1555. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1556. {
  1557. struct r8152 *tp = netdev_priv(netdev);
  1558. if (netif_carrier_ok(netdev)) {
  1559. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1560. schedule_delayed_work(&tp->schedule, 0);
  1561. }
  1562. }
  1563. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1564. {
  1565. struct r8152 *tp = netdev_priv(netdev);
  1566. u32 mc_filter[2]; /* Multicast hash filter */
  1567. __le32 tmp[2];
  1568. u32 ocp_data;
  1569. netif_stop_queue(netdev);
  1570. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1571. ocp_data &= ~RCR_ACPT_ALL;
  1572. ocp_data |= RCR_AB | RCR_APM;
  1573. if (netdev->flags & IFF_PROMISC) {
  1574. /* Unconditionally log net taps. */
  1575. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1576. ocp_data |= RCR_AM | RCR_AAP;
  1577. mc_filter[1] = 0xffffffff;
  1578. mc_filter[0] = 0xffffffff;
  1579. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1580. (netdev->flags & IFF_ALLMULTI)) {
  1581. /* Too many to filter perfectly -- accept all multicasts. */
  1582. ocp_data |= RCR_AM;
  1583. mc_filter[1] = 0xffffffff;
  1584. mc_filter[0] = 0xffffffff;
  1585. } else {
  1586. struct netdev_hw_addr *ha;
  1587. mc_filter[1] = 0;
  1588. mc_filter[0] = 0;
  1589. netdev_for_each_mc_addr(ha, netdev) {
  1590. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1591. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1592. ocp_data |= RCR_AM;
  1593. }
  1594. }
  1595. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1596. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1597. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1598. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1599. netif_wake_queue(netdev);
  1600. }
  1601. static netdev_features_t
  1602. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1603. netdev_features_t features)
  1604. {
  1605. u32 mss = skb_shinfo(skb)->gso_size;
  1606. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1607. int offset = skb_transport_offset(skb);
  1608. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1609. features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  1610. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1611. features &= ~NETIF_F_GSO_MASK;
  1612. return features;
  1613. }
  1614. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1615. struct net_device *netdev)
  1616. {
  1617. struct r8152 *tp = netdev_priv(netdev);
  1618. skb_tx_timestamp(skb);
  1619. skb_queue_tail(&tp->tx_queue, skb);
  1620. if (!list_empty(&tp->tx_free)) {
  1621. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1622. set_bit(SCHEDULE_NAPI, &tp->flags);
  1623. schedule_delayed_work(&tp->schedule, 0);
  1624. } else {
  1625. usb_mark_last_busy(tp->udev);
  1626. napi_schedule(&tp->napi);
  1627. }
  1628. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1629. netif_stop_queue(netdev);
  1630. }
  1631. return NETDEV_TX_OK;
  1632. }
  1633. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1634. {
  1635. u32 ocp_data;
  1636. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1637. ocp_data &= ~FMC_FCR_MCU_EN;
  1638. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1639. ocp_data |= FMC_FCR_MCU_EN;
  1640. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1641. }
  1642. static void rtl8152_nic_reset(struct r8152 *tp)
  1643. {
  1644. int i;
  1645. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1646. for (i = 0; i < 1000; i++) {
  1647. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1648. break;
  1649. usleep_range(100, 400);
  1650. }
  1651. }
  1652. static void set_tx_qlen(struct r8152 *tp)
  1653. {
  1654. struct net_device *netdev = tp->netdev;
  1655. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1656. sizeof(struct tx_desc));
  1657. }
  1658. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1659. {
  1660. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1661. }
  1662. static void rtl_set_eee_plus(struct r8152 *tp)
  1663. {
  1664. u32 ocp_data;
  1665. u8 speed;
  1666. speed = rtl8152_get_speed(tp);
  1667. if (speed & _10bps) {
  1668. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1669. ocp_data |= EEEP_CR_EEEP_TX;
  1670. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1671. } else {
  1672. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1673. ocp_data &= ~EEEP_CR_EEEP_TX;
  1674. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1675. }
  1676. }
  1677. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1678. {
  1679. u32 ocp_data;
  1680. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1681. if (enable)
  1682. ocp_data |= RXDY_GATED_EN;
  1683. else
  1684. ocp_data &= ~RXDY_GATED_EN;
  1685. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1686. }
  1687. static int rtl_start_rx(struct r8152 *tp)
  1688. {
  1689. int i, ret = 0;
  1690. INIT_LIST_HEAD(&tp->rx_done);
  1691. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1692. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1693. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1694. if (ret)
  1695. break;
  1696. }
  1697. if (ret && ++i < RTL8152_MAX_RX) {
  1698. struct list_head rx_queue;
  1699. unsigned long flags;
  1700. INIT_LIST_HEAD(&rx_queue);
  1701. do {
  1702. struct rx_agg *agg = &tp->rx_info[i++];
  1703. struct urb *urb = agg->urb;
  1704. urb->actual_length = 0;
  1705. list_add_tail(&agg->list, &rx_queue);
  1706. } while (i < RTL8152_MAX_RX);
  1707. spin_lock_irqsave(&tp->rx_lock, flags);
  1708. list_splice_tail(&rx_queue, &tp->rx_done);
  1709. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1710. }
  1711. return ret;
  1712. }
  1713. static int rtl_stop_rx(struct r8152 *tp)
  1714. {
  1715. int i;
  1716. for (i = 0; i < RTL8152_MAX_RX; i++)
  1717. usb_kill_urb(tp->rx_info[i].urb);
  1718. while (!skb_queue_empty(&tp->rx_queue))
  1719. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1720. return 0;
  1721. }
  1722. static int rtl_enable(struct r8152 *tp)
  1723. {
  1724. u32 ocp_data;
  1725. r8152b_reset_packet_filter(tp);
  1726. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1727. ocp_data |= CR_RE | CR_TE;
  1728. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1729. rxdy_gated_en(tp, false);
  1730. return 0;
  1731. }
  1732. static int rtl8152_enable(struct r8152 *tp)
  1733. {
  1734. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1735. return -ENODEV;
  1736. set_tx_qlen(tp);
  1737. rtl_set_eee_plus(tp);
  1738. return rtl_enable(tp);
  1739. }
  1740. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1741. {
  1742. u32 ocp_data = tp->coalesce / 8;
  1743. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1744. }
  1745. static void r8153_set_rx_early_size(struct r8152 *tp)
  1746. {
  1747. u32 mtu = tp->netdev->mtu;
  1748. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
  1749. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1750. }
  1751. static int rtl8153_enable(struct r8152 *tp)
  1752. {
  1753. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1754. return -ENODEV;
  1755. usb_disable_lpm(tp->udev);
  1756. set_tx_qlen(tp);
  1757. rtl_set_eee_plus(tp);
  1758. r8153_set_rx_early_timeout(tp);
  1759. r8153_set_rx_early_size(tp);
  1760. return rtl_enable(tp);
  1761. }
  1762. static void rtl_disable(struct r8152 *tp)
  1763. {
  1764. u32 ocp_data;
  1765. int i;
  1766. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1767. rtl_drop_queued_tx(tp);
  1768. return;
  1769. }
  1770. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1771. ocp_data &= ~RCR_ACPT_ALL;
  1772. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1773. rtl_drop_queued_tx(tp);
  1774. for (i = 0; i < RTL8152_MAX_TX; i++)
  1775. usb_kill_urb(tp->tx_info[i].urb);
  1776. rxdy_gated_en(tp, true);
  1777. for (i = 0; i < 1000; i++) {
  1778. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1779. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1780. break;
  1781. usleep_range(1000, 2000);
  1782. }
  1783. for (i = 0; i < 1000; i++) {
  1784. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1785. break;
  1786. usleep_range(1000, 2000);
  1787. }
  1788. rtl_stop_rx(tp);
  1789. rtl8152_nic_reset(tp);
  1790. }
  1791. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1792. {
  1793. u32 ocp_data;
  1794. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1795. if (enable)
  1796. ocp_data |= POWER_CUT;
  1797. else
  1798. ocp_data &= ~POWER_CUT;
  1799. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1800. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1801. ocp_data &= ~RESUME_INDICATE;
  1802. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1803. }
  1804. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1805. {
  1806. u32 ocp_data;
  1807. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1808. if (enable)
  1809. ocp_data |= CPCR_RX_VLAN;
  1810. else
  1811. ocp_data &= ~CPCR_RX_VLAN;
  1812. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1813. }
  1814. static int rtl8152_set_features(struct net_device *dev,
  1815. netdev_features_t features)
  1816. {
  1817. netdev_features_t changed = features ^ dev->features;
  1818. struct r8152 *tp = netdev_priv(dev);
  1819. int ret;
  1820. ret = usb_autopm_get_interface(tp->intf);
  1821. if (ret < 0)
  1822. goto out;
  1823. mutex_lock(&tp->control);
  1824. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1825. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1826. rtl_rx_vlan_en(tp, true);
  1827. else
  1828. rtl_rx_vlan_en(tp, false);
  1829. }
  1830. mutex_unlock(&tp->control);
  1831. usb_autopm_put_interface(tp->intf);
  1832. out:
  1833. return ret;
  1834. }
  1835. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1836. static u32 __rtl_get_wol(struct r8152 *tp)
  1837. {
  1838. u32 ocp_data;
  1839. u32 wolopts = 0;
  1840. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1841. if (!(ocp_data & LAN_WAKE_EN))
  1842. return 0;
  1843. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1844. if (ocp_data & LINK_ON_WAKE_EN)
  1845. wolopts |= WAKE_PHY;
  1846. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1847. if (ocp_data & UWF_EN)
  1848. wolopts |= WAKE_UCAST;
  1849. if (ocp_data & BWF_EN)
  1850. wolopts |= WAKE_BCAST;
  1851. if (ocp_data & MWF_EN)
  1852. wolopts |= WAKE_MCAST;
  1853. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1854. if (ocp_data & MAGIC_EN)
  1855. wolopts |= WAKE_MAGIC;
  1856. return wolopts;
  1857. }
  1858. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1859. {
  1860. u32 ocp_data;
  1861. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1862. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1863. ocp_data &= ~LINK_ON_WAKE_EN;
  1864. if (wolopts & WAKE_PHY)
  1865. ocp_data |= LINK_ON_WAKE_EN;
  1866. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1867. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1868. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1869. if (wolopts & WAKE_UCAST)
  1870. ocp_data |= UWF_EN;
  1871. if (wolopts & WAKE_BCAST)
  1872. ocp_data |= BWF_EN;
  1873. if (wolopts & WAKE_MCAST)
  1874. ocp_data |= MWF_EN;
  1875. if (wolopts & WAKE_ANY)
  1876. ocp_data |= LAN_WAKE_EN;
  1877. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1878. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1879. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1880. ocp_data &= ~MAGIC_EN;
  1881. if (wolopts & WAKE_MAGIC)
  1882. ocp_data |= MAGIC_EN;
  1883. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1884. if (wolopts & WAKE_ANY)
  1885. device_set_wakeup_enable(&tp->udev->dev, true);
  1886. else
  1887. device_set_wakeup_enable(&tp->udev->dev, false);
  1888. }
  1889. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  1890. {
  1891. u8 u1u2[8];
  1892. if (enable)
  1893. memset(u1u2, 0xff, sizeof(u1u2));
  1894. else
  1895. memset(u1u2, 0x00, sizeof(u1u2));
  1896. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  1897. }
  1898. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  1899. {
  1900. u32 ocp_data;
  1901. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  1902. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  1903. ocp_data |= U2P3_ENABLE;
  1904. else
  1905. ocp_data &= ~U2P3_ENABLE;
  1906. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  1907. }
  1908. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  1909. {
  1910. u32 ocp_data;
  1911. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  1912. if (enable)
  1913. ocp_data |= PWR_EN | PHASE2_EN;
  1914. else
  1915. ocp_data &= ~(PWR_EN | PHASE2_EN);
  1916. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  1917. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1918. ocp_data &= ~PCUT_STATUS;
  1919. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  1920. }
  1921. static bool rtl_can_wakeup(struct r8152 *tp)
  1922. {
  1923. struct usb_device *udev = tp->udev;
  1924. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  1925. }
  1926. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1927. {
  1928. if (enable) {
  1929. u32 ocp_data;
  1930. r8153_u1u2en(tp, false);
  1931. r8153_u2p3en(tp, false);
  1932. __rtl_set_wol(tp, WAKE_ANY);
  1933. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1934. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1935. ocp_data |= LINK_OFF_WAKE_EN;
  1936. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1937. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1938. } else {
  1939. __rtl_set_wol(tp, tp->saved_wolopts);
  1940. r8153_u2p3en(tp, true);
  1941. r8153_u1u2en(tp, true);
  1942. }
  1943. }
  1944. static void rtl_phy_reset(struct r8152 *tp)
  1945. {
  1946. u16 data;
  1947. int i;
  1948. data = r8152_mdio_read(tp, MII_BMCR);
  1949. /* don't reset again before the previous one complete */
  1950. if (data & BMCR_RESET)
  1951. return;
  1952. data |= BMCR_RESET;
  1953. r8152_mdio_write(tp, MII_BMCR, data);
  1954. for (i = 0; i < 50; i++) {
  1955. msleep(20);
  1956. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1957. break;
  1958. }
  1959. }
  1960. static void r8153_teredo_off(struct r8152 *tp)
  1961. {
  1962. u32 ocp_data;
  1963. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1964. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1965. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1966. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1967. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1968. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1969. }
  1970. static void r8152b_disable_aldps(struct r8152 *tp)
  1971. {
  1972. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1973. msleep(20);
  1974. }
  1975. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1976. {
  1977. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1978. LINKENA | DIS_SDSAVE);
  1979. }
  1980. static void rtl8152_disable(struct r8152 *tp)
  1981. {
  1982. r8152b_disable_aldps(tp);
  1983. rtl_disable(tp);
  1984. r8152b_enable_aldps(tp);
  1985. }
  1986. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1987. {
  1988. u16 data;
  1989. data = r8152_mdio_read(tp, MII_BMCR);
  1990. if (data & BMCR_PDOWN) {
  1991. data &= ~BMCR_PDOWN;
  1992. r8152_mdio_write(tp, MII_BMCR, data);
  1993. }
  1994. set_bit(PHY_RESET, &tp->flags);
  1995. }
  1996. static void r8152b_exit_oob(struct r8152 *tp)
  1997. {
  1998. u32 ocp_data;
  1999. int i;
  2000. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2001. ocp_data &= ~RCR_ACPT_ALL;
  2002. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2003. rxdy_gated_en(tp, true);
  2004. r8153_teredo_off(tp);
  2005. r8152b_hw_phy_cfg(tp);
  2006. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2007. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  2008. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2009. ocp_data &= ~NOW_IS_OOB;
  2010. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2011. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2012. ocp_data &= ~MCU_BORW_EN;
  2013. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2014. for (i = 0; i < 1000; i++) {
  2015. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2016. if (ocp_data & LINK_LIST_READY)
  2017. break;
  2018. usleep_range(1000, 2000);
  2019. }
  2020. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2021. ocp_data |= RE_INIT_LL;
  2022. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2023. for (i = 0; i < 1000; i++) {
  2024. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2025. if (ocp_data & LINK_LIST_READY)
  2026. break;
  2027. usleep_range(1000, 2000);
  2028. }
  2029. rtl8152_nic_reset(tp);
  2030. /* rx share fifo credit full threshold */
  2031. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2032. if (tp->udev->speed == USB_SPEED_FULL ||
  2033. tp->udev->speed == USB_SPEED_LOW) {
  2034. /* rx share fifo credit near full threshold */
  2035. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2036. RXFIFO_THR2_FULL);
  2037. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2038. RXFIFO_THR3_FULL);
  2039. } else {
  2040. /* rx share fifo credit near full threshold */
  2041. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2042. RXFIFO_THR2_HIGH);
  2043. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2044. RXFIFO_THR3_HIGH);
  2045. }
  2046. /* TX share fifo free credit full threshold */
  2047. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2048. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2049. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2050. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2051. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2052. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2053. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2054. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2055. ocp_data |= TCR0_AUTO_FIFO;
  2056. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2057. }
  2058. static void r8152b_enter_oob(struct r8152 *tp)
  2059. {
  2060. u32 ocp_data;
  2061. int i;
  2062. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2063. ocp_data &= ~NOW_IS_OOB;
  2064. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2065. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2066. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2067. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2068. rtl_disable(tp);
  2069. for (i = 0; i < 1000; i++) {
  2070. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2071. if (ocp_data & LINK_LIST_READY)
  2072. break;
  2073. usleep_range(1000, 2000);
  2074. }
  2075. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2076. ocp_data |= RE_INIT_LL;
  2077. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2078. for (i = 0; i < 1000; i++) {
  2079. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2080. if (ocp_data & LINK_LIST_READY)
  2081. break;
  2082. usleep_range(1000, 2000);
  2083. }
  2084. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2085. rtl_rx_vlan_en(tp, true);
  2086. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2087. ocp_data |= ALDPS_PROXY_MODE;
  2088. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2089. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2090. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2091. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2092. rxdy_gated_en(tp, false);
  2093. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2094. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2095. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2096. }
  2097. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2098. {
  2099. u32 ocp_data;
  2100. u16 data;
  2101. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  2102. tp->version == RTL_VER_05)
  2103. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2104. data = r8152_mdio_read(tp, MII_BMCR);
  2105. if (data & BMCR_PDOWN) {
  2106. data &= ~BMCR_PDOWN;
  2107. r8152_mdio_write(tp, MII_BMCR, data);
  2108. }
  2109. if (tp->version == RTL_VER_03) {
  2110. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2111. data &= ~CTAP_SHORT_EN;
  2112. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2113. }
  2114. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2115. data |= EEE_CLKDIV_EN;
  2116. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2117. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2118. data |= EN_10M_BGOFF;
  2119. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2120. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2121. data |= EN_10M_PLLOFF;
  2122. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2123. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2124. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2125. ocp_data |= PFM_PWM_SWITCH;
  2126. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2127. /* Enable LPF corner auto tune */
  2128. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2129. /* Adjust 10M Amplitude */
  2130. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2131. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2132. set_bit(PHY_RESET, &tp->flags);
  2133. }
  2134. static void r8153_first_init(struct r8152 *tp)
  2135. {
  2136. u32 ocp_data;
  2137. int i;
  2138. rxdy_gated_en(tp, true);
  2139. r8153_teredo_off(tp);
  2140. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2141. ocp_data &= ~RCR_ACPT_ALL;
  2142. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2143. r8153_hw_phy_cfg(tp);
  2144. rtl8152_nic_reset(tp);
  2145. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2146. ocp_data &= ~NOW_IS_OOB;
  2147. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2148. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2149. ocp_data &= ~MCU_BORW_EN;
  2150. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2151. for (i = 0; i < 1000; i++) {
  2152. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2153. if (ocp_data & LINK_LIST_READY)
  2154. break;
  2155. usleep_range(1000, 2000);
  2156. }
  2157. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2158. ocp_data |= RE_INIT_LL;
  2159. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2160. for (i = 0; i < 1000; i++) {
  2161. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2162. if (ocp_data & LINK_LIST_READY)
  2163. break;
  2164. usleep_range(1000, 2000);
  2165. }
  2166. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2167. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2168. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2169. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2170. ocp_data |= TCR0_AUTO_FIFO;
  2171. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2172. rtl8152_nic_reset(tp);
  2173. /* rx share fifo credit full threshold */
  2174. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2175. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2176. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2177. /* TX share fifo free credit full threshold */
  2178. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2179. /* rx aggregation */
  2180. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2181. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2182. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2183. }
  2184. static void r8153_enter_oob(struct r8152 *tp)
  2185. {
  2186. u32 ocp_data;
  2187. int i;
  2188. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2189. ocp_data &= ~NOW_IS_OOB;
  2190. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2191. rtl_disable(tp);
  2192. for (i = 0; i < 1000; i++) {
  2193. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2194. if (ocp_data & LINK_LIST_READY)
  2195. break;
  2196. usleep_range(1000, 2000);
  2197. }
  2198. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2199. ocp_data |= RE_INIT_LL;
  2200. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2201. for (i = 0; i < 1000; i++) {
  2202. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2203. if (ocp_data & LINK_LIST_READY)
  2204. break;
  2205. usleep_range(1000, 2000);
  2206. }
  2207. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2208. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2209. ocp_data &= ~TEREDO_WAKE_MASK;
  2210. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2211. rtl_rx_vlan_en(tp, true);
  2212. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2213. ocp_data |= ALDPS_PROXY_MODE;
  2214. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2215. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2216. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2217. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2218. rxdy_gated_en(tp, false);
  2219. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2220. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2221. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2222. }
  2223. static void r8153_disable_aldps(struct r8152 *tp)
  2224. {
  2225. u16 data;
  2226. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2227. data &= ~EN_ALDPS;
  2228. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2229. msleep(20);
  2230. }
  2231. static void r8153_enable_aldps(struct r8152 *tp)
  2232. {
  2233. u16 data;
  2234. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2235. data |= EN_ALDPS;
  2236. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2237. }
  2238. static void rtl8153_disable(struct r8152 *tp)
  2239. {
  2240. r8153_disable_aldps(tp);
  2241. rtl_disable(tp);
  2242. r8153_enable_aldps(tp);
  2243. usb_enable_lpm(tp->udev);
  2244. }
  2245. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2246. {
  2247. u16 bmcr, anar, gbcr;
  2248. int ret = 0;
  2249. cancel_delayed_work_sync(&tp->schedule);
  2250. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2251. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2252. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2253. if (tp->mii.supports_gmii) {
  2254. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2255. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2256. } else {
  2257. gbcr = 0;
  2258. }
  2259. if (autoneg == AUTONEG_DISABLE) {
  2260. if (speed == SPEED_10) {
  2261. bmcr = 0;
  2262. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2263. } else if (speed == SPEED_100) {
  2264. bmcr = BMCR_SPEED100;
  2265. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2266. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2267. bmcr = BMCR_SPEED1000;
  2268. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2269. } else {
  2270. ret = -EINVAL;
  2271. goto out;
  2272. }
  2273. if (duplex == DUPLEX_FULL)
  2274. bmcr |= BMCR_FULLDPLX;
  2275. } else {
  2276. if (speed == SPEED_10) {
  2277. if (duplex == DUPLEX_FULL)
  2278. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2279. else
  2280. anar |= ADVERTISE_10HALF;
  2281. } else if (speed == SPEED_100) {
  2282. if (duplex == DUPLEX_FULL) {
  2283. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2284. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2285. } else {
  2286. anar |= ADVERTISE_10HALF;
  2287. anar |= ADVERTISE_100HALF;
  2288. }
  2289. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2290. if (duplex == DUPLEX_FULL) {
  2291. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2292. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2293. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2294. } else {
  2295. anar |= ADVERTISE_10HALF;
  2296. anar |= ADVERTISE_100HALF;
  2297. gbcr |= ADVERTISE_1000HALF;
  2298. }
  2299. } else {
  2300. ret = -EINVAL;
  2301. goto out;
  2302. }
  2303. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2304. }
  2305. if (test_bit(PHY_RESET, &tp->flags))
  2306. bmcr |= BMCR_RESET;
  2307. if (tp->mii.supports_gmii)
  2308. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2309. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2310. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2311. if (test_and_clear_bit(PHY_RESET, &tp->flags)) {
  2312. int i;
  2313. for (i = 0; i < 50; i++) {
  2314. msleep(20);
  2315. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2316. break;
  2317. }
  2318. }
  2319. out:
  2320. return ret;
  2321. }
  2322. static void rtl8152_up(struct r8152 *tp)
  2323. {
  2324. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2325. return;
  2326. r8152b_disable_aldps(tp);
  2327. r8152b_exit_oob(tp);
  2328. r8152b_enable_aldps(tp);
  2329. }
  2330. static void rtl8152_down(struct r8152 *tp)
  2331. {
  2332. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2333. rtl_drop_queued_tx(tp);
  2334. return;
  2335. }
  2336. r8152_power_cut_en(tp, false);
  2337. r8152b_disable_aldps(tp);
  2338. r8152b_enter_oob(tp);
  2339. r8152b_enable_aldps(tp);
  2340. }
  2341. static void rtl8153_up(struct r8152 *tp)
  2342. {
  2343. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2344. return;
  2345. r8153_u1u2en(tp, false);
  2346. r8153_disable_aldps(tp);
  2347. r8153_first_init(tp);
  2348. r8153_enable_aldps(tp);
  2349. r8153_u2p3en(tp, true);
  2350. r8153_u1u2en(tp, true);
  2351. usb_enable_lpm(tp->udev);
  2352. }
  2353. static void rtl8153_down(struct r8152 *tp)
  2354. {
  2355. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2356. rtl_drop_queued_tx(tp);
  2357. return;
  2358. }
  2359. r8153_u1u2en(tp, false);
  2360. r8153_u2p3en(tp, false);
  2361. r8153_power_cut_en(tp, false);
  2362. r8153_disable_aldps(tp);
  2363. r8153_enter_oob(tp);
  2364. r8153_enable_aldps(tp);
  2365. }
  2366. static bool rtl8152_in_nway(struct r8152 *tp)
  2367. {
  2368. u16 nway_state;
  2369. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  2370. tp->ocp_base = 0x2000;
  2371. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  2372. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  2373. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  2374. if (nway_state & 0xc000)
  2375. return false;
  2376. else
  2377. return true;
  2378. }
  2379. static bool rtl8153_in_nway(struct r8152 *tp)
  2380. {
  2381. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  2382. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  2383. return false;
  2384. else
  2385. return true;
  2386. }
  2387. static void set_carrier(struct r8152 *tp)
  2388. {
  2389. struct net_device *netdev = tp->netdev;
  2390. u8 speed;
  2391. speed = rtl8152_get_speed(tp);
  2392. if (speed & LINK_STATUS) {
  2393. if (!netif_carrier_ok(netdev)) {
  2394. tp->rtl_ops.enable(tp);
  2395. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2396. napi_disable(&tp->napi);
  2397. netif_carrier_on(netdev);
  2398. rtl_start_rx(tp);
  2399. napi_enable(&tp->napi);
  2400. }
  2401. } else {
  2402. if (netif_carrier_ok(netdev)) {
  2403. netif_carrier_off(netdev);
  2404. napi_disable(&tp->napi);
  2405. tp->rtl_ops.disable(tp);
  2406. napi_enable(&tp->napi);
  2407. }
  2408. }
  2409. }
  2410. static void rtl_work_func_t(struct work_struct *work)
  2411. {
  2412. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2413. /* If the device is unplugged or !netif_running(), the workqueue
  2414. * doesn't need to wake the device, and could return directly.
  2415. */
  2416. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2417. return;
  2418. if (usb_autopm_get_interface(tp->intf) < 0)
  2419. return;
  2420. if (!test_bit(WORK_ENABLE, &tp->flags))
  2421. goto out1;
  2422. if (!mutex_trylock(&tp->control)) {
  2423. schedule_delayed_work(&tp->schedule, 0);
  2424. goto out1;
  2425. }
  2426. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  2427. set_carrier(tp);
  2428. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2429. _rtl8152_set_rx_mode(tp->netdev);
  2430. /* don't schedule napi before linking */
  2431. if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
  2432. netif_carrier_ok(tp->netdev))
  2433. napi_schedule(&tp->napi);
  2434. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  2435. rtl_phy_reset(tp);
  2436. mutex_unlock(&tp->control);
  2437. out1:
  2438. usb_autopm_put_interface(tp->intf);
  2439. }
  2440. static int rtl8152_open(struct net_device *netdev)
  2441. {
  2442. struct r8152 *tp = netdev_priv(netdev);
  2443. int res = 0;
  2444. res = alloc_all_mem(tp);
  2445. if (res)
  2446. goto out;
  2447. netif_carrier_off(netdev);
  2448. res = usb_autopm_get_interface(tp->intf);
  2449. if (res < 0) {
  2450. free_all_mem(tp);
  2451. goto out;
  2452. }
  2453. mutex_lock(&tp->control);
  2454. tp->rtl_ops.up(tp);
  2455. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2456. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2457. DUPLEX_FULL);
  2458. netif_carrier_off(netdev);
  2459. netif_start_queue(netdev);
  2460. set_bit(WORK_ENABLE, &tp->flags);
  2461. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2462. if (res) {
  2463. if (res == -ENODEV)
  2464. netif_device_detach(tp->netdev);
  2465. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2466. res);
  2467. free_all_mem(tp);
  2468. } else {
  2469. napi_enable(&tp->napi);
  2470. }
  2471. mutex_unlock(&tp->control);
  2472. usb_autopm_put_interface(tp->intf);
  2473. out:
  2474. return res;
  2475. }
  2476. static int rtl8152_close(struct net_device *netdev)
  2477. {
  2478. struct r8152 *tp = netdev_priv(netdev);
  2479. int res = 0;
  2480. napi_disable(&tp->napi);
  2481. clear_bit(WORK_ENABLE, &tp->flags);
  2482. usb_kill_urb(tp->intr_urb);
  2483. cancel_delayed_work_sync(&tp->schedule);
  2484. netif_stop_queue(netdev);
  2485. res = usb_autopm_get_interface(tp->intf);
  2486. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2487. rtl_drop_queued_tx(tp);
  2488. rtl_stop_rx(tp);
  2489. } else {
  2490. mutex_lock(&tp->control);
  2491. tp->rtl_ops.down(tp);
  2492. mutex_unlock(&tp->control);
  2493. usb_autopm_put_interface(tp->intf);
  2494. }
  2495. free_all_mem(tp);
  2496. return res;
  2497. }
  2498. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2499. {
  2500. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2501. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2502. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2503. }
  2504. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2505. {
  2506. u16 data;
  2507. r8152_mmd_indirect(tp, dev, reg);
  2508. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2509. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2510. return data;
  2511. }
  2512. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2513. {
  2514. r8152_mmd_indirect(tp, dev, reg);
  2515. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2516. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2517. }
  2518. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2519. {
  2520. u16 config1, config2, config3;
  2521. u32 ocp_data;
  2522. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2523. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2524. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2525. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2526. if (enable) {
  2527. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2528. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2529. config1 |= sd_rise_time(1);
  2530. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2531. config3 |= fast_snr(42);
  2532. } else {
  2533. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2534. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2535. RX_QUIET_EN);
  2536. config1 |= sd_rise_time(7);
  2537. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2538. config3 |= fast_snr(511);
  2539. }
  2540. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2541. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2542. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2543. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2544. }
  2545. static void r8152b_enable_eee(struct r8152 *tp)
  2546. {
  2547. r8152_eee_en(tp, true);
  2548. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2549. }
  2550. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2551. {
  2552. u32 ocp_data;
  2553. u16 config;
  2554. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2555. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2556. if (enable) {
  2557. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2558. config |= EEE10_EN;
  2559. } else {
  2560. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2561. config &= ~EEE10_EN;
  2562. }
  2563. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2564. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2565. }
  2566. static void r8153_enable_eee(struct r8152 *tp)
  2567. {
  2568. r8153_eee_en(tp, true);
  2569. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2570. }
  2571. static void r8152b_enable_fc(struct r8152 *tp)
  2572. {
  2573. u16 anar;
  2574. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2575. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2576. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2577. }
  2578. static void rtl_tally_reset(struct r8152 *tp)
  2579. {
  2580. u32 ocp_data;
  2581. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2582. ocp_data |= TALLY_RESET;
  2583. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2584. }
  2585. static void r8152b_init(struct r8152 *tp)
  2586. {
  2587. u32 ocp_data;
  2588. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2589. return;
  2590. r8152b_disable_aldps(tp);
  2591. if (tp->version == RTL_VER_01) {
  2592. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2593. ocp_data &= ~LED_MODE_MASK;
  2594. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2595. }
  2596. r8152_power_cut_en(tp, false);
  2597. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2598. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2599. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2600. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2601. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2602. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2603. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2604. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2605. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2606. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2607. r8152b_enable_eee(tp);
  2608. r8152b_enable_aldps(tp);
  2609. r8152b_enable_fc(tp);
  2610. rtl_tally_reset(tp);
  2611. /* enable rx aggregation */
  2612. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2613. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2614. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2615. }
  2616. static void r8153_init(struct r8152 *tp)
  2617. {
  2618. u32 ocp_data;
  2619. int i;
  2620. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2621. return;
  2622. r8153_disable_aldps(tp);
  2623. r8153_u1u2en(tp, false);
  2624. for (i = 0; i < 500; i++) {
  2625. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2626. AUTOLOAD_DONE)
  2627. break;
  2628. msleep(20);
  2629. }
  2630. for (i = 0; i < 500; i++) {
  2631. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2632. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2633. break;
  2634. msleep(20);
  2635. }
  2636. usb_disable_lpm(tp->udev);
  2637. r8153_u2p3en(tp, false);
  2638. if (tp->version == RTL_VER_04) {
  2639. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2640. ocp_data &= ~pwd_dn_scale_mask;
  2641. ocp_data |= pwd_dn_scale(96);
  2642. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2643. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2644. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2645. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2646. } else if (tp->version == RTL_VER_05) {
  2647. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2648. ocp_data &= ~ECM_ALDPS;
  2649. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2650. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2651. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2652. ocp_data &= ~DYNAMIC_BURST;
  2653. else
  2654. ocp_data |= DYNAMIC_BURST;
  2655. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2656. } else if (tp->version == RTL_VER_06) {
  2657. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2658. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2659. ocp_data &= ~DYNAMIC_BURST;
  2660. else
  2661. ocp_data |= DYNAMIC_BURST;
  2662. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2663. }
  2664. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2665. ocp_data |= EP4_FULL_FC;
  2666. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2667. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2668. ocp_data &= ~TIMER11_EN;
  2669. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2670. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2671. ocp_data &= ~LED_MODE_MASK;
  2672. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2673. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2674. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  2675. ocp_data |= LPM_TIMER_500MS;
  2676. else
  2677. ocp_data |= LPM_TIMER_500US;
  2678. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2679. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2680. ocp_data &= ~SEN_VAL_MASK;
  2681. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2682. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2683. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2684. r8153_power_cut_en(tp, false);
  2685. r8153_u1u2en(tp, true);
  2686. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2687. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2688. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2689. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2690. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2691. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2692. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2693. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2694. EEE_SPDWN_EN);
  2695. r8153_enable_eee(tp);
  2696. r8153_enable_aldps(tp);
  2697. r8152b_enable_fc(tp);
  2698. rtl_tally_reset(tp);
  2699. r8153_u2p3en(tp, true);
  2700. }
  2701. static int rtl8152_pre_reset(struct usb_interface *intf)
  2702. {
  2703. struct r8152 *tp = usb_get_intfdata(intf);
  2704. struct net_device *netdev;
  2705. if (!tp)
  2706. return 0;
  2707. netdev = tp->netdev;
  2708. if (!netif_running(netdev))
  2709. return 0;
  2710. napi_disable(&tp->napi);
  2711. clear_bit(WORK_ENABLE, &tp->flags);
  2712. usb_kill_urb(tp->intr_urb);
  2713. cancel_delayed_work_sync(&tp->schedule);
  2714. if (netif_carrier_ok(netdev)) {
  2715. netif_stop_queue(netdev);
  2716. mutex_lock(&tp->control);
  2717. tp->rtl_ops.disable(tp);
  2718. mutex_unlock(&tp->control);
  2719. }
  2720. return 0;
  2721. }
  2722. static int rtl8152_post_reset(struct usb_interface *intf)
  2723. {
  2724. struct r8152 *tp = usb_get_intfdata(intf);
  2725. struct net_device *netdev;
  2726. if (!tp)
  2727. return 0;
  2728. netdev = tp->netdev;
  2729. if (!netif_running(netdev))
  2730. return 0;
  2731. set_bit(WORK_ENABLE, &tp->flags);
  2732. if (netif_carrier_ok(netdev)) {
  2733. mutex_lock(&tp->control);
  2734. tp->rtl_ops.enable(tp);
  2735. rtl8152_set_rx_mode(netdev);
  2736. mutex_unlock(&tp->control);
  2737. netif_wake_queue(netdev);
  2738. }
  2739. napi_enable(&tp->napi);
  2740. return 0;
  2741. }
  2742. static bool delay_autosuspend(struct r8152 *tp)
  2743. {
  2744. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  2745. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  2746. /* This means a linking change occurs and the driver doesn't detect it,
  2747. * yet. If the driver has disabled tx/rx and hw is linking on, the
  2748. * device wouldn't wake up by receiving any packet.
  2749. */
  2750. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  2751. return true;
  2752. /* If the linking down is occurred by nway, the device may miss the
  2753. * linking change event. And it wouldn't wake when linking on.
  2754. */
  2755. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  2756. return true;
  2757. else
  2758. return false;
  2759. }
  2760. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2761. {
  2762. struct r8152 *tp = usb_get_intfdata(intf);
  2763. struct net_device *netdev = tp->netdev;
  2764. int ret = 0;
  2765. mutex_lock(&tp->control);
  2766. if (PMSG_IS_AUTO(message)) {
  2767. if (netif_running(netdev) && delay_autosuspend(tp)) {
  2768. ret = -EBUSY;
  2769. goto out1;
  2770. }
  2771. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2772. } else {
  2773. netif_device_detach(netdev);
  2774. }
  2775. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2776. clear_bit(WORK_ENABLE, &tp->flags);
  2777. usb_kill_urb(tp->intr_urb);
  2778. napi_disable(&tp->napi);
  2779. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2780. rtl_stop_rx(tp);
  2781. rtl_runtime_suspend_enable(tp, true);
  2782. } else {
  2783. cancel_delayed_work_sync(&tp->schedule);
  2784. tp->rtl_ops.down(tp);
  2785. }
  2786. napi_enable(&tp->napi);
  2787. }
  2788. out1:
  2789. mutex_unlock(&tp->control);
  2790. return ret;
  2791. }
  2792. static int rtl8152_resume(struct usb_interface *intf)
  2793. {
  2794. struct r8152 *tp = usb_get_intfdata(intf);
  2795. mutex_lock(&tp->control);
  2796. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2797. tp->rtl_ops.init(tp);
  2798. netif_device_attach(tp->netdev);
  2799. }
  2800. if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
  2801. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2802. rtl_runtime_suspend_enable(tp, false);
  2803. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2804. napi_disable(&tp->napi);
  2805. set_bit(WORK_ENABLE, &tp->flags);
  2806. if (netif_carrier_ok(tp->netdev))
  2807. rtl_start_rx(tp);
  2808. napi_enable(&tp->napi);
  2809. } else {
  2810. tp->rtl_ops.up(tp);
  2811. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2812. tp->mii.supports_gmii ?
  2813. SPEED_1000 : SPEED_100,
  2814. DUPLEX_FULL);
  2815. netif_carrier_off(tp->netdev);
  2816. set_bit(WORK_ENABLE, &tp->flags);
  2817. }
  2818. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2819. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2820. if (tp->netdev->flags & IFF_UP)
  2821. rtl_runtime_suspend_enable(tp, false);
  2822. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2823. }
  2824. mutex_unlock(&tp->control);
  2825. return 0;
  2826. }
  2827. static int rtl8152_reset_resume(struct usb_interface *intf)
  2828. {
  2829. struct r8152 *tp = usb_get_intfdata(intf);
  2830. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2831. return rtl8152_resume(intf);
  2832. }
  2833. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2834. {
  2835. struct r8152 *tp = netdev_priv(dev);
  2836. if (usb_autopm_get_interface(tp->intf) < 0)
  2837. return;
  2838. if (!rtl_can_wakeup(tp)) {
  2839. wol->supported = 0;
  2840. wol->wolopts = 0;
  2841. } else {
  2842. mutex_lock(&tp->control);
  2843. wol->supported = WAKE_ANY;
  2844. wol->wolopts = __rtl_get_wol(tp);
  2845. mutex_unlock(&tp->control);
  2846. }
  2847. usb_autopm_put_interface(tp->intf);
  2848. }
  2849. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2850. {
  2851. struct r8152 *tp = netdev_priv(dev);
  2852. int ret;
  2853. if (!rtl_can_wakeup(tp))
  2854. return -EOPNOTSUPP;
  2855. ret = usb_autopm_get_interface(tp->intf);
  2856. if (ret < 0)
  2857. goto out_set_wol;
  2858. mutex_lock(&tp->control);
  2859. __rtl_set_wol(tp, wol->wolopts);
  2860. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2861. mutex_unlock(&tp->control);
  2862. usb_autopm_put_interface(tp->intf);
  2863. out_set_wol:
  2864. return ret;
  2865. }
  2866. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2867. {
  2868. struct r8152 *tp = netdev_priv(dev);
  2869. return tp->msg_enable;
  2870. }
  2871. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2872. {
  2873. struct r8152 *tp = netdev_priv(dev);
  2874. tp->msg_enable = value;
  2875. }
  2876. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2877. struct ethtool_drvinfo *info)
  2878. {
  2879. struct r8152 *tp = netdev_priv(netdev);
  2880. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2881. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2882. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2883. }
  2884. static
  2885. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2886. {
  2887. struct r8152 *tp = netdev_priv(netdev);
  2888. int ret;
  2889. if (!tp->mii.mdio_read)
  2890. return -EOPNOTSUPP;
  2891. ret = usb_autopm_get_interface(tp->intf);
  2892. if (ret < 0)
  2893. goto out;
  2894. mutex_lock(&tp->control);
  2895. ret = mii_ethtool_gset(&tp->mii, cmd);
  2896. mutex_unlock(&tp->control);
  2897. usb_autopm_put_interface(tp->intf);
  2898. out:
  2899. return ret;
  2900. }
  2901. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2902. {
  2903. struct r8152 *tp = netdev_priv(dev);
  2904. int ret;
  2905. ret = usb_autopm_get_interface(tp->intf);
  2906. if (ret < 0)
  2907. goto out;
  2908. mutex_lock(&tp->control);
  2909. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  2910. mutex_unlock(&tp->control);
  2911. usb_autopm_put_interface(tp->intf);
  2912. out:
  2913. return ret;
  2914. }
  2915. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  2916. "tx_packets",
  2917. "rx_packets",
  2918. "tx_errors",
  2919. "rx_errors",
  2920. "rx_missed",
  2921. "align_errors",
  2922. "tx_single_collisions",
  2923. "tx_multi_collisions",
  2924. "rx_unicast",
  2925. "rx_broadcast",
  2926. "rx_multicast",
  2927. "tx_aborted",
  2928. "tx_underrun",
  2929. };
  2930. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  2931. {
  2932. switch (sset) {
  2933. case ETH_SS_STATS:
  2934. return ARRAY_SIZE(rtl8152_gstrings);
  2935. default:
  2936. return -EOPNOTSUPP;
  2937. }
  2938. }
  2939. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  2940. struct ethtool_stats *stats, u64 *data)
  2941. {
  2942. struct r8152 *tp = netdev_priv(dev);
  2943. struct tally_counter tally;
  2944. if (usb_autopm_get_interface(tp->intf) < 0)
  2945. return;
  2946. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  2947. usb_autopm_put_interface(tp->intf);
  2948. data[0] = le64_to_cpu(tally.tx_packets);
  2949. data[1] = le64_to_cpu(tally.rx_packets);
  2950. data[2] = le64_to_cpu(tally.tx_errors);
  2951. data[3] = le32_to_cpu(tally.rx_errors);
  2952. data[4] = le16_to_cpu(tally.rx_missed);
  2953. data[5] = le16_to_cpu(tally.align_errors);
  2954. data[6] = le32_to_cpu(tally.tx_one_collision);
  2955. data[7] = le32_to_cpu(tally.tx_multi_collision);
  2956. data[8] = le64_to_cpu(tally.rx_unicast);
  2957. data[9] = le64_to_cpu(tally.rx_broadcast);
  2958. data[10] = le32_to_cpu(tally.rx_multicast);
  2959. data[11] = le16_to_cpu(tally.tx_aborted);
  2960. data[12] = le16_to_cpu(tally.tx_underrun);
  2961. }
  2962. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2963. {
  2964. switch (stringset) {
  2965. case ETH_SS_STATS:
  2966. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  2967. break;
  2968. }
  2969. }
  2970. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2971. {
  2972. u32 ocp_data, lp, adv, supported = 0;
  2973. u16 val;
  2974. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  2975. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2976. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  2977. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2978. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  2979. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2980. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2981. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2982. eee->eee_enabled = !!ocp_data;
  2983. eee->eee_active = !!(supported & adv & lp);
  2984. eee->supported = supported;
  2985. eee->advertised = adv;
  2986. eee->lp_advertised = lp;
  2987. return 0;
  2988. }
  2989. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2990. {
  2991. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2992. r8152_eee_en(tp, eee->eee_enabled);
  2993. if (!eee->eee_enabled)
  2994. val = 0;
  2995. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  2996. return 0;
  2997. }
  2998. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2999. {
  3000. u32 ocp_data, lp, adv, supported = 0;
  3001. u16 val;
  3002. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  3003. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3004. val = ocp_reg_read(tp, OCP_EEE_ADV);
  3005. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3006. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  3007. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3008. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3009. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3010. eee->eee_enabled = !!ocp_data;
  3011. eee->eee_active = !!(supported & adv & lp);
  3012. eee->supported = supported;
  3013. eee->advertised = adv;
  3014. eee->lp_advertised = lp;
  3015. return 0;
  3016. }
  3017. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3018. {
  3019. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3020. r8153_eee_en(tp, eee->eee_enabled);
  3021. if (!eee->eee_enabled)
  3022. val = 0;
  3023. ocp_reg_write(tp, OCP_EEE_ADV, val);
  3024. return 0;
  3025. }
  3026. static int
  3027. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  3028. {
  3029. struct r8152 *tp = netdev_priv(net);
  3030. int ret;
  3031. ret = usb_autopm_get_interface(tp->intf);
  3032. if (ret < 0)
  3033. goto out;
  3034. mutex_lock(&tp->control);
  3035. ret = tp->rtl_ops.eee_get(tp, edata);
  3036. mutex_unlock(&tp->control);
  3037. usb_autopm_put_interface(tp->intf);
  3038. out:
  3039. return ret;
  3040. }
  3041. static int
  3042. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  3043. {
  3044. struct r8152 *tp = netdev_priv(net);
  3045. int ret;
  3046. ret = usb_autopm_get_interface(tp->intf);
  3047. if (ret < 0)
  3048. goto out;
  3049. mutex_lock(&tp->control);
  3050. ret = tp->rtl_ops.eee_set(tp, edata);
  3051. if (!ret)
  3052. ret = mii_nway_restart(&tp->mii);
  3053. mutex_unlock(&tp->control);
  3054. usb_autopm_put_interface(tp->intf);
  3055. out:
  3056. return ret;
  3057. }
  3058. static int rtl8152_nway_reset(struct net_device *dev)
  3059. {
  3060. struct r8152 *tp = netdev_priv(dev);
  3061. int ret;
  3062. ret = usb_autopm_get_interface(tp->intf);
  3063. if (ret < 0)
  3064. goto out;
  3065. mutex_lock(&tp->control);
  3066. ret = mii_nway_restart(&tp->mii);
  3067. mutex_unlock(&tp->control);
  3068. usb_autopm_put_interface(tp->intf);
  3069. out:
  3070. return ret;
  3071. }
  3072. static int rtl8152_get_coalesce(struct net_device *netdev,
  3073. struct ethtool_coalesce *coalesce)
  3074. {
  3075. struct r8152 *tp = netdev_priv(netdev);
  3076. switch (tp->version) {
  3077. case RTL_VER_01:
  3078. case RTL_VER_02:
  3079. return -EOPNOTSUPP;
  3080. default:
  3081. break;
  3082. }
  3083. coalesce->rx_coalesce_usecs = tp->coalesce;
  3084. return 0;
  3085. }
  3086. static int rtl8152_set_coalesce(struct net_device *netdev,
  3087. struct ethtool_coalesce *coalesce)
  3088. {
  3089. struct r8152 *tp = netdev_priv(netdev);
  3090. int ret;
  3091. switch (tp->version) {
  3092. case RTL_VER_01:
  3093. case RTL_VER_02:
  3094. return -EOPNOTSUPP;
  3095. default:
  3096. break;
  3097. }
  3098. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  3099. return -EINVAL;
  3100. ret = usb_autopm_get_interface(tp->intf);
  3101. if (ret < 0)
  3102. return ret;
  3103. mutex_lock(&tp->control);
  3104. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  3105. tp->coalesce = coalesce->rx_coalesce_usecs;
  3106. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  3107. r8153_set_rx_early_timeout(tp);
  3108. }
  3109. mutex_unlock(&tp->control);
  3110. usb_autopm_put_interface(tp->intf);
  3111. return ret;
  3112. }
  3113. static struct ethtool_ops ops = {
  3114. .get_drvinfo = rtl8152_get_drvinfo,
  3115. .get_settings = rtl8152_get_settings,
  3116. .set_settings = rtl8152_set_settings,
  3117. .get_link = ethtool_op_get_link,
  3118. .nway_reset = rtl8152_nway_reset,
  3119. .get_msglevel = rtl8152_get_msglevel,
  3120. .set_msglevel = rtl8152_set_msglevel,
  3121. .get_wol = rtl8152_get_wol,
  3122. .set_wol = rtl8152_set_wol,
  3123. .get_strings = rtl8152_get_strings,
  3124. .get_sset_count = rtl8152_get_sset_count,
  3125. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3126. .get_coalesce = rtl8152_get_coalesce,
  3127. .set_coalesce = rtl8152_set_coalesce,
  3128. .get_eee = rtl_ethtool_get_eee,
  3129. .set_eee = rtl_ethtool_set_eee,
  3130. };
  3131. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3132. {
  3133. struct r8152 *tp = netdev_priv(netdev);
  3134. struct mii_ioctl_data *data = if_mii(rq);
  3135. int res;
  3136. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3137. return -ENODEV;
  3138. res = usb_autopm_get_interface(tp->intf);
  3139. if (res < 0)
  3140. goto out;
  3141. switch (cmd) {
  3142. case SIOCGMIIPHY:
  3143. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3144. break;
  3145. case SIOCGMIIREG:
  3146. mutex_lock(&tp->control);
  3147. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3148. mutex_unlock(&tp->control);
  3149. break;
  3150. case SIOCSMIIREG:
  3151. if (!capable(CAP_NET_ADMIN)) {
  3152. res = -EPERM;
  3153. break;
  3154. }
  3155. mutex_lock(&tp->control);
  3156. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3157. mutex_unlock(&tp->control);
  3158. break;
  3159. default:
  3160. res = -EOPNOTSUPP;
  3161. }
  3162. usb_autopm_put_interface(tp->intf);
  3163. out:
  3164. return res;
  3165. }
  3166. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3167. {
  3168. struct r8152 *tp = netdev_priv(dev);
  3169. int ret;
  3170. switch (tp->version) {
  3171. case RTL_VER_01:
  3172. case RTL_VER_02:
  3173. return eth_change_mtu(dev, new_mtu);
  3174. default:
  3175. break;
  3176. }
  3177. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3178. return -EINVAL;
  3179. ret = usb_autopm_get_interface(tp->intf);
  3180. if (ret < 0)
  3181. return ret;
  3182. mutex_lock(&tp->control);
  3183. dev->mtu = new_mtu;
  3184. if (netif_running(dev) && netif_carrier_ok(dev))
  3185. r8153_set_rx_early_size(tp);
  3186. mutex_unlock(&tp->control);
  3187. usb_autopm_put_interface(tp->intf);
  3188. return ret;
  3189. }
  3190. static const struct net_device_ops rtl8152_netdev_ops = {
  3191. .ndo_open = rtl8152_open,
  3192. .ndo_stop = rtl8152_close,
  3193. .ndo_do_ioctl = rtl8152_ioctl,
  3194. .ndo_start_xmit = rtl8152_start_xmit,
  3195. .ndo_tx_timeout = rtl8152_tx_timeout,
  3196. .ndo_set_features = rtl8152_set_features,
  3197. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3198. .ndo_set_mac_address = rtl8152_set_mac_address,
  3199. .ndo_change_mtu = rtl8152_change_mtu,
  3200. .ndo_validate_addr = eth_validate_addr,
  3201. .ndo_features_check = rtl8152_features_check,
  3202. };
  3203. static void r8152b_get_version(struct r8152 *tp)
  3204. {
  3205. u32 ocp_data;
  3206. u16 version;
  3207. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3208. version = (u16)(ocp_data & VERSION_MASK);
  3209. switch (version) {
  3210. case 0x4c00:
  3211. tp->version = RTL_VER_01;
  3212. break;
  3213. case 0x4c10:
  3214. tp->version = RTL_VER_02;
  3215. break;
  3216. case 0x5c00:
  3217. tp->version = RTL_VER_03;
  3218. tp->mii.supports_gmii = 1;
  3219. break;
  3220. case 0x5c10:
  3221. tp->version = RTL_VER_04;
  3222. tp->mii.supports_gmii = 1;
  3223. break;
  3224. case 0x5c20:
  3225. tp->version = RTL_VER_05;
  3226. tp->mii.supports_gmii = 1;
  3227. break;
  3228. case 0x5c30:
  3229. tp->version = RTL_VER_06;
  3230. tp->mii.supports_gmii = 1;
  3231. break;
  3232. default:
  3233. netif_info(tp, probe, tp->netdev,
  3234. "Unknown version 0x%04x\n", version);
  3235. break;
  3236. }
  3237. }
  3238. static void rtl8152_unload(struct r8152 *tp)
  3239. {
  3240. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3241. return;
  3242. if (tp->version != RTL_VER_01)
  3243. r8152_power_cut_en(tp, true);
  3244. }
  3245. static void rtl8153_unload(struct r8152 *tp)
  3246. {
  3247. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3248. return;
  3249. r8153_power_cut_en(tp, false);
  3250. }
  3251. static int rtl_ops_init(struct r8152 *tp)
  3252. {
  3253. struct rtl_ops *ops = &tp->rtl_ops;
  3254. int ret = 0;
  3255. switch (tp->version) {
  3256. case RTL_VER_01:
  3257. case RTL_VER_02:
  3258. ops->init = r8152b_init;
  3259. ops->enable = rtl8152_enable;
  3260. ops->disable = rtl8152_disable;
  3261. ops->up = rtl8152_up;
  3262. ops->down = rtl8152_down;
  3263. ops->unload = rtl8152_unload;
  3264. ops->eee_get = r8152_get_eee;
  3265. ops->eee_set = r8152_set_eee;
  3266. ops->in_nway = rtl8152_in_nway;
  3267. break;
  3268. case RTL_VER_03:
  3269. case RTL_VER_04:
  3270. case RTL_VER_05:
  3271. case RTL_VER_06:
  3272. ops->init = r8153_init;
  3273. ops->enable = rtl8153_enable;
  3274. ops->disable = rtl8153_disable;
  3275. ops->up = rtl8153_up;
  3276. ops->down = rtl8153_down;
  3277. ops->unload = rtl8153_unload;
  3278. ops->eee_get = r8153_get_eee;
  3279. ops->eee_set = r8153_set_eee;
  3280. ops->in_nway = rtl8153_in_nway;
  3281. break;
  3282. default:
  3283. ret = -ENODEV;
  3284. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3285. break;
  3286. }
  3287. return ret;
  3288. }
  3289. static int rtl8152_probe(struct usb_interface *intf,
  3290. const struct usb_device_id *id)
  3291. {
  3292. struct usb_device *udev = interface_to_usbdev(intf);
  3293. struct r8152 *tp;
  3294. struct net_device *netdev;
  3295. int ret;
  3296. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3297. usb_driver_set_configuration(udev, 1);
  3298. return -ENODEV;
  3299. }
  3300. usb_reset_device(udev);
  3301. netdev = alloc_etherdev(sizeof(struct r8152));
  3302. if (!netdev) {
  3303. dev_err(&intf->dev, "Out of memory\n");
  3304. return -ENOMEM;
  3305. }
  3306. SET_NETDEV_DEV(netdev, &intf->dev);
  3307. tp = netdev_priv(netdev);
  3308. tp->msg_enable = 0x7FFF;
  3309. tp->udev = udev;
  3310. tp->netdev = netdev;
  3311. tp->intf = intf;
  3312. r8152b_get_version(tp);
  3313. ret = rtl_ops_init(tp);
  3314. if (ret)
  3315. goto out;
  3316. mutex_init(&tp->control);
  3317. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3318. netdev->netdev_ops = &rtl8152_netdev_ops;
  3319. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3320. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3321. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3322. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3323. NETIF_F_HW_VLAN_CTAG_TX;
  3324. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3325. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3326. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3327. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3328. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3329. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3330. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3331. netdev->ethtool_ops = &ops;
  3332. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3333. tp->mii.dev = netdev;
  3334. tp->mii.mdio_read = read_mii_word;
  3335. tp->mii.mdio_write = write_mii_word;
  3336. tp->mii.phy_id_mask = 0x3f;
  3337. tp->mii.reg_num_mask = 0x1f;
  3338. tp->mii.phy_id = R8152_PHY_ID;
  3339. switch (udev->speed) {
  3340. case USB_SPEED_SUPER:
  3341. tp->coalesce = COALESCE_SUPER;
  3342. break;
  3343. case USB_SPEED_HIGH:
  3344. tp->coalesce = COALESCE_HIGH;
  3345. break;
  3346. default:
  3347. tp->coalesce = COALESCE_SLOW;
  3348. break;
  3349. }
  3350. intf->needs_remote_wakeup = 1;
  3351. tp->rtl_ops.init(tp);
  3352. set_ethernet_addr(tp);
  3353. usb_set_intfdata(intf, tp);
  3354. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3355. ret = register_netdev(netdev);
  3356. if (ret != 0) {
  3357. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3358. goto out1;
  3359. }
  3360. if (!rtl_can_wakeup(tp))
  3361. __rtl_set_wol(tp, 0);
  3362. tp->saved_wolopts = __rtl_get_wol(tp);
  3363. if (tp->saved_wolopts)
  3364. device_set_wakeup_enable(&udev->dev, true);
  3365. else
  3366. device_set_wakeup_enable(&udev->dev, false);
  3367. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3368. return 0;
  3369. out1:
  3370. netif_napi_del(&tp->napi);
  3371. usb_set_intfdata(intf, NULL);
  3372. out:
  3373. free_netdev(netdev);
  3374. return ret;
  3375. }
  3376. static void rtl8152_disconnect(struct usb_interface *intf)
  3377. {
  3378. struct r8152 *tp = usb_get_intfdata(intf);
  3379. usb_set_intfdata(intf, NULL);
  3380. if (tp) {
  3381. struct usb_device *udev = tp->udev;
  3382. if (udev->state == USB_STATE_NOTATTACHED)
  3383. set_bit(RTL8152_UNPLUG, &tp->flags);
  3384. netif_napi_del(&tp->napi);
  3385. unregister_netdev(tp->netdev);
  3386. tp->rtl_ops.unload(tp);
  3387. free_netdev(tp->netdev);
  3388. }
  3389. }
  3390. #define REALTEK_USB_DEVICE(vend, prod) \
  3391. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3392. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3393. .idVendor = (vend), \
  3394. .idProduct = (prod), \
  3395. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3396. }, \
  3397. { \
  3398. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3399. USB_DEVICE_ID_MATCH_DEVICE, \
  3400. .idVendor = (vend), \
  3401. .idProduct = (prod), \
  3402. .bInterfaceClass = USB_CLASS_COMM, \
  3403. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3404. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3405. /* table of devices that work with this driver */
  3406. static struct usb_device_id rtl8152_table[] = {
  3407. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3408. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3409. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3410. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3411. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3412. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  3413. {}
  3414. };
  3415. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3416. static struct usb_driver rtl8152_driver = {
  3417. .name = MODULENAME,
  3418. .id_table = rtl8152_table,
  3419. .probe = rtl8152_probe,
  3420. .disconnect = rtl8152_disconnect,
  3421. .suspend = rtl8152_suspend,
  3422. .resume = rtl8152_resume,
  3423. .reset_resume = rtl8152_reset_resume,
  3424. .pre_reset = rtl8152_pre_reset,
  3425. .post_reset = rtl8152_post_reset,
  3426. .supports_autosuspend = 1,
  3427. .disable_hub_initiated_lpm = 1,
  3428. };
  3429. module_usb_driver(rtl8152_driver);
  3430. MODULE_AUTHOR(DRIVER_AUTHOR);
  3431. MODULE_DESCRIPTION(DRIVER_DESC);
  3432. MODULE_LICENSE("GPL");