omap_crtc.c 17 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_crtc.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/completion.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc.h>
  23. #include <drm/drm_crtc_helper.h>
  24. #include <drm/drm_mode.h>
  25. #include <drm/drm_plane_helper.h>
  26. #include "omap_drv.h"
  27. #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  28. struct omap_crtc {
  29. struct drm_crtc base;
  30. const char *name;
  31. enum omap_channel channel;
  32. struct drm_encoder *current_encoder;
  33. /*
  34. * Temporary: eventually this will go away, but it is needed
  35. * for now to keep the output's happy. (They only need
  36. * mgr->id.) Eventually this will be replaced w/ something
  37. * more common-panel-framework-y
  38. */
  39. struct omap_overlay_manager *mgr;
  40. struct omap_video_timings timings;
  41. struct omap_drm_irq vblank_irq;
  42. struct omap_drm_irq error_irq;
  43. /* pending event */
  44. struct drm_pending_vblank_event *event;
  45. wait_queue_head_t flip_wait;
  46. struct completion completion;
  47. bool ignore_digit_sync_lost;
  48. };
  49. /* -----------------------------------------------------------------------------
  50. * Helper Functions
  51. */
  52. uint32_t pipe2vbl(struct drm_crtc *crtc)
  53. {
  54. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  55. return dispc_mgr_get_vsync_irq(omap_crtc->channel);
  56. }
  57. const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
  58. {
  59. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  60. return &omap_crtc->timings;
  61. }
  62. enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  63. {
  64. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  65. return omap_crtc->channel;
  66. }
  67. /* -----------------------------------------------------------------------------
  68. * DSS Manager Functions
  69. */
  70. /*
  71. * Manager-ops, callbacks from output when they need to configure
  72. * the upstream part of the video pipe.
  73. *
  74. * Most of these we can ignore until we add support for command-mode
  75. * panels.. for video-mode the crtc-helpers already do an adequate
  76. * job of sequencing the setup of the video pipe in the proper order
  77. */
  78. /* ovl-mgr-id -> crtc */
  79. static struct omap_crtc *omap_crtcs[8];
  80. /* we can probably ignore these until we support command-mode panels: */
  81. static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
  82. struct omap_dss_device *dst)
  83. {
  84. if (mgr->output)
  85. return -EINVAL;
  86. if ((mgr->supported_outputs & dst->id) == 0)
  87. return -EINVAL;
  88. dst->manager = mgr;
  89. mgr->output = dst;
  90. return 0;
  91. }
  92. static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
  93. struct omap_dss_device *dst)
  94. {
  95. mgr->output->manager = NULL;
  96. mgr->output = NULL;
  97. }
  98. static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
  99. {
  100. }
  101. /* Called only from omap_crtc_encoder_setup and suspend/resume handlers. */
  102. static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
  103. {
  104. struct drm_device *dev = crtc->dev;
  105. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  106. enum omap_channel channel = omap_crtc->channel;
  107. struct omap_irq_wait *wait;
  108. u32 framedone_irq, vsync_irq;
  109. int ret;
  110. if (dispc_mgr_is_enabled(channel) == enable)
  111. return;
  112. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  113. /*
  114. * Digit output produces some sync lost interrupts during the
  115. * first frame when enabling, so we need to ignore those.
  116. */
  117. omap_crtc->ignore_digit_sync_lost = true;
  118. }
  119. framedone_irq = dispc_mgr_get_framedone_irq(channel);
  120. vsync_irq = dispc_mgr_get_vsync_irq(channel);
  121. if (enable) {
  122. wait = omap_irq_wait_init(dev, vsync_irq, 1);
  123. } else {
  124. /*
  125. * When we disable the digit output, we need to wait for
  126. * FRAMEDONE to know that DISPC has finished with the output.
  127. *
  128. * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
  129. * that case we need to use vsync interrupt, and wait for both
  130. * even and odd frames.
  131. */
  132. if (framedone_irq)
  133. wait = omap_irq_wait_init(dev, framedone_irq, 1);
  134. else
  135. wait = omap_irq_wait_init(dev, vsync_irq, 2);
  136. }
  137. dispc_mgr_enable(channel, enable);
  138. ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
  139. if (ret) {
  140. dev_err(dev->dev, "%s: timeout waiting for %s\n",
  141. omap_crtc->name, enable ? "enable" : "disable");
  142. }
  143. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  144. omap_crtc->ignore_digit_sync_lost = false;
  145. /* make sure the irq handler sees the value above */
  146. mb();
  147. }
  148. }
  149. static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
  150. {
  151. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  152. struct omap_overlay_manager_info info;
  153. memset(&info, 0, sizeof(info));
  154. info.default_color = 0x00000000;
  155. info.trans_key = 0x00000000;
  156. info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
  157. info.trans_enabled = false;
  158. dispc_mgr_setup(omap_crtc->channel, &info);
  159. dispc_mgr_set_timings(omap_crtc->channel,
  160. &omap_crtc->timings);
  161. omap_crtc_set_enabled(&omap_crtc->base, true);
  162. return 0;
  163. }
  164. static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
  165. {
  166. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  167. omap_crtc_set_enabled(&omap_crtc->base, false);
  168. }
  169. static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
  170. const struct omap_video_timings *timings)
  171. {
  172. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  173. DBG("%s", omap_crtc->name);
  174. omap_crtc->timings = *timings;
  175. }
  176. static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
  177. const struct dss_lcd_mgr_config *config)
  178. {
  179. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  180. DBG("%s", omap_crtc->name);
  181. dispc_mgr_set_lcd_config(omap_crtc->channel, config);
  182. }
  183. static int omap_crtc_dss_register_framedone(
  184. struct omap_overlay_manager *mgr,
  185. void (*handler)(void *), void *data)
  186. {
  187. return 0;
  188. }
  189. static void omap_crtc_dss_unregister_framedone(
  190. struct omap_overlay_manager *mgr,
  191. void (*handler)(void *), void *data)
  192. {
  193. }
  194. static const struct dss_mgr_ops mgr_ops = {
  195. .connect = omap_crtc_dss_connect,
  196. .disconnect = omap_crtc_dss_disconnect,
  197. .start_update = omap_crtc_dss_start_update,
  198. .enable = omap_crtc_dss_enable,
  199. .disable = omap_crtc_dss_disable,
  200. .set_timings = omap_crtc_dss_set_timings,
  201. .set_lcd_config = omap_crtc_dss_set_lcd_config,
  202. .register_framedone_handler = omap_crtc_dss_register_framedone,
  203. .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
  204. };
  205. /* -----------------------------------------------------------------------------
  206. * Setup, Flush and Page Flip
  207. */
  208. static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
  209. {
  210. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  211. struct drm_pending_vblank_event *event;
  212. struct drm_device *dev = crtc->dev;
  213. unsigned long flags;
  214. spin_lock_irqsave(&dev->event_lock, flags);
  215. event = omap_crtc->event;
  216. omap_crtc->event = NULL;
  217. if (event) {
  218. list_del(&event->base.link);
  219. /*
  220. * Queue the event for delivery if it's still linked to a file
  221. * handle, otherwise just destroy it.
  222. */
  223. if (event->base.file_priv)
  224. drm_crtc_send_vblank_event(crtc, event);
  225. else
  226. event->base.destroy(&event->base);
  227. wake_up(&omap_crtc->flip_wait);
  228. drm_crtc_vblank_put(crtc);
  229. }
  230. spin_unlock_irqrestore(&dev->event_lock, flags);
  231. }
  232. static bool omap_crtc_page_flip_pending(struct drm_crtc *crtc)
  233. {
  234. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  235. struct drm_device *dev = crtc->dev;
  236. unsigned long flags;
  237. bool pending;
  238. spin_lock_irqsave(&dev->event_lock, flags);
  239. pending = omap_crtc->event != NULL;
  240. spin_unlock_irqrestore(&dev->event_lock, flags);
  241. return pending;
  242. }
  243. static void omap_crtc_wait_page_flip(struct drm_crtc *crtc)
  244. {
  245. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  246. if (wait_event_timeout(omap_crtc->flip_wait,
  247. !omap_crtc_page_flip_pending(crtc),
  248. msecs_to_jiffies(50)))
  249. return;
  250. dev_warn(crtc->dev->dev, "page flip timeout!\n");
  251. omap_crtc_complete_page_flip(crtc);
  252. }
  253. static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  254. {
  255. struct omap_crtc *omap_crtc =
  256. container_of(irq, struct omap_crtc, error_irq);
  257. if (omap_crtc->ignore_digit_sync_lost) {
  258. irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
  259. if (!irqstatus)
  260. return;
  261. }
  262. DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
  263. }
  264. static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  265. {
  266. struct omap_crtc *omap_crtc =
  267. container_of(irq, struct omap_crtc, vblank_irq);
  268. struct drm_device *dev = omap_crtc->base.dev;
  269. if (dispc_mgr_go_busy(omap_crtc->channel))
  270. return;
  271. DBG("%s: apply done", omap_crtc->name);
  272. __omap_irq_unregister(dev, &omap_crtc->vblank_irq);
  273. /* wakeup userspace */
  274. omap_crtc_complete_page_flip(&omap_crtc->base);
  275. complete(&omap_crtc->completion);
  276. }
  277. static int omap_crtc_flush(struct drm_crtc *crtc)
  278. {
  279. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  280. DBG("%s: GO", omap_crtc->name);
  281. WARN_ON(omap_crtc->vblank_irq.registered);
  282. if (dispc_mgr_is_enabled(omap_crtc->channel)) {
  283. dispc_mgr_go(omap_crtc->channel);
  284. omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
  285. WARN_ON(!wait_for_completion_timeout(&omap_crtc->completion,
  286. msecs_to_jiffies(100)));
  287. reinit_completion(&omap_crtc->completion);
  288. }
  289. return 0;
  290. }
  291. static void omap_crtc_encoder_setup(struct drm_crtc *crtc, bool enable)
  292. {
  293. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  294. struct omap_drm_private *priv = crtc->dev->dev_private;
  295. struct drm_encoder *encoder = NULL;
  296. unsigned int i;
  297. DBG("%s: enable=%d", omap_crtc->name, enable);
  298. dispc_runtime_get();
  299. for (i = 0; i < priv->num_encoders; i++) {
  300. if (priv->encoders[i]->crtc == crtc) {
  301. encoder = priv->encoders[i];
  302. break;
  303. }
  304. }
  305. if (omap_crtc->current_encoder && encoder != omap_crtc->current_encoder)
  306. omap_encoder_set_enabled(omap_crtc->current_encoder, false);
  307. omap_crtc->current_encoder = encoder;
  308. if (encoder) {
  309. omap_encoder_set_enabled(encoder, false);
  310. if (enable) {
  311. omap_encoder_update(encoder, omap_crtc->mgr,
  312. &omap_crtc->timings);
  313. omap_encoder_set_enabled(encoder, true);
  314. }
  315. }
  316. dispc_runtime_put();
  317. }
  318. /* -----------------------------------------------------------------------------
  319. * CRTC Functions
  320. */
  321. static void omap_crtc_destroy(struct drm_crtc *crtc)
  322. {
  323. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  324. DBG("%s", omap_crtc->name);
  325. WARN_ON(omap_crtc->vblank_irq.registered);
  326. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  327. drm_crtc_cleanup(crtc);
  328. kfree(omap_crtc);
  329. }
  330. static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
  331. const struct drm_display_mode *mode,
  332. struct drm_display_mode *adjusted_mode)
  333. {
  334. return true;
  335. }
  336. static void omap_crtc_enable(struct drm_crtc *crtc)
  337. {
  338. struct omap_drm_private *priv = crtc->dev->dev_private;
  339. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  340. unsigned int i;
  341. DBG("%s", omap_crtc->name);
  342. dispc_runtime_get();
  343. /* Enable all planes associated with the CRTC. */
  344. for (i = 0; i < priv->num_planes; i++) {
  345. struct drm_plane *plane = priv->planes[i];
  346. if (plane->crtc == crtc)
  347. WARN_ON(omap_plane_setup(plane));
  348. }
  349. omap_crtc_encoder_setup(crtc, true);
  350. omap_crtc_flush(crtc);
  351. drm_crtc_vblank_on(crtc);
  352. dispc_runtime_put();
  353. }
  354. static void omap_crtc_disable(struct drm_crtc *crtc)
  355. {
  356. struct omap_drm_private *priv = crtc->dev->dev_private;
  357. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  358. unsigned int i;
  359. DBG("%s", omap_crtc->name);
  360. omap_crtc_wait_page_flip(crtc);
  361. dispc_runtime_get();
  362. drm_crtc_vblank_off(crtc);
  363. /* Disable all planes associated with the CRTC. */
  364. for (i = 0; i < priv->num_planes; i++) {
  365. struct drm_plane *plane = priv->planes[i];
  366. if (plane->crtc == crtc)
  367. WARN_ON(omap_plane_setup(plane));
  368. }
  369. omap_crtc_encoder_setup(crtc, false);
  370. omap_crtc_flush(crtc);
  371. dispc_runtime_put();
  372. }
  373. static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
  374. {
  375. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  376. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  377. DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
  378. omap_crtc->name, mode->base.id, mode->name,
  379. mode->vrefresh, mode->clock,
  380. mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
  381. mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
  382. mode->type, mode->flags);
  383. copy_timings_drm_to_omap(&omap_crtc->timings, mode);
  384. }
  385. static void omap_crtc_atomic_begin(struct drm_crtc *crtc)
  386. {
  387. struct drm_pending_vblank_event *event = crtc->state->event;
  388. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  389. struct drm_device *dev = crtc->dev;
  390. unsigned long flags;
  391. dispc_runtime_get();
  392. if (event) {
  393. WARN_ON(omap_crtc->event);
  394. WARN_ON(drm_crtc_vblank_get(crtc) != 0);
  395. spin_lock_irqsave(&dev->event_lock, flags);
  396. omap_crtc->event = event;
  397. spin_unlock_irqrestore(&dev->event_lock, flags);
  398. }
  399. }
  400. static void omap_crtc_atomic_flush(struct drm_crtc *crtc)
  401. {
  402. omap_crtc_flush(crtc);
  403. dispc_runtime_put();
  404. crtc->invert_dimensions = !!(crtc->primary->state->rotation &
  405. (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)));
  406. }
  407. static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
  408. struct drm_crtc_state *state,
  409. struct drm_property *property,
  410. uint64_t val)
  411. {
  412. struct drm_plane_state *plane_state;
  413. struct drm_plane *plane = crtc->primary;
  414. /*
  415. * Delegate property set to the primary plane. Get the plane state and
  416. * set the property directly.
  417. */
  418. plane_state = drm_atomic_get_plane_state(state->state, plane);
  419. if (!plane_state)
  420. return -EINVAL;
  421. return drm_atomic_plane_set_property(plane, plane_state, property, val);
  422. }
  423. static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
  424. const struct drm_crtc_state *state,
  425. struct drm_property *property,
  426. uint64_t *val)
  427. {
  428. /*
  429. * Delegate property get to the primary plane. The
  430. * drm_atomic_plane_get_property() function isn't exported, but can be
  431. * called through drm_object_property_get_value() as that will call
  432. * drm_atomic_get_property() for atomic drivers.
  433. */
  434. return drm_object_property_get_value(&crtc->primary->base, property,
  435. val);
  436. }
  437. static const struct drm_crtc_funcs omap_crtc_funcs = {
  438. .reset = drm_atomic_helper_crtc_reset,
  439. .set_config = drm_atomic_helper_set_config,
  440. .destroy = omap_crtc_destroy,
  441. .page_flip = drm_atomic_helper_page_flip,
  442. .set_property = drm_atomic_helper_crtc_set_property,
  443. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  444. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  445. .atomic_set_property = omap_crtc_atomic_set_property,
  446. .atomic_get_property = omap_crtc_atomic_get_property,
  447. };
  448. static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
  449. .mode_fixup = omap_crtc_mode_fixup,
  450. .mode_set_nofb = omap_crtc_mode_set_nofb,
  451. .disable = omap_crtc_disable,
  452. .enable = omap_crtc_enable,
  453. .atomic_begin = omap_crtc_atomic_begin,
  454. .atomic_flush = omap_crtc_atomic_flush,
  455. };
  456. /* -----------------------------------------------------------------------------
  457. * Init and Cleanup
  458. */
  459. static const char *channel_names[] = {
  460. [OMAP_DSS_CHANNEL_LCD] = "lcd",
  461. [OMAP_DSS_CHANNEL_DIGIT] = "tv",
  462. [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
  463. [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
  464. };
  465. void omap_crtc_pre_init(void)
  466. {
  467. dss_install_mgr_ops(&mgr_ops);
  468. }
  469. void omap_crtc_pre_uninit(void)
  470. {
  471. dss_uninstall_mgr_ops();
  472. }
  473. /* initialize crtc */
  474. struct drm_crtc *omap_crtc_init(struct drm_device *dev,
  475. struct drm_plane *plane, enum omap_channel channel, int id)
  476. {
  477. struct drm_crtc *crtc = NULL;
  478. struct omap_crtc *omap_crtc;
  479. int ret;
  480. DBG("%s", channel_names[channel]);
  481. omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
  482. if (!omap_crtc)
  483. return NULL;
  484. crtc = &omap_crtc->base;
  485. init_waitqueue_head(&omap_crtc->flip_wait);
  486. init_completion(&omap_crtc->completion);
  487. omap_crtc->channel = channel;
  488. omap_crtc->name = channel_names[channel];
  489. omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
  490. omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
  491. omap_crtc->error_irq.irqmask =
  492. dispc_mgr_get_sync_lost_irq(channel);
  493. omap_crtc->error_irq.irq = omap_crtc_error_irq;
  494. omap_irq_register(dev, &omap_crtc->error_irq);
  495. /* temporary: */
  496. omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
  497. ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
  498. &omap_crtc_funcs);
  499. if (ret < 0) {
  500. kfree(omap_crtc);
  501. return NULL;
  502. }
  503. drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
  504. omap_plane_install_properties(crtc->primary, &crtc->base);
  505. omap_crtcs[channel] = omap_crtc;
  506. return crtc;
  507. }