sdhci.c 33 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * Note that PIO transfer is rather crappy atm. The buffer full/empty
  12. * interrupts aren't reliable so we currently transfer the entire buffer
  13. * directly. Patches to solve the problem are welcome.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/protocol.h>
  21. #include <asm/scatterlist.h>
  22. #include "sdhci.h"
  23. #define DRIVER_NAME "sdhci"
  24. #define DRIVER_VERSION "0.11"
  25. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  26. #define DBG(f, x...) \
  27. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. /* handle any SD host controller */
  30. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  31. { /* end: all zeroes */ },
  32. };
  33. MODULE_DEVICE_TABLE(pci, pci_ids);
  34. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  35. static void sdhci_finish_data(struct sdhci_host *);
  36. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  37. static void sdhci_finish_command(struct sdhci_host *);
  38. static void sdhci_dumpregs(struct sdhci_host *host)
  39. {
  40. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  41. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  42. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  43. readw(host->ioaddr + SDHCI_HOST_VERSION));
  44. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  45. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  46. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  47. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  48. readl(host->ioaddr + SDHCI_ARGUMENT),
  49. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  50. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  51. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  52. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  53. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  54. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  55. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  56. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  57. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  58. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  59. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  60. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  61. readl(host->ioaddr + SDHCI_INT_STATUS));
  62. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  63. readl(host->ioaddr + SDHCI_INT_ENABLE),
  64. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  65. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  66. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  67. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  68. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  69. readl(host->ioaddr + SDHCI_CAPABILITIES),
  70. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  71. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  72. }
  73. /*****************************************************************************\
  74. * *
  75. * Low level functions *
  76. * *
  77. \*****************************************************************************/
  78. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  79. {
  80. unsigned long timeout;
  81. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  82. if (mask & SDHCI_RESET_ALL)
  83. host->clock = 0;
  84. /* Wait max 100 ms */
  85. timeout = 100;
  86. /* hw clears the bit when it's done */
  87. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  88. if (timeout == 0) {
  89. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  90. "Please report this to " BUGMAIL ".\n",
  91. mmc_hostname(host->mmc), (int)mask);
  92. sdhci_dumpregs(host);
  93. return;
  94. }
  95. timeout--;
  96. mdelay(1);
  97. }
  98. }
  99. static void sdhci_init(struct sdhci_host *host)
  100. {
  101. u32 intmask;
  102. sdhci_reset(host, SDHCI_RESET_ALL);
  103. intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  104. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  105. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  106. }
  107. static void sdhci_activate_led(struct sdhci_host *host)
  108. {
  109. u8 ctrl;
  110. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  111. ctrl |= SDHCI_CTRL_LED;
  112. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  113. }
  114. static void sdhci_deactivate_led(struct sdhci_host *host)
  115. {
  116. u8 ctrl;
  117. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  118. ctrl &= ~SDHCI_CTRL_LED;
  119. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  120. }
  121. /*****************************************************************************\
  122. * *
  123. * Core functions *
  124. * *
  125. \*****************************************************************************/
  126. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  127. {
  128. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  129. return host->mapped_sg + host->cur_sg->offset;
  130. }
  131. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  132. {
  133. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  134. }
  135. static inline int sdhci_next_sg(struct sdhci_host* host)
  136. {
  137. /*
  138. * Skip to next SG entry.
  139. */
  140. host->cur_sg++;
  141. host->num_sg--;
  142. /*
  143. * Any entries left?
  144. */
  145. if (host->num_sg > 0) {
  146. host->offset = 0;
  147. host->remain = host->cur_sg->length;
  148. }
  149. return host->num_sg;
  150. }
  151. static void sdhci_transfer_pio(struct sdhci_host *host)
  152. {
  153. char *buffer;
  154. u32 mask;
  155. int bytes, size;
  156. unsigned long max_jiffies;
  157. BUG_ON(!host->data);
  158. if (host->num_sg == 0)
  159. return;
  160. bytes = 0;
  161. if (host->data->flags & MMC_DATA_READ)
  162. mask = SDHCI_DATA_AVAILABLE;
  163. else
  164. mask = SDHCI_SPACE_AVAILABLE;
  165. buffer = sdhci_kmap_sg(host) + host->offset;
  166. /* Transfer shouldn't take more than 5 s */
  167. max_jiffies = jiffies + HZ * 5;
  168. while (host->size > 0) {
  169. if (time_after(jiffies, max_jiffies)) {
  170. printk(KERN_ERR "%s: PIO transfer stalled. "
  171. "Please report this to "
  172. BUGMAIL ".\n", mmc_hostname(host->mmc));
  173. sdhci_dumpregs(host);
  174. sdhci_kunmap_sg(host);
  175. host->data->error = MMC_ERR_FAILED;
  176. sdhci_finish_data(host);
  177. return;
  178. }
  179. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
  180. continue;
  181. size = min(host->size, host->remain);
  182. if (size >= 4) {
  183. if (host->data->flags & MMC_DATA_READ)
  184. *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
  185. else
  186. writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
  187. size = 4;
  188. } else if (size >= 2) {
  189. if (host->data->flags & MMC_DATA_READ)
  190. *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
  191. else
  192. writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
  193. size = 2;
  194. } else {
  195. if (host->data->flags & MMC_DATA_READ)
  196. *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
  197. else
  198. writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
  199. size = 1;
  200. }
  201. buffer += size;
  202. host->offset += size;
  203. host->remain -= size;
  204. bytes += size;
  205. host->size -= size;
  206. if (host->remain == 0) {
  207. sdhci_kunmap_sg(host);
  208. if (sdhci_next_sg(host) == 0) {
  209. DBG("PIO transfer: %d bytes\n", bytes);
  210. return;
  211. }
  212. buffer = sdhci_kmap_sg(host);
  213. }
  214. }
  215. sdhci_kunmap_sg(host);
  216. DBG("PIO transfer: %d bytes\n", bytes);
  217. }
  218. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  219. {
  220. u16 mode;
  221. u8 count;
  222. unsigned target_timeout, current_timeout;
  223. WARN_ON(host->data);
  224. if (data == NULL) {
  225. writew(0, host->ioaddr + SDHCI_TRANSFER_MODE);
  226. return;
  227. }
  228. DBG("blksz %04x blks %04x flags %08x\n",
  229. data->blksz, data->blocks, data->flags);
  230. DBG("tsac %d ms nsac %d clk\n",
  231. data->timeout_ns / 1000000, data->timeout_clks);
  232. /* timeout in us */
  233. target_timeout = data->timeout_ns / 1000 +
  234. data->timeout_clks / host->clock;
  235. /*
  236. * Figure out needed cycles.
  237. * We do this in steps in order to fit inside a 32 bit int.
  238. * The first step is the minimum timeout, which will have a
  239. * minimum resolution of 6 bits:
  240. * (1) 2^13*1000 > 2^22,
  241. * (2) host->timeout_clk < 2^16
  242. * =>
  243. * (1) / (2) > 2^6
  244. */
  245. count = 0;
  246. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  247. while (current_timeout < target_timeout) {
  248. count++;
  249. current_timeout <<= 1;
  250. if (count >= 0xF)
  251. break;
  252. }
  253. if (count >= 0xF) {
  254. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  255. mmc_hostname(host->mmc));
  256. count = 0xE;
  257. }
  258. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  259. mode = SDHCI_TRNS_BLK_CNT_EN;
  260. if (data->blocks > 1)
  261. mode |= SDHCI_TRNS_MULTI;
  262. if (data->flags & MMC_DATA_READ)
  263. mode |= SDHCI_TRNS_READ;
  264. if (host->flags & SDHCI_USE_DMA)
  265. mode |= SDHCI_TRNS_DMA;
  266. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  267. writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
  268. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  269. if (host->flags & SDHCI_USE_DMA) {
  270. int count;
  271. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  272. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  273. BUG_ON(count != 1);
  274. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  275. } else {
  276. host->size = data->blksz * data->blocks;
  277. host->cur_sg = data->sg;
  278. host->num_sg = data->sg_len;
  279. host->offset = 0;
  280. host->remain = host->cur_sg->length;
  281. }
  282. }
  283. static void sdhci_finish_data(struct sdhci_host *host)
  284. {
  285. struct mmc_data *data;
  286. u32 intmask;
  287. u16 blocks;
  288. BUG_ON(!host->data);
  289. data = host->data;
  290. host->data = NULL;
  291. if (host->flags & SDHCI_USE_DMA) {
  292. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  293. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  294. } else {
  295. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  296. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  297. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  298. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  299. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  300. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  301. }
  302. /*
  303. * Controller doesn't count down when in single block mode.
  304. */
  305. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  306. blocks = 0;
  307. else
  308. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  309. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  310. if ((data->error == MMC_ERR_NONE) && blocks) {
  311. printk(KERN_ERR "%s: Controller signalled completion even "
  312. "though there were blocks left. Please report this "
  313. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  314. data->error = MMC_ERR_FAILED;
  315. }
  316. if (host->size != 0) {
  317. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  318. "Please report this to " BUGMAIL ".\n",
  319. mmc_hostname(host->mmc), host->size);
  320. data->error = MMC_ERR_FAILED;
  321. }
  322. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  323. if (data->stop) {
  324. /*
  325. * The controller needs a reset of internal state machines
  326. * upon error conditions.
  327. */
  328. if (data->error != MMC_ERR_NONE) {
  329. sdhci_reset(host, SDHCI_RESET_CMD);
  330. sdhci_reset(host, SDHCI_RESET_DATA);
  331. }
  332. sdhci_send_command(host, data->stop);
  333. } else
  334. tasklet_schedule(&host->finish_tasklet);
  335. }
  336. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  337. {
  338. int flags;
  339. unsigned long timeout;
  340. WARN_ON(host->cmd);
  341. DBG("Sending cmd (%x)\n", cmd->opcode);
  342. /* Wait max 10 ms */
  343. timeout = 10;
  344. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  345. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  346. if (timeout == 0) {
  347. printk(KERN_ERR "%s: Controller never released "
  348. "inhibit bits. Please report this to "
  349. BUGMAIL ".\n", mmc_hostname(host->mmc));
  350. sdhci_dumpregs(host);
  351. cmd->error = MMC_ERR_FAILED;
  352. tasklet_schedule(&host->finish_tasklet);
  353. return;
  354. }
  355. timeout--;
  356. mdelay(1);
  357. }
  358. mod_timer(&host->timer, jiffies + 10 * HZ);
  359. host->cmd = cmd;
  360. sdhci_prepare_data(host, cmd->data);
  361. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  362. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  363. printk(KERN_ERR "%s: Unsupported response type! "
  364. "Please report this to " BUGMAIL ".\n",
  365. mmc_hostname(host->mmc));
  366. cmd->error = MMC_ERR_INVALID;
  367. tasklet_schedule(&host->finish_tasklet);
  368. return;
  369. }
  370. if (!(cmd->flags & MMC_RSP_PRESENT))
  371. flags = SDHCI_CMD_RESP_NONE;
  372. else if (cmd->flags & MMC_RSP_136)
  373. flags = SDHCI_CMD_RESP_LONG;
  374. else if (cmd->flags & MMC_RSP_BUSY)
  375. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  376. else
  377. flags = SDHCI_CMD_RESP_SHORT;
  378. if (cmd->flags & MMC_RSP_CRC)
  379. flags |= SDHCI_CMD_CRC;
  380. if (cmd->flags & MMC_RSP_OPCODE)
  381. flags |= SDHCI_CMD_INDEX;
  382. if (cmd->data)
  383. flags |= SDHCI_CMD_DATA;
  384. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  385. host->ioaddr + SDHCI_COMMAND);
  386. }
  387. static void sdhci_finish_command(struct sdhci_host *host)
  388. {
  389. int i;
  390. BUG_ON(host->cmd == NULL);
  391. if (host->cmd->flags & MMC_RSP_PRESENT) {
  392. if (host->cmd->flags & MMC_RSP_136) {
  393. /* CRC is stripped so we need to do some shifting. */
  394. for (i = 0;i < 4;i++) {
  395. host->cmd->resp[i] = readl(host->ioaddr +
  396. SDHCI_RESPONSE + (3-i)*4) << 8;
  397. if (i != 3)
  398. host->cmd->resp[i] |=
  399. readb(host->ioaddr +
  400. SDHCI_RESPONSE + (3-i)*4-1);
  401. }
  402. } else {
  403. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  404. }
  405. }
  406. host->cmd->error = MMC_ERR_NONE;
  407. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  408. if (host->cmd->data) {
  409. u32 intmask;
  410. host->data = host->cmd->data;
  411. if (!(host->flags & SDHCI_USE_DMA)) {
  412. /*
  413. * Don't enable the interrupts until now to make sure we
  414. * get stable handling of the FIFO.
  415. */
  416. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  417. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  418. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  419. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  420. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  421. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  422. /*
  423. * The buffer interrupts are to unreliable so we
  424. * start the transfer immediatly.
  425. */
  426. sdhci_transfer_pio(host);
  427. }
  428. } else
  429. tasklet_schedule(&host->finish_tasklet);
  430. host->cmd = NULL;
  431. }
  432. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  433. {
  434. int div;
  435. u16 clk;
  436. unsigned long timeout;
  437. if (clock == host->clock)
  438. return;
  439. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  440. if (clock == 0)
  441. goto out;
  442. for (div = 1;div < 256;div *= 2) {
  443. if ((host->max_clk / div) <= clock)
  444. break;
  445. }
  446. div >>= 1;
  447. clk = div << SDHCI_DIVIDER_SHIFT;
  448. clk |= SDHCI_CLOCK_INT_EN;
  449. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  450. /* Wait max 10 ms */
  451. timeout = 10;
  452. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  453. & SDHCI_CLOCK_INT_STABLE)) {
  454. if (timeout == 0) {
  455. printk(KERN_ERR "%s: Internal clock never stabilised. "
  456. "Please report this to " BUGMAIL ".\n",
  457. mmc_hostname(host->mmc));
  458. sdhci_dumpregs(host);
  459. return;
  460. }
  461. timeout--;
  462. mdelay(1);
  463. }
  464. clk |= SDHCI_CLOCK_CARD_EN;
  465. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  466. out:
  467. host->clock = clock;
  468. }
  469. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  470. {
  471. u8 pwr;
  472. if (host->power == power)
  473. return;
  474. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  475. if (power == (unsigned short)-1)
  476. goto out;
  477. pwr = SDHCI_POWER_ON;
  478. switch (power) {
  479. case MMC_VDD_170:
  480. case MMC_VDD_180:
  481. case MMC_VDD_190:
  482. pwr |= SDHCI_POWER_180;
  483. break;
  484. case MMC_VDD_290:
  485. case MMC_VDD_300:
  486. case MMC_VDD_310:
  487. pwr |= SDHCI_POWER_300;
  488. break;
  489. case MMC_VDD_320:
  490. case MMC_VDD_330:
  491. case MMC_VDD_340:
  492. pwr |= SDHCI_POWER_330;
  493. break;
  494. default:
  495. BUG();
  496. }
  497. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  498. out:
  499. host->power = power;
  500. }
  501. /*****************************************************************************\
  502. * *
  503. * MMC callbacks *
  504. * *
  505. \*****************************************************************************/
  506. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  507. {
  508. struct sdhci_host *host;
  509. unsigned long flags;
  510. host = mmc_priv(mmc);
  511. spin_lock_irqsave(&host->lock, flags);
  512. WARN_ON(host->mrq != NULL);
  513. sdhci_activate_led(host);
  514. host->mrq = mrq;
  515. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  516. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  517. tasklet_schedule(&host->finish_tasklet);
  518. } else
  519. sdhci_send_command(host, mrq->cmd);
  520. spin_unlock_irqrestore(&host->lock, flags);
  521. }
  522. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  523. {
  524. struct sdhci_host *host;
  525. unsigned long flags;
  526. u8 ctrl;
  527. host = mmc_priv(mmc);
  528. spin_lock_irqsave(&host->lock, flags);
  529. /*
  530. * Reset the chip on each power off.
  531. * Should clear out any weird states.
  532. */
  533. if (ios->power_mode == MMC_POWER_OFF) {
  534. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  535. sdhci_init(host);
  536. }
  537. sdhci_set_clock(host, ios->clock);
  538. if (ios->power_mode == MMC_POWER_OFF)
  539. sdhci_set_power(host, -1);
  540. else
  541. sdhci_set_power(host, ios->vdd);
  542. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  543. if (ios->bus_width == MMC_BUS_WIDTH_4)
  544. ctrl |= SDHCI_CTRL_4BITBUS;
  545. else
  546. ctrl &= ~SDHCI_CTRL_4BITBUS;
  547. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  548. spin_unlock_irqrestore(&host->lock, flags);
  549. }
  550. static int sdhci_get_ro(struct mmc_host *mmc)
  551. {
  552. struct sdhci_host *host;
  553. unsigned long flags;
  554. int present;
  555. host = mmc_priv(mmc);
  556. spin_lock_irqsave(&host->lock, flags);
  557. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  558. spin_unlock_irqrestore(&host->lock, flags);
  559. return !(present & SDHCI_WRITE_PROTECT);
  560. }
  561. static struct mmc_host_ops sdhci_ops = {
  562. .request = sdhci_request,
  563. .set_ios = sdhci_set_ios,
  564. .get_ro = sdhci_get_ro,
  565. };
  566. /*****************************************************************************\
  567. * *
  568. * Tasklets *
  569. * *
  570. \*****************************************************************************/
  571. static void sdhci_tasklet_card(unsigned long param)
  572. {
  573. struct sdhci_host *host;
  574. unsigned long flags;
  575. host = (struct sdhci_host*)param;
  576. spin_lock_irqsave(&host->lock, flags);
  577. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  578. if (host->mrq) {
  579. printk(KERN_ERR "%s: Card removed during transfer!\n",
  580. mmc_hostname(host->mmc));
  581. printk(KERN_ERR "%s: Resetting controller.\n",
  582. mmc_hostname(host->mmc));
  583. sdhci_reset(host, SDHCI_RESET_CMD);
  584. sdhci_reset(host, SDHCI_RESET_DATA);
  585. host->mrq->cmd->error = MMC_ERR_FAILED;
  586. tasklet_schedule(&host->finish_tasklet);
  587. }
  588. }
  589. spin_unlock_irqrestore(&host->lock, flags);
  590. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  591. }
  592. static void sdhci_tasklet_finish(unsigned long param)
  593. {
  594. struct sdhci_host *host;
  595. unsigned long flags;
  596. struct mmc_request *mrq;
  597. host = (struct sdhci_host*)param;
  598. spin_lock_irqsave(&host->lock, flags);
  599. del_timer(&host->timer);
  600. mrq = host->mrq;
  601. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  602. /*
  603. * The controller needs a reset of internal state machines
  604. * upon error conditions.
  605. */
  606. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  607. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  608. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  609. sdhci_reset(host, SDHCI_RESET_CMD);
  610. sdhci_reset(host, SDHCI_RESET_DATA);
  611. }
  612. host->mrq = NULL;
  613. host->cmd = NULL;
  614. host->data = NULL;
  615. sdhci_deactivate_led(host);
  616. spin_unlock_irqrestore(&host->lock, flags);
  617. mmc_request_done(host->mmc, mrq);
  618. }
  619. static void sdhci_timeout_timer(unsigned long data)
  620. {
  621. struct sdhci_host *host;
  622. unsigned long flags;
  623. host = (struct sdhci_host*)data;
  624. spin_lock_irqsave(&host->lock, flags);
  625. if (host->mrq) {
  626. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  627. "Please report this to " BUGMAIL ".\n",
  628. mmc_hostname(host->mmc));
  629. sdhci_dumpregs(host);
  630. if (host->data) {
  631. host->data->error = MMC_ERR_TIMEOUT;
  632. sdhci_finish_data(host);
  633. } else {
  634. if (host->cmd)
  635. host->cmd->error = MMC_ERR_TIMEOUT;
  636. else
  637. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  638. tasklet_schedule(&host->finish_tasklet);
  639. }
  640. }
  641. spin_unlock_irqrestore(&host->lock, flags);
  642. }
  643. /*****************************************************************************\
  644. * *
  645. * Interrupt handling *
  646. * *
  647. \*****************************************************************************/
  648. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  649. {
  650. BUG_ON(intmask == 0);
  651. if (!host->cmd) {
  652. printk(KERN_ERR "%s: Got command interrupt even though no "
  653. "command operation was in progress.\n",
  654. mmc_hostname(host->mmc));
  655. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  656. mmc_hostname(host->mmc));
  657. sdhci_dumpregs(host);
  658. return;
  659. }
  660. if (intmask & SDHCI_INT_RESPONSE)
  661. sdhci_finish_command(host);
  662. else {
  663. if (intmask & SDHCI_INT_TIMEOUT)
  664. host->cmd->error = MMC_ERR_TIMEOUT;
  665. else if (intmask & SDHCI_INT_CRC)
  666. host->cmd->error = MMC_ERR_BADCRC;
  667. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  668. host->cmd->error = MMC_ERR_FAILED;
  669. else
  670. host->cmd->error = MMC_ERR_INVALID;
  671. tasklet_schedule(&host->finish_tasklet);
  672. }
  673. }
  674. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  675. {
  676. BUG_ON(intmask == 0);
  677. if (!host->data) {
  678. /*
  679. * A data end interrupt is sent together with the response
  680. * for the stop command.
  681. */
  682. if (intmask & SDHCI_INT_DATA_END)
  683. return;
  684. printk(KERN_ERR "%s: Got data interrupt even though no "
  685. "data operation was in progress.\n",
  686. mmc_hostname(host->mmc));
  687. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  688. mmc_hostname(host->mmc));
  689. sdhci_dumpregs(host);
  690. return;
  691. }
  692. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  693. host->data->error = MMC_ERR_TIMEOUT;
  694. else if (intmask & SDHCI_INT_DATA_CRC)
  695. host->data->error = MMC_ERR_BADCRC;
  696. else if (intmask & SDHCI_INT_DATA_END_BIT)
  697. host->data->error = MMC_ERR_FAILED;
  698. if (host->data->error != MMC_ERR_NONE)
  699. sdhci_finish_data(host);
  700. else {
  701. if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
  702. sdhci_transfer_pio(host);
  703. if (intmask & SDHCI_INT_DATA_END)
  704. sdhci_finish_data(host);
  705. }
  706. }
  707. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  708. {
  709. irqreturn_t result;
  710. struct sdhci_host* host = dev_id;
  711. u32 intmask;
  712. spin_lock(&host->lock);
  713. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  714. if (!intmask) {
  715. result = IRQ_NONE;
  716. goto out;
  717. }
  718. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  719. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  720. tasklet_schedule(&host->card_tasklet);
  721. if (intmask & SDHCI_INT_CMD_MASK) {
  722. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  723. writel(intmask & SDHCI_INT_CMD_MASK,
  724. host->ioaddr + SDHCI_INT_STATUS);
  725. }
  726. if (intmask & SDHCI_INT_DATA_MASK) {
  727. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  728. writel(intmask & SDHCI_INT_DATA_MASK,
  729. host->ioaddr + SDHCI_INT_STATUS);
  730. }
  731. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  732. if (intmask & SDHCI_INT_CARD_INT) {
  733. printk(KERN_ERR "%s: Unexpected card interrupt. Please "
  734. "report this to " BUGMAIL ".\n",
  735. mmc_hostname(host->mmc));
  736. sdhci_dumpregs(host);
  737. }
  738. if (intmask & SDHCI_INT_BUS_POWER) {
  739. printk(KERN_ERR "%s: Unexpected bus power interrupt. Please "
  740. "report this to " BUGMAIL ".\n",
  741. mmc_hostname(host->mmc));
  742. sdhci_dumpregs(host);
  743. }
  744. if (intmask & SDHCI_INT_ACMD12ERR) {
  745. printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please "
  746. "report this to " BUGMAIL ".\n",
  747. mmc_hostname(host->mmc));
  748. sdhci_dumpregs(host);
  749. writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
  750. }
  751. if (intmask)
  752. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  753. result = IRQ_HANDLED;
  754. out:
  755. spin_unlock(&host->lock);
  756. return result;
  757. }
  758. /*****************************************************************************\
  759. * *
  760. * Suspend/resume *
  761. * *
  762. \*****************************************************************************/
  763. #ifdef CONFIG_PM
  764. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  765. {
  766. struct sdhci_chip *chip;
  767. int i, ret;
  768. chip = pci_get_drvdata(pdev);
  769. if (!chip)
  770. return 0;
  771. DBG("Suspending...\n");
  772. for (i = 0;i < chip->num_slots;i++) {
  773. if (!chip->hosts[i])
  774. continue;
  775. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  776. if (ret) {
  777. for (i--;i >= 0;i--)
  778. mmc_resume_host(chip->hosts[i]->mmc);
  779. return ret;
  780. }
  781. }
  782. pci_save_state(pdev);
  783. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  784. pci_disable_device(pdev);
  785. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  786. return 0;
  787. }
  788. static int sdhci_resume (struct pci_dev *pdev)
  789. {
  790. struct sdhci_chip *chip;
  791. int i, ret;
  792. chip = pci_get_drvdata(pdev);
  793. if (!chip)
  794. return 0;
  795. DBG("Resuming...\n");
  796. pci_set_power_state(pdev, PCI_D0);
  797. pci_restore_state(pdev);
  798. pci_enable_device(pdev);
  799. for (i = 0;i < chip->num_slots;i++) {
  800. if (!chip->hosts[i])
  801. continue;
  802. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  803. pci_set_master(pdev);
  804. sdhci_init(chip->hosts[i]);
  805. ret = mmc_resume_host(chip->hosts[i]->mmc);
  806. if (ret)
  807. return ret;
  808. }
  809. return 0;
  810. }
  811. #else /* CONFIG_PM */
  812. #define sdhci_suspend NULL
  813. #define sdhci_resume NULL
  814. #endif /* CONFIG_PM */
  815. /*****************************************************************************\
  816. * *
  817. * Device probing/removal *
  818. * *
  819. \*****************************************************************************/
  820. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  821. {
  822. int ret;
  823. struct sdhci_chip *chip;
  824. struct mmc_host *mmc;
  825. struct sdhci_host *host;
  826. u8 first_bar;
  827. unsigned int caps;
  828. chip = pci_get_drvdata(pdev);
  829. BUG_ON(!chip);
  830. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  831. if (ret)
  832. return ret;
  833. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  834. if (first_bar > 5) {
  835. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  836. return -ENODEV;
  837. }
  838. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  839. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  840. return -ENODEV;
  841. }
  842. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  843. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  844. return -ENODEV;
  845. }
  846. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  847. if (!mmc)
  848. return -ENOMEM;
  849. host = mmc_priv(mmc);
  850. host->mmc = mmc;
  851. host->bar = first_bar + slot;
  852. host->addr = pci_resource_start(pdev, host->bar);
  853. host->irq = pdev->irq;
  854. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  855. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  856. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  857. if (ret)
  858. goto free;
  859. host->ioaddr = ioremap_nocache(host->addr,
  860. pci_resource_len(pdev, host->bar));
  861. if (!host->ioaddr) {
  862. ret = -ENOMEM;
  863. goto release;
  864. }
  865. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  866. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  867. host->flags |= SDHCI_USE_DMA;
  868. if (host->flags & SDHCI_USE_DMA) {
  869. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  870. printk(KERN_WARNING "%s: No suitable DMA available. "
  871. "Falling back to PIO.\n", host->slot_descr);
  872. host->flags &= ~SDHCI_USE_DMA;
  873. }
  874. }
  875. if (host->flags & SDHCI_USE_DMA)
  876. pci_set_master(pdev);
  877. else /* XXX: Hack to get MMC layer to avoid highmem */
  878. pdev->dma_mask = 0;
  879. host->max_clk =
  880. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  881. if (host->max_clk == 0) {
  882. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  883. "frequency.\n", host->slot_descr);
  884. ret = -ENODEV;
  885. goto unmap;
  886. }
  887. host->max_clk *= 1000000;
  888. host->timeout_clk =
  889. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  890. if (host->timeout_clk == 0) {
  891. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  892. "frequency.\n", host->slot_descr);
  893. ret = -ENODEV;
  894. goto unmap;
  895. }
  896. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  897. host->timeout_clk *= 1000;
  898. /*
  899. * Set host parameters.
  900. */
  901. mmc->ops = &sdhci_ops;
  902. mmc->f_min = host->max_clk / 256;
  903. mmc->f_max = host->max_clk;
  904. mmc->caps = MMC_CAP_4_BIT_DATA;
  905. mmc->ocr_avail = 0;
  906. if (caps & SDHCI_CAN_VDD_330)
  907. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  908. else if (caps & SDHCI_CAN_VDD_300)
  909. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  910. else if (caps & SDHCI_CAN_VDD_180)
  911. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  912. if (mmc->ocr_avail == 0) {
  913. printk(KERN_ERR "%s: Hardware doesn't report any "
  914. "support voltages.\n", host->slot_descr);
  915. ret = -ENODEV;
  916. goto unmap;
  917. }
  918. spin_lock_init(&host->lock);
  919. /*
  920. * Maximum number of segments. Hardware cannot do scatter lists.
  921. */
  922. if (host->flags & SDHCI_USE_DMA)
  923. mmc->max_hw_segs = 1;
  924. else
  925. mmc->max_hw_segs = 16;
  926. mmc->max_phys_segs = 16;
  927. /*
  928. * Maximum number of sectors in one transfer. Limited by sector
  929. * count register.
  930. */
  931. mmc->max_sectors = 0x3FFF;
  932. /*
  933. * Maximum segment size. Could be one segment with the maximum number
  934. * of sectors.
  935. */
  936. mmc->max_seg_size = mmc->max_sectors * 512;
  937. /*
  938. * Init tasklets.
  939. */
  940. tasklet_init(&host->card_tasklet,
  941. sdhci_tasklet_card, (unsigned long)host);
  942. tasklet_init(&host->finish_tasklet,
  943. sdhci_tasklet_finish, (unsigned long)host);
  944. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  945. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  946. host->slot_descr, host);
  947. if (ret)
  948. goto untasklet;
  949. sdhci_init(host);
  950. #ifdef CONFIG_MMC_DEBUG
  951. sdhci_dumpregs(host);
  952. #endif
  953. host->chip = chip;
  954. chip->hosts[slot] = host;
  955. mmc_add_host(mmc);
  956. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  957. host->addr, host->irq,
  958. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  959. return 0;
  960. untasklet:
  961. tasklet_kill(&host->card_tasklet);
  962. tasklet_kill(&host->finish_tasklet);
  963. unmap:
  964. iounmap(host->ioaddr);
  965. release:
  966. pci_release_region(pdev, host->bar);
  967. free:
  968. mmc_free_host(mmc);
  969. return ret;
  970. }
  971. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  972. {
  973. struct sdhci_chip *chip;
  974. struct mmc_host *mmc;
  975. struct sdhci_host *host;
  976. chip = pci_get_drvdata(pdev);
  977. host = chip->hosts[slot];
  978. mmc = host->mmc;
  979. chip->hosts[slot] = NULL;
  980. mmc_remove_host(mmc);
  981. sdhci_reset(host, SDHCI_RESET_ALL);
  982. free_irq(host->irq, host);
  983. del_timer_sync(&host->timer);
  984. tasklet_kill(&host->card_tasklet);
  985. tasklet_kill(&host->finish_tasklet);
  986. iounmap(host->ioaddr);
  987. pci_release_region(pdev, host->bar);
  988. mmc_free_host(mmc);
  989. }
  990. static int __devinit sdhci_probe(struct pci_dev *pdev,
  991. const struct pci_device_id *ent)
  992. {
  993. int ret, i;
  994. u8 slots, rev;
  995. struct sdhci_chip *chip;
  996. BUG_ON(pdev == NULL);
  997. BUG_ON(ent == NULL);
  998. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  999. printk(KERN_INFO DRIVER_NAME
  1000. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1001. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1002. (int)rev);
  1003. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1004. if (ret)
  1005. return ret;
  1006. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1007. DBG("found %d slot(s)\n", slots);
  1008. if (slots == 0)
  1009. return -ENODEV;
  1010. ret = pci_enable_device(pdev);
  1011. if (ret)
  1012. return ret;
  1013. chip = kzalloc(sizeof(struct sdhci_chip) +
  1014. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1015. if (!chip) {
  1016. ret = -ENOMEM;
  1017. goto err;
  1018. }
  1019. chip->pdev = pdev;
  1020. chip->num_slots = slots;
  1021. pci_set_drvdata(pdev, chip);
  1022. for (i = 0;i < slots;i++) {
  1023. ret = sdhci_probe_slot(pdev, i);
  1024. if (ret) {
  1025. for (i--;i >= 0;i--)
  1026. sdhci_remove_slot(pdev, i);
  1027. goto free;
  1028. }
  1029. }
  1030. return 0;
  1031. free:
  1032. pci_set_drvdata(pdev, NULL);
  1033. kfree(chip);
  1034. err:
  1035. pci_disable_device(pdev);
  1036. return ret;
  1037. }
  1038. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1039. {
  1040. int i;
  1041. struct sdhci_chip *chip;
  1042. chip = pci_get_drvdata(pdev);
  1043. if (chip) {
  1044. for (i = 0;i < chip->num_slots;i++)
  1045. sdhci_remove_slot(pdev, i);
  1046. pci_set_drvdata(pdev, NULL);
  1047. kfree(chip);
  1048. }
  1049. pci_disable_device(pdev);
  1050. }
  1051. static struct pci_driver sdhci_driver = {
  1052. .name = DRIVER_NAME,
  1053. .id_table = pci_ids,
  1054. .probe = sdhci_probe,
  1055. .remove = __devexit_p(sdhci_remove),
  1056. .suspend = sdhci_suspend,
  1057. .resume = sdhci_resume,
  1058. };
  1059. /*****************************************************************************\
  1060. * *
  1061. * Driver init/exit *
  1062. * *
  1063. \*****************************************************************************/
  1064. static int __init sdhci_drv_init(void)
  1065. {
  1066. printk(KERN_INFO DRIVER_NAME
  1067. ": Secure Digital Host Controller Interface driver, "
  1068. DRIVER_VERSION "\n");
  1069. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1070. return pci_register_driver(&sdhci_driver);
  1071. }
  1072. static void __exit sdhci_drv_exit(void)
  1073. {
  1074. DBG("Exiting\n");
  1075. pci_unregister_driver(&sdhci_driver);
  1076. }
  1077. module_init(sdhci_drv_init);
  1078. module_exit(sdhci_drv_exit);
  1079. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1080. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1081. MODULE_VERSION(DRIVER_VERSION);
  1082. MODULE_LICENSE("GPL");