lmc_main.c 61 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114
  1. /*
  2. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  3. * All rights reserved. www.lanmedia.com
  4. * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
  5. *
  6. * This code is written by:
  7. * Andrew Stanley-Jones (asj@cban.com)
  8. * Rob Braun (bbraun@vix.com),
  9. * Michael Graff (explorer@vix.com) and
  10. * Matt Thomas (matt@3am-software.com).
  11. *
  12. * With Help By:
  13. * David Boggs
  14. * Ron Crane
  15. * Alan Cox
  16. *
  17. * This software may be used and distributed according to the terms
  18. * of the GNU General Public License version 2, incorporated herein by reference.
  19. *
  20. * Driver for the LanMedia LMC5200, LMC5245, LMC1000, LMC1200 cards.
  21. *
  22. * To control link specific options lmcctl is required.
  23. * It can be obtained from ftp.lanmedia.com.
  24. *
  25. * Linux driver notes:
  26. * Linux uses the device struct lmc_private to pass private information
  27. * around.
  28. *
  29. * The initialization portion of this driver (the lmc_reset() and the
  30. * lmc_dec_reset() functions, as well as the led controls and the
  31. * lmc_initcsrs() functions.
  32. *
  33. * The watchdog function runs every second and checks to see if
  34. * we still have link, and that the timing source is what we expected
  35. * it to be. If link is lost, the interface is marked down, and
  36. * we no longer can transmit.
  37. *
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/ptrace.h>
  44. #include <linux/errno.h>
  45. #include <linux/ioport.h>
  46. #include <linux/slab.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/delay.h>
  50. #include <linux/hdlc.h>
  51. #include <linux/in.h>
  52. #include <linux/if_arp.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/etherdevice.h>
  55. #include <linux/skbuff.h>
  56. #include <linux/inet.h>
  57. #include <linux/bitops.h>
  58. #include <asm/processor.h> /* Processor type for cache alignment. */
  59. #include <asm/io.h>
  60. #include <asm/dma.h>
  61. #include <linux/uaccess.h>
  62. //#include <asm/spinlock.h>
  63. #define DRIVER_MAJOR_VERSION 1
  64. #define DRIVER_MINOR_VERSION 34
  65. #define DRIVER_SUB_VERSION 0
  66. #define DRIVER_VERSION ((DRIVER_MAJOR_VERSION << 8) + DRIVER_MINOR_VERSION)
  67. #include "lmc.h"
  68. #include "lmc_var.h"
  69. #include "lmc_ioctl.h"
  70. #include "lmc_debug.h"
  71. #include "lmc_proto.h"
  72. static int LMC_PKT_BUF_SZ = 1542;
  73. static const struct pci_device_id lmc_pci_tbl[] = {
  74. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  75. PCI_VENDOR_ID_LMC, PCI_ANY_ID },
  76. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  77. PCI_ANY_ID, PCI_VENDOR_ID_LMC },
  78. { 0 }
  79. };
  80. MODULE_DEVICE_TABLE(pci, lmc_pci_tbl);
  81. MODULE_LICENSE("GPL v2");
  82. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  83. struct net_device *dev);
  84. static int lmc_rx (struct net_device *dev);
  85. static int lmc_open(struct net_device *dev);
  86. static int lmc_close(struct net_device *dev);
  87. static struct net_device_stats *lmc_get_stats(struct net_device *dev);
  88. static irqreturn_t lmc_interrupt(int irq, void *dev_instance);
  89. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
  90. static void lmc_softreset(lmc_softc_t * const);
  91. static void lmc_running_reset(struct net_device *dev);
  92. static int lmc_ifdown(struct net_device * const);
  93. static void lmc_watchdog(unsigned long data);
  94. static void lmc_reset(lmc_softc_t * const sc);
  95. static void lmc_dec_reset(lmc_softc_t * const sc);
  96. static void lmc_driver_timeout(struct net_device *dev);
  97. /*
  98. * linux reserves 16 device specific IOCTLs. We call them
  99. * LMCIOC* to control various bits of our world.
  100. */
  101. int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/
  102. {
  103. lmc_softc_t *sc = dev_to_sc(dev);
  104. lmc_ctl_t ctl;
  105. int ret = -EOPNOTSUPP;
  106. u16 regVal;
  107. unsigned long flags;
  108. lmc_trace(dev, "lmc_ioctl in");
  109. /*
  110. * Most functions mess with the structure
  111. * Disable interrupts while we do the polling
  112. */
  113. switch (cmd) {
  114. /*
  115. * Return current driver state. Since we keep this up
  116. * To date internally, just copy this out to the user.
  117. */
  118. case LMCIOCGINFO: /*fold01*/
  119. if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
  120. ret = -EFAULT;
  121. else
  122. ret = 0;
  123. break;
  124. case LMCIOCSINFO: /*fold01*/
  125. if (!capable(CAP_NET_ADMIN)) {
  126. ret = -EPERM;
  127. break;
  128. }
  129. if(dev->flags & IFF_UP){
  130. ret = -EBUSY;
  131. break;
  132. }
  133. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  134. ret = -EFAULT;
  135. break;
  136. }
  137. spin_lock_irqsave(&sc->lmc_lock, flags);
  138. sc->lmc_media->set_status (sc, &ctl);
  139. if(ctl.crc_length != sc->ictl.crc_length) {
  140. sc->lmc_media->set_crc_length(sc, ctl.crc_length);
  141. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
  142. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  143. else
  144. sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
  145. }
  146. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  147. ret = 0;
  148. break;
  149. case LMCIOCIFTYPE: /*fold01*/
  150. {
  151. u16 old_type = sc->if_type;
  152. u16 new_type;
  153. if (!capable(CAP_NET_ADMIN)) {
  154. ret = -EPERM;
  155. break;
  156. }
  157. if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
  158. ret = -EFAULT;
  159. break;
  160. }
  161. if (new_type == old_type)
  162. {
  163. ret = 0 ;
  164. break; /* no change */
  165. }
  166. spin_lock_irqsave(&sc->lmc_lock, flags);
  167. lmc_proto_close(sc);
  168. sc->if_type = new_type;
  169. lmc_proto_attach(sc);
  170. ret = lmc_proto_open(sc);
  171. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  172. break;
  173. }
  174. case LMCIOCGETXINFO: /*fold01*/
  175. spin_lock_irqsave(&sc->lmc_lock, flags);
  176. sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
  177. sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
  178. sc->lmc_xinfo.PciSlotNumber = 0;
  179. sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
  180. sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
  181. sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
  182. sc->lmc_xinfo.XilinxRevisionNumber =
  183. lmc_mii_readreg (sc, 0, 3) & 0xf;
  184. sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
  185. sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
  186. sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
  187. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  188. sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
  189. if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
  190. sizeof(struct lmc_xinfo)))
  191. ret = -EFAULT;
  192. else
  193. ret = 0;
  194. break;
  195. case LMCIOCGETLMCSTATS:
  196. spin_lock_irqsave(&sc->lmc_lock, flags);
  197. if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
  198. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
  199. sc->extra_stats.framingBitErrorCount +=
  200. lmc_mii_readreg(sc, 0, 18) & 0xff;
  201. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
  202. sc->extra_stats.framingBitErrorCount +=
  203. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  204. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
  205. sc->extra_stats.lineCodeViolationCount +=
  206. lmc_mii_readreg(sc, 0, 18) & 0xff;
  207. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
  208. sc->extra_stats.lineCodeViolationCount +=
  209. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  210. lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
  211. regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
  212. sc->extra_stats.lossOfFrameCount +=
  213. (regVal & T1FRAMER_LOF_MASK) >> 4;
  214. sc->extra_stats.changeOfFrameAlignmentCount +=
  215. (regVal & T1FRAMER_COFA_MASK) >> 2;
  216. sc->extra_stats.severelyErroredFrameCount +=
  217. regVal & T1FRAMER_SEF_MASK;
  218. }
  219. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  220. if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
  221. sizeof(sc->lmc_device->stats)) ||
  222. copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
  223. &sc->extra_stats, sizeof(sc->extra_stats)))
  224. ret = -EFAULT;
  225. else
  226. ret = 0;
  227. break;
  228. case LMCIOCCLEARLMCSTATS:
  229. if (!capable(CAP_NET_ADMIN)) {
  230. ret = -EPERM;
  231. break;
  232. }
  233. spin_lock_irqsave(&sc->lmc_lock, flags);
  234. memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
  235. memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
  236. sc->extra_stats.check = STATCHECK;
  237. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  238. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  239. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  240. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  241. ret = 0;
  242. break;
  243. case LMCIOCSETCIRCUIT: /*fold01*/
  244. if (!capable(CAP_NET_ADMIN)){
  245. ret = -EPERM;
  246. break;
  247. }
  248. if(dev->flags & IFF_UP){
  249. ret = -EBUSY;
  250. break;
  251. }
  252. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  253. ret = -EFAULT;
  254. break;
  255. }
  256. spin_lock_irqsave(&sc->lmc_lock, flags);
  257. sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
  258. sc->ictl.circuit_type = ctl.circuit_type;
  259. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  260. ret = 0;
  261. break;
  262. case LMCIOCRESET: /*fold01*/
  263. if (!capable(CAP_NET_ADMIN)){
  264. ret = -EPERM;
  265. break;
  266. }
  267. spin_lock_irqsave(&sc->lmc_lock, flags);
  268. /* Reset driver and bring back to current state */
  269. printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  270. lmc_running_reset (dev);
  271. printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  272. LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  273. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  274. ret = 0;
  275. break;
  276. #ifdef DEBUG
  277. case LMCIOCDUMPEVENTLOG:
  278. if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
  279. ret = -EFAULT;
  280. break;
  281. }
  282. if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
  283. sizeof(lmcEventLogBuf)))
  284. ret = -EFAULT;
  285. else
  286. ret = 0;
  287. break;
  288. #endif /* end ifdef _DBG_EVENTLOG */
  289. case LMCIOCT1CONTROL: /*fold01*/
  290. if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
  291. ret = -EOPNOTSUPP;
  292. break;
  293. }
  294. break;
  295. case LMCIOCXILINX: /*fold01*/
  296. {
  297. struct lmc_xilinx_control xc; /*fold02*/
  298. if (!capable(CAP_NET_ADMIN)){
  299. ret = -EPERM;
  300. break;
  301. }
  302. /*
  303. * Stop the xwitter whlie we restart the hardware
  304. */
  305. netif_stop_queue(dev);
  306. if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
  307. ret = -EFAULT;
  308. break;
  309. }
  310. switch(xc.command){
  311. case lmc_xilinx_reset: /*fold02*/
  312. {
  313. u16 mii;
  314. spin_lock_irqsave(&sc->lmc_lock, flags);
  315. mii = lmc_mii_readreg (sc, 0, 16);
  316. /*
  317. * Make all of them 0 and make input
  318. */
  319. lmc_gpio_mkinput(sc, 0xff);
  320. /*
  321. * make the reset output
  322. */
  323. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  324. /*
  325. * RESET low to force configuration. This also forces
  326. * the transmitter clock to be internal, but we expect to reset
  327. * that later anyway.
  328. */
  329. sc->lmc_gpio &= ~LMC_GEP_RESET;
  330. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  331. /*
  332. * hold for more than 10 microseconds
  333. */
  334. udelay(50);
  335. sc->lmc_gpio |= LMC_GEP_RESET;
  336. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  337. /*
  338. * stop driving Xilinx-related signals
  339. */
  340. lmc_gpio_mkinput(sc, 0xff);
  341. /* Reset the frammer hardware */
  342. sc->lmc_media->set_link_status (sc, 1);
  343. sc->lmc_media->set_status (sc, NULL);
  344. // lmc_softreset(sc);
  345. {
  346. int i;
  347. for(i = 0; i < 5; i++){
  348. lmc_led_on(sc, LMC_DS3_LED0);
  349. mdelay(100);
  350. lmc_led_off(sc, LMC_DS3_LED0);
  351. lmc_led_on(sc, LMC_DS3_LED1);
  352. mdelay(100);
  353. lmc_led_off(sc, LMC_DS3_LED1);
  354. lmc_led_on(sc, LMC_DS3_LED3);
  355. mdelay(100);
  356. lmc_led_off(sc, LMC_DS3_LED3);
  357. lmc_led_on(sc, LMC_DS3_LED2);
  358. mdelay(100);
  359. lmc_led_off(sc, LMC_DS3_LED2);
  360. }
  361. }
  362. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  363. ret = 0x0;
  364. }
  365. break;
  366. case lmc_xilinx_load_prom: /*fold02*/
  367. {
  368. u16 mii;
  369. int timeout = 500000;
  370. spin_lock_irqsave(&sc->lmc_lock, flags);
  371. mii = lmc_mii_readreg (sc, 0, 16);
  372. /*
  373. * Make all of them 0 and make input
  374. */
  375. lmc_gpio_mkinput(sc, 0xff);
  376. /*
  377. * make the reset output
  378. */
  379. lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  380. /*
  381. * RESET low to force configuration. This also forces
  382. * the transmitter clock to be internal, but we expect to reset
  383. * that later anyway.
  384. */
  385. sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
  386. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  387. /*
  388. * hold for more than 10 microseconds
  389. */
  390. udelay(50);
  391. sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
  392. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  393. /*
  394. * busy wait for the chip to reset
  395. */
  396. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  397. (timeout-- > 0))
  398. cpu_relax();
  399. /*
  400. * stop driving Xilinx-related signals
  401. */
  402. lmc_gpio_mkinput(sc, 0xff);
  403. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  404. ret = 0x0;
  405. break;
  406. }
  407. case lmc_xilinx_load: /*fold02*/
  408. {
  409. char *data;
  410. int pos;
  411. int timeout = 500000;
  412. if (!xc.data) {
  413. ret = -EINVAL;
  414. break;
  415. }
  416. data = kmalloc(xc.len, GFP_KERNEL);
  417. if (!data) {
  418. ret = -ENOMEM;
  419. break;
  420. }
  421. if(copy_from_user(data, xc.data, xc.len))
  422. {
  423. kfree(data);
  424. ret = -ENOMEM;
  425. break;
  426. }
  427. printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
  428. spin_lock_irqsave(&sc->lmc_lock, flags);
  429. lmc_gpio_mkinput(sc, 0xff);
  430. /*
  431. * Clear the Xilinx and start prgramming from the DEC
  432. */
  433. /*
  434. * Set ouput as:
  435. * Reset: 0 (active)
  436. * DP: 0 (active)
  437. * Mode: 1
  438. *
  439. */
  440. sc->lmc_gpio = 0x00;
  441. sc->lmc_gpio &= ~LMC_GEP_DP;
  442. sc->lmc_gpio &= ~LMC_GEP_RESET;
  443. sc->lmc_gpio |= LMC_GEP_MODE;
  444. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  445. lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
  446. /*
  447. * Wait at least 10 us 20 to be safe
  448. */
  449. udelay(50);
  450. /*
  451. * Clear reset and activate programming lines
  452. * Reset: Input
  453. * DP: Input
  454. * Clock: Output
  455. * Data: Output
  456. * Mode: Output
  457. */
  458. lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  459. /*
  460. * Set LOAD, DATA, Clock to 1
  461. */
  462. sc->lmc_gpio = 0x00;
  463. sc->lmc_gpio |= LMC_GEP_MODE;
  464. sc->lmc_gpio |= LMC_GEP_DATA;
  465. sc->lmc_gpio |= LMC_GEP_CLK;
  466. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  467. lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
  468. /*
  469. * busy wait for the chip to reset
  470. */
  471. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  472. (timeout-- > 0))
  473. cpu_relax();
  474. printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
  475. for(pos = 0; pos < xc.len; pos++){
  476. switch(data[pos]){
  477. case 0:
  478. sc->lmc_gpio &= ~LMC_GEP_DATA; /* Data is 0 */
  479. break;
  480. case 1:
  481. sc->lmc_gpio |= LMC_GEP_DATA; /* Data is 1 */
  482. break;
  483. default:
  484. printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
  485. sc->lmc_gpio |= LMC_GEP_DATA; /* Assume it's 1 */
  486. }
  487. sc->lmc_gpio &= ~LMC_GEP_CLK; /* Clock to zero */
  488. sc->lmc_gpio |= LMC_GEP_MODE;
  489. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  490. udelay(1);
  491. sc->lmc_gpio |= LMC_GEP_CLK; /* Put the clack back to one */
  492. sc->lmc_gpio |= LMC_GEP_MODE;
  493. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  494. udelay(1);
  495. }
  496. if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
  497. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
  498. }
  499. else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
  500. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
  501. }
  502. else {
  503. printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
  504. }
  505. lmc_gpio_mkinput(sc, 0xff);
  506. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  507. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  508. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  509. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  510. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  511. kfree(data);
  512. ret = 0;
  513. break;
  514. }
  515. default: /*fold02*/
  516. ret = -EBADE;
  517. break;
  518. }
  519. netif_wake_queue(dev);
  520. sc->lmc_txfull = 0;
  521. }
  522. break;
  523. default: /*fold01*/
  524. /* If we don't know what to do, give the protocol a shot. */
  525. ret = lmc_proto_ioctl (sc, ifr, cmd);
  526. break;
  527. }
  528. lmc_trace(dev, "lmc_ioctl out");
  529. return ret;
  530. }
  531. /* the watchdog process that cruises around */
  532. static void lmc_watchdog (unsigned long data) /*fold00*/
  533. {
  534. struct net_device *dev = (struct net_device *)data;
  535. lmc_softc_t *sc = dev_to_sc(dev);
  536. int link_status;
  537. u32 ticks;
  538. unsigned long flags;
  539. lmc_trace(dev, "lmc_watchdog in");
  540. spin_lock_irqsave(&sc->lmc_lock, flags);
  541. if(sc->check != 0xBEAFCAFE){
  542. printk("LMC: Corrupt net_device struct, breaking out\n");
  543. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  544. return;
  545. }
  546. /* Make sure the tx jabber and rx watchdog are off,
  547. * and the transmit and receive processes are running.
  548. */
  549. LMC_CSR_WRITE (sc, csr_15, 0x00000011);
  550. sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN;
  551. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  552. if (sc->lmc_ok == 0)
  553. goto kick_timer;
  554. LMC_EVENT_LOG(LMC_EVENT_WATCHDOG, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  555. /* --- begin time out check -----------------------------------
  556. * check for a transmit interrupt timeout
  557. * Has the packet xmt vs xmt serviced threshold been exceeded */
  558. if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  559. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  560. sc->tx_TimeoutInd == 0)
  561. {
  562. /* wait for the watchdog to come around again */
  563. sc->tx_TimeoutInd = 1;
  564. }
  565. else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  566. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  567. sc->tx_TimeoutInd)
  568. {
  569. LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0);
  570. sc->tx_TimeoutDisplay = 1;
  571. sc->extra_stats.tx_TimeoutCnt++;
  572. /* DEC chip is stuck, hit it with a RESET!!!! */
  573. lmc_running_reset (dev);
  574. /* look at receive & transmit process state to make sure they are running */
  575. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  576. /* look at: DSR - 02 for Reg 16
  577. * CTS - 08
  578. * DCD - 10
  579. * RI - 20
  580. * for Reg 17
  581. */
  582. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg (sc, 0, 16), lmc_mii_readreg (sc, 0, 17));
  583. /* reset the transmit timeout detection flag */
  584. sc->tx_TimeoutInd = 0;
  585. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  586. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  587. } else {
  588. sc->tx_TimeoutInd = 0;
  589. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  590. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  591. }
  592. /* --- end time out check ----------------------------------- */
  593. link_status = sc->lmc_media->get_link_status (sc);
  594. /*
  595. * hardware level link lost, but the interface is marked as up.
  596. * Mark it as down.
  597. */
  598. if ((link_status == 0) && (sc->last_link_status != 0)) {
  599. printk(KERN_WARNING "%s: hardware/physical link down\n", dev->name);
  600. sc->last_link_status = 0;
  601. /* lmc_reset (sc); Why reset??? The link can go down ok */
  602. /* Inform the world that link has been lost */
  603. netif_carrier_off(dev);
  604. }
  605. /*
  606. * hardware link is up, but the interface is marked as down.
  607. * Bring it back up again.
  608. */
  609. if (link_status != 0 && sc->last_link_status == 0) {
  610. printk(KERN_WARNING "%s: hardware/physical link up\n", dev->name);
  611. sc->last_link_status = 1;
  612. /* lmc_reset (sc); Again why reset??? */
  613. netif_carrier_on(dev);
  614. }
  615. /* Call media specific watchdog functions */
  616. sc->lmc_media->watchdog(sc);
  617. /*
  618. * Poke the transmitter to make sure it
  619. * never stops, even if we run out of mem
  620. */
  621. LMC_CSR_WRITE(sc, csr_rxpoll, 0);
  622. /*
  623. * Check for code that failed
  624. * and try and fix it as appropriate
  625. */
  626. if(sc->failed_ring == 1){
  627. /*
  628. * Failed to setup the recv/xmit rin
  629. * Try again
  630. */
  631. sc->failed_ring = 0;
  632. lmc_softreset(sc);
  633. }
  634. if(sc->failed_recv_alloc == 1){
  635. /*
  636. * We failed to alloc mem in the
  637. * interrupt handler, go through the rings
  638. * and rebuild them
  639. */
  640. sc->failed_recv_alloc = 0;
  641. lmc_softreset(sc);
  642. }
  643. /*
  644. * remember the timer value
  645. */
  646. kick_timer:
  647. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  648. LMC_CSR_WRITE (sc, csr_gp_timer, 0xffffffffUL);
  649. sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff);
  650. /*
  651. * restart this timer.
  652. */
  653. sc->timer.expires = jiffies + (HZ);
  654. add_timer (&sc->timer);
  655. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  656. lmc_trace(dev, "lmc_watchdog out");
  657. }
  658. static int lmc_attach(struct net_device *dev, unsigned short encoding,
  659. unsigned short parity)
  660. {
  661. if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
  662. return 0;
  663. return -EINVAL;
  664. }
  665. static const struct net_device_ops lmc_ops = {
  666. .ndo_open = lmc_open,
  667. .ndo_stop = lmc_close,
  668. .ndo_start_xmit = hdlc_start_xmit,
  669. .ndo_do_ioctl = lmc_ioctl,
  670. .ndo_tx_timeout = lmc_driver_timeout,
  671. .ndo_get_stats = lmc_get_stats,
  672. };
  673. static int lmc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  674. {
  675. lmc_softc_t *sc;
  676. struct net_device *dev;
  677. u16 subdevice;
  678. u16 AdapModelNum;
  679. int err;
  680. static int cards_found;
  681. /* lmc_trace(dev, "lmc_init_one in"); */
  682. err = pcim_enable_device(pdev);
  683. if (err) {
  684. printk(KERN_ERR "lmc: pci enable failed: %d\n", err);
  685. return err;
  686. }
  687. err = pci_request_regions(pdev, "lmc");
  688. if (err) {
  689. printk(KERN_ERR "lmc: pci_request_region failed\n");
  690. return err;
  691. }
  692. /*
  693. * Allocate our own device structure
  694. */
  695. sc = devm_kzalloc(&pdev->dev, sizeof(lmc_softc_t), GFP_KERNEL);
  696. if (!sc)
  697. return -ENOMEM;
  698. dev = alloc_hdlcdev(sc);
  699. if (!dev) {
  700. printk(KERN_ERR "lmc:alloc_netdev for device failed\n");
  701. return -ENOMEM;
  702. }
  703. dev->type = ARPHRD_HDLC;
  704. dev_to_hdlc(dev)->xmit = lmc_start_xmit;
  705. dev_to_hdlc(dev)->attach = lmc_attach;
  706. dev->netdev_ops = &lmc_ops;
  707. dev->watchdog_timeo = HZ; /* 1 second */
  708. dev->tx_queue_len = 100;
  709. sc->lmc_device = dev;
  710. sc->name = dev->name;
  711. sc->if_type = LMC_PPP;
  712. sc->check = 0xBEAFCAFE;
  713. dev->base_addr = pci_resource_start(pdev, 0);
  714. dev->irq = pdev->irq;
  715. pci_set_drvdata(pdev, dev);
  716. SET_NETDEV_DEV(dev, &pdev->dev);
  717. /*
  718. * This will get the protocol layer ready and do any 1 time init's
  719. * Must have a valid sc and dev structure
  720. */
  721. lmc_proto_attach(sc);
  722. /* Init the spin lock so can call it latter */
  723. spin_lock_init(&sc->lmc_lock);
  724. pci_set_master(pdev);
  725. printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name,
  726. dev->base_addr, dev->irq);
  727. err = register_hdlc_device(dev);
  728. if (err) {
  729. printk(KERN_ERR "%s: register_netdev failed.\n", dev->name);
  730. free_netdev(dev);
  731. return err;
  732. }
  733. sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN;
  734. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  735. /*
  736. *
  737. * Check either the subvendor or the subdevice, some systems reverse
  738. * the setting in the bois, seems to be version and arch dependent?
  739. * Fix the error, exchange the two values
  740. */
  741. if ((subdevice = pdev->subsystem_device) == PCI_VENDOR_ID_LMC)
  742. subdevice = pdev->subsystem_vendor;
  743. switch (subdevice) {
  744. case PCI_DEVICE_ID_LMC_HSSI:
  745. printk(KERN_INFO "%s: LMC HSSI\n", dev->name);
  746. sc->lmc_cardtype = LMC_CARDTYPE_HSSI;
  747. sc->lmc_media = &lmc_hssi_media;
  748. break;
  749. case PCI_DEVICE_ID_LMC_DS3:
  750. printk(KERN_INFO "%s: LMC DS3\n", dev->name);
  751. sc->lmc_cardtype = LMC_CARDTYPE_DS3;
  752. sc->lmc_media = &lmc_ds3_media;
  753. break;
  754. case PCI_DEVICE_ID_LMC_SSI:
  755. printk(KERN_INFO "%s: LMC SSI\n", dev->name);
  756. sc->lmc_cardtype = LMC_CARDTYPE_SSI;
  757. sc->lmc_media = &lmc_ssi_media;
  758. break;
  759. case PCI_DEVICE_ID_LMC_T1:
  760. printk(KERN_INFO "%s: LMC T1\n", dev->name);
  761. sc->lmc_cardtype = LMC_CARDTYPE_T1;
  762. sc->lmc_media = &lmc_t1_media;
  763. break;
  764. default:
  765. printk(KERN_WARNING "%s: LMC UNKNOWN CARD!\n", dev->name);
  766. break;
  767. }
  768. lmc_initcsrs (sc, dev->base_addr, 8);
  769. lmc_gpio_mkinput (sc, 0xff);
  770. sc->lmc_gpio = 0; /* drive no signals yet */
  771. sc->lmc_media->defaults (sc);
  772. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  773. /* verify that the PCI Sub System ID matches the Adapter Model number
  774. * from the MII register
  775. */
  776. AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4;
  777. if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */
  778. subdevice != PCI_DEVICE_ID_LMC_T1) &&
  779. (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */
  780. subdevice != PCI_DEVICE_ID_LMC_SSI) &&
  781. (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */
  782. subdevice != PCI_DEVICE_ID_LMC_DS3) &&
  783. (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */
  784. subdevice != PCI_DEVICE_ID_LMC_HSSI))
  785. printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI"
  786. " Subsystem ID = 0x%04x\n",
  787. dev->name, AdapModelNum, subdevice);
  788. /*
  789. * reset clock
  790. */
  791. LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL);
  792. sc->board_idx = cards_found++;
  793. sc->extra_stats.check = STATCHECK;
  794. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  795. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  796. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  797. sc->lmc_ok = 0;
  798. sc->last_link_status = 0;
  799. lmc_trace(dev, "lmc_init_one out");
  800. return 0;
  801. }
  802. /*
  803. * Called from pci when removing module.
  804. */
  805. static void lmc_remove_one(struct pci_dev *pdev)
  806. {
  807. struct net_device *dev = pci_get_drvdata(pdev);
  808. if (dev) {
  809. printk(KERN_DEBUG "%s: removing...\n", dev->name);
  810. unregister_hdlc_device(dev);
  811. free_netdev(dev);
  812. }
  813. }
  814. /* After this is called, packets can be sent.
  815. * Does not initialize the addresses
  816. */
  817. static int lmc_open(struct net_device *dev)
  818. {
  819. lmc_softc_t *sc = dev_to_sc(dev);
  820. int err;
  821. lmc_trace(dev, "lmc_open in");
  822. lmc_led_on(sc, LMC_DS3_LED0);
  823. lmc_dec_reset(sc);
  824. lmc_reset(sc);
  825. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0);
  826. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16),
  827. lmc_mii_readreg(sc, 0, 17));
  828. if (sc->lmc_ok){
  829. lmc_trace(dev, "lmc_open lmc_ok out");
  830. return 0;
  831. }
  832. lmc_softreset (sc);
  833. /* Since we have to use PCI bus, this should work on x86,alpha,ppc */
  834. if (request_irq (dev->irq, lmc_interrupt, IRQF_SHARED, dev->name, dev)){
  835. printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
  836. lmc_trace(dev, "lmc_open irq failed out");
  837. return -EAGAIN;
  838. }
  839. sc->got_irq = 1;
  840. /* Assert Terminal Active */
  841. sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
  842. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  843. /*
  844. * reset to last state.
  845. */
  846. sc->lmc_media->set_status (sc, NULL);
  847. /* setup default bits to be used in tulip_desc_t transmit descriptor
  848. * -baz */
  849. sc->TxDescriptControlInit = (
  850. LMC_TDES_INTERRUPT_ON_COMPLETION
  851. | LMC_TDES_FIRST_SEGMENT
  852. | LMC_TDES_LAST_SEGMENT
  853. | LMC_TDES_SECOND_ADDR_CHAINED
  854. | LMC_TDES_DISABLE_PADDING
  855. );
  856. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16) {
  857. /* disable 32 bit CRC generated by ASIC */
  858. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  859. }
  860. sc->lmc_media->set_crc_length(sc, sc->ictl.crc_length);
  861. /* Acknoledge the Terminal Active and light LEDs */
  862. /* dev->flags |= IFF_UP; */
  863. if ((err = lmc_proto_open(sc)) != 0)
  864. return err;
  865. netif_start_queue(dev);
  866. sc->extra_stats.tx_tbusy0++;
  867. /*
  868. * select what interrupts we want to get
  869. */
  870. sc->lmc_intrmask = 0;
  871. /* Should be using the default interrupt mask defined in the .h file. */
  872. sc->lmc_intrmask |= (TULIP_STS_NORMALINTR
  873. | TULIP_STS_RXINTR
  874. | TULIP_STS_TXINTR
  875. | TULIP_STS_ABNRMLINTR
  876. | TULIP_STS_SYSERROR
  877. | TULIP_STS_TXSTOPPED
  878. | TULIP_STS_TXUNDERFLOW
  879. | TULIP_STS_RXSTOPPED
  880. | TULIP_STS_RXNOBUF
  881. );
  882. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  883. sc->lmc_cmdmode |= TULIP_CMD_TXRUN;
  884. sc->lmc_cmdmode |= TULIP_CMD_RXRUN;
  885. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  886. sc->lmc_ok = 1; /* Run watchdog */
  887. /*
  888. * Set the if up now - pfb
  889. */
  890. sc->last_link_status = 1;
  891. /*
  892. * Setup a timer for the watchdog on probe, and start it running.
  893. * Since lmc_ok == 0, it will be a NOP for now.
  894. */
  895. setup_timer(&sc->timer, lmc_watchdog, (unsigned long)dev);
  896. sc->timer.expires = jiffies + HZ;
  897. add_timer (&sc->timer);
  898. lmc_trace(dev, "lmc_open out");
  899. return 0;
  900. }
  901. /* Total reset to compensate for the AdTran DSU doing bad things
  902. * under heavy load
  903. */
  904. static void lmc_running_reset (struct net_device *dev) /*fold00*/
  905. {
  906. lmc_softc_t *sc = dev_to_sc(dev);
  907. lmc_trace(dev, "lmc_running_reset in");
  908. /* stop interrupts */
  909. /* Clear the interrupt mask */
  910. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  911. lmc_dec_reset (sc);
  912. lmc_reset (sc);
  913. lmc_softreset (sc);
  914. /* sc->lmc_miireg16 |= LMC_MII16_LED_ALL; */
  915. sc->lmc_media->set_link_status (sc, 1);
  916. sc->lmc_media->set_status (sc, NULL);
  917. netif_wake_queue(dev);
  918. sc->lmc_txfull = 0;
  919. sc->extra_stats.tx_tbusy0++;
  920. sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK;
  921. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  922. sc->lmc_cmdmode |= (TULIP_CMD_TXRUN | TULIP_CMD_RXRUN);
  923. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  924. lmc_trace(dev, "lmc_runnin_reset_out");
  925. }
  926. /* This is what is called when you ifconfig down a device.
  927. * This disables the timer for the watchdog and keepalives,
  928. * and disables the irq for dev.
  929. */
  930. static int lmc_close(struct net_device *dev)
  931. {
  932. /* not calling release_region() as we should */
  933. lmc_softc_t *sc = dev_to_sc(dev);
  934. lmc_trace(dev, "lmc_close in");
  935. sc->lmc_ok = 0;
  936. sc->lmc_media->set_link_status (sc, 0);
  937. del_timer (&sc->timer);
  938. lmc_proto_close(sc);
  939. lmc_ifdown (dev);
  940. lmc_trace(dev, "lmc_close out");
  941. return 0;
  942. }
  943. /* Ends the transfer of packets */
  944. /* When the interface goes down, this is called */
  945. static int lmc_ifdown (struct net_device *dev) /*fold00*/
  946. {
  947. lmc_softc_t *sc = dev_to_sc(dev);
  948. u32 csr6;
  949. int i;
  950. lmc_trace(dev, "lmc_ifdown in");
  951. /* Don't let anything else go on right now */
  952. // dev->start = 0;
  953. netif_stop_queue(dev);
  954. sc->extra_stats.tx_tbusy1++;
  955. /* stop interrupts */
  956. /* Clear the interrupt mask */
  957. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  958. /* Stop Tx and Rx on the chip */
  959. csr6 = LMC_CSR_READ (sc, csr_command);
  960. csr6 &= ~LMC_DEC_ST; /* Turn off the Transmission bit */
  961. csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
  962. LMC_CSR_WRITE (sc, csr_command, csr6);
  963. sc->lmc_device->stats.rx_missed_errors +=
  964. LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  965. /* release the interrupt */
  966. if(sc->got_irq == 1){
  967. free_irq (dev->irq, dev);
  968. sc->got_irq = 0;
  969. }
  970. /* free skbuffs in the Rx queue */
  971. for (i = 0; i < LMC_RXDESCS; i++)
  972. {
  973. struct sk_buff *skb = sc->lmc_rxq[i];
  974. sc->lmc_rxq[i] = NULL;
  975. sc->lmc_rxring[i].status = 0;
  976. sc->lmc_rxring[i].length = 0;
  977. sc->lmc_rxring[i].buffer1 = 0xDEADBEEF;
  978. if (skb != NULL)
  979. dev_kfree_skb(skb);
  980. sc->lmc_rxq[i] = NULL;
  981. }
  982. for (i = 0; i < LMC_TXDESCS; i++)
  983. {
  984. if (sc->lmc_txq[i] != NULL)
  985. dev_kfree_skb(sc->lmc_txq[i]);
  986. sc->lmc_txq[i] = NULL;
  987. }
  988. lmc_led_off (sc, LMC_MII16_LED_ALL);
  989. netif_wake_queue(dev);
  990. sc->extra_stats.tx_tbusy0++;
  991. lmc_trace(dev, "lmc_ifdown out");
  992. return 0;
  993. }
  994. /* Interrupt handling routine. This will take an incoming packet, or clean
  995. * up after a trasmit.
  996. */
  997. static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/
  998. {
  999. struct net_device *dev = (struct net_device *) dev_instance;
  1000. lmc_softc_t *sc = dev_to_sc(dev);
  1001. u32 csr;
  1002. int i;
  1003. s32 stat;
  1004. unsigned int badtx;
  1005. u32 firstcsr;
  1006. int max_work = LMC_RXDESCS;
  1007. int handled = 0;
  1008. lmc_trace(dev, "lmc_interrupt in");
  1009. spin_lock(&sc->lmc_lock);
  1010. /*
  1011. * Read the csr to find what interrupts we have (if any)
  1012. */
  1013. csr = LMC_CSR_READ (sc, csr_status);
  1014. /*
  1015. * Make sure this is our interrupt
  1016. */
  1017. if ( ! (csr & sc->lmc_intrmask)) {
  1018. goto lmc_int_fail_out;
  1019. }
  1020. firstcsr = csr;
  1021. /* always go through this loop at least once */
  1022. while (csr & sc->lmc_intrmask) {
  1023. handled = 1;
  1024. /*
  1025. * Clear interrupt bits, we handle all case below
  1026. */
  1027. LMC_CSR_WRITE (sc, csr_status, csr);
  1028. /*
  1029. * One of
  1030. * - Transmit process timed out CSR5<1>
  1031. * - Transmit jabber timeout CSR5<3>
  1032. * - Transmit underflow CSR5<5>
  1033. * - Transmit Receiver buffer unavailable CSR5<7>
  1034. * - Receive process stopped CSR5<8>
  1035. * - Receive watchdog timeout CSR5<9>
  1036. * - Early transmit interrupt CSR5<10>
  1037. *
  1038. * Is this really right? Should we do a running reset for jabber?
  1039. * (being a WAN card and all)
  1040. */
  1041. if (csr & TULIP_STS_ABNRMLINTR){
  1042. lmc_running_reset (dev);
  1043. break;
  1044. }
  1045. if (csr & TULIP_STS_RXINTR){
  1046. lmc_trace(dev, "rx interrupt");
  1047. lmc_rx (dev);
  1048. }
  1049. if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) {
  1050. int n_compl = 0 ;
  1051. /* reset the transmit timeout detection flag -baz */
  1052. sc->extra_stats.tx_NoCompleteCnt = 0;
  1053. badtx = sc->lmc_taint_tx;
  1054. i = badtx % LMC_TXDESCS;
  1055. while ((badtx < sc->lmc_next_tx)) {
  1056. stat = sc->lmc_txring[i].status;
  1057. LMC_EVENT_LOG (LMC_EVENT_XMTINT, stat,
  1058. sc->lmc_txring[i].length);
  1059. /*
  1060. * If bit 31 is 1 the tulip owns it break out of the loop
  1061. */
  1062. if (stat & 0x80000000)
  1063. break;
  1064. n_compl++ ; /* i.e., have an empty slot in ring */
  1065. /*
  1066. * If we have no skbuff or have cleared it
  1067. * Already continue to the next buffer
  1068. */
  1069. if (sc->lmc_txq[i] == NULL)
  1070. continue;
  1071. /*
  1072. * Check the total error summary to look for any errors
  1073. */
  1074. if (stat & 0x8000) {
  1075. sc->lmc_device->stats.tx_errors++;
  1076. if (stat & 0x4104)
  1077. sc->lmc_device->stats.tx_aborted_errors++;
  1078. if (stat & 0x0C00)
  1079. sc->lmc_device->stats.tx_carrier_errors++;
  1080. if (stat & 0x0200)
  1081. sc->lmc_device->stats.tx_window_errors++;
  1082. if (stat & 0x0002)
  1083. sc->lmc_device->stats.tx_fifo_errors++;
  1084. } else {
  1085. sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff;
  1086. sc->lmc_device->stats.tx_packets++;
  1087. }
  1088. // dev_kfree_skb(sc->lmc_txq[i]);
  1089. dev_kfree_skb_irq(sc->lmc_txq[i]);
  1090. sc->lmc_txq[i] = NULL;
  1091. badtx++;
  1092. i = badtx % LMC_TXDESCS;
  1093. }
  1094. if (sc->lmc_next_tx - badtx > LMC_TXDESCS)
  1095. {
  1096. printk ("%s: out of sync pointer\n", dev->name);
  1097. badtx += LMC_TXDESCS;
  1098. }
  1099. LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0);
  1100. sc->lmc_txfull = 0;
  1101. netif_wake_queue(dev);
  1102. sc->extra_stats.tx_tbusy0++;
  1103. #ifdef DEBUG
  1104. sc->extra_stats.dirtyTx = badtx;
  1105. sc->extra_stats.lmc_next_tx = sc->lmc_next_tx;
  1106. sc->extra_stats.lmc_txfull = sc->lmc_txfull;
  1107. #endif
  1108. sc->lmc_taint_tx = badtx;
  1109. /*
  1110. * Why was there a break here???
  1111. */
  1112. } /* end handle transmit interrupt */
  1113. if (csr & TULIP_STS_SYSERROR) {
  1114. u32 error;
  1115. printk (KERN_WARNING "%s: system bus error csr: %#8.8x\n", dev->name, csr);
  1116. error = csr>>23 & 0x7;
  1117. switch(error){
  1118. case 0x000:
  1119. printk(KERN_WARNING "%s: Parity Fault (bad)\n", dev->name);
  1120. break;
  1121. case 0x001:
  1122. printk(KERN_WARNING "%s: Master Abort (naughty)\n", dev->name);
  1123. break;
  1124. case 0x010:
  1125. printk(KERN_WARNING "%s: Target Abort (not so naughty)\n", dev->name);
  1126. break;
  1127. default:
  1128. printk(KERN_WARNING "%s: This bus error code was supposed to be reserved!\n", dev->name);
  1129. }
  1130. lmc_dec_reset (sc);
  1131. lmc_reset (sc);
  1132. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1133. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1134. lmc_mii_readreg (sc, 0, 16),
  1135. lmc_mii_readreg (sc, 0, 17));
  1136. }
  1137. if(max_work-- <= 0)
  1138. break;
  1139. /*
  1140. * Get current csr status to make sure
  1141. * we've cleared all interrupts
  1142. */
  1143. csr = LMC_CSR_READ (sc, csr_status);
  1144. } /* end interrupt loop */
  1145. LMC_EVENT_LOG(LMC_EVENT_INT, firstcsr, csr);
  1146. lmc_int_fail_out:
  1147. spin_unlock(&sc->lmc_lock);
  1148. lmc_trace(dev, "lmc_interrupt out");
  1149. return IRQ_RETVAL(handled);
  1150. }
  1151. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  1152. struct net_device *dev)
  1153. {
  1154. lmc_softc_t *sc = dev_to_sc(dev);
  1155. u32 flag;
  1156. int entry;
  1157. unsigned long flags;
  1158. lmc_trace(dev, "lmc_start_xmit in");
  1159. spin_lock_irqsave(&sc->lmc_lock, flags);
  1160. /* normal path, tbusy known to be zero */
  1161. entry = sc->lmc_next_tx % LMC_TXDESCS;
  1162. sc->lmc_txq[entry] = skb;
  1163. sc->lmc_txring[entry].buffer1 = virt_to_bus (skb->data);
  1164. LMC_CONSOLE_LOG("xmit", skb->data, skb->len);
  1165. #ifndef GCOM
  1166. /* If the queue is less than half full, don't interrupt */
  1167. if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS / 2)
  1168. {
  1169. /* Do not interrupt on completion of this packet */
  1170. flag = 0x60000000;
  1171. netif_wake_queue(dev);
  1172. }
  1173. else if (sc->lmc_next_tx - sc->lmc_taint_tx == LMC_TXDESCS / 2)
  1174. {
  1175. /* This generates an interrupt on completion of this packet */
  1176. flag = 0xe0000000;
  1177. netif_wake_queue(dev);
  1178. }
  1179. else if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS - 1)
  1180. {
  1181. /* Do not interrupt on completion of this packet */
  1182. flag = 0x60000000;
  1183. netif_wake_queue(dev);
  1184. }
  1185. else
  1186. {
  1187. /* This generates an interrupt on completion of this packet */
  1188. flag = 0xe0000000;
  1189. sc->lmc_txfull = 1;
  1190. netif_stop_queue(dev);
  1191. }
  1192. #else
  1193. flag = LMC_TDES_INTERRUPT_ON_COMPLETION;
  1194. if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1)
  1195. { /* ring full, go busy */
  1196. sc->lmc_txfull = 1;
  1197. netif_stop_queue(dev);
  1198. sc->extra_stats.tx_tbusy1++;
  1199. LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0);
  1200. }
  1201. #endif
  1202. if (entry == LMC_TXDESCS - 1) /* last descriptor in ring */
  1203. flag |= LMC_TDES_END_OF_RING; /* flag as such for Tulip */
  1204. /* don't pad small packets either */
  1205. flag = sc->lmc_txring[entry].length = (skb->len) | flag |
  1206. sc->TxDescriptControlInit;
  1207. /* set the transmit timeout flag to be checked in
  1208. * the watchdog timer handler. -baz
  1209. */
  1210. sc->extra_stats.tx_NoCompleteCnt++;
  1211. sc->lmc_next_tx++;
  1212. /* give ownership to the chip */
  1213. LMC_EVENT_LOG(LMC_EVENT_XMT, flag, entry);
  1214. sc->lmc_txring[entry].status = 0x80000000;
  1215. /* send now! */
  1216. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1217. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1218. lmc_trace(dev, "lmc_start_xmit_out");
  1219. return NETDEV_TX_OK;
  1220. }
  1221. static int lmc_rx(struct net_device *dev)
  1222. {
  1223. lmc_softc_t *sc = dev_to_sc(dev);
  1224. int i;
  1225. int rx_work_limit = LMC_RXDESCS;
  1226. unsigned int next_rx;
  1227. int rxIntLoopCnt; /* debug -baz */
  1228. int localLengthErrCnt = 0;
  1229. long stat;
  1230. struct sk_buff *skb, *nsb;
  1231. u16 len;
  1232. lmc_trace(dev, "lmc_rx in");
  1233. lmc_led_on(sc, LMC_DS3_LED3);
  1234. rxIntLoopCnt = 0; /* debug -baz */
  1235. i = sc->lmc_next_rx % LMC_RXDESCS;
  1236. next_rx = sc->lmc_next_rx;
  1237. while (((stat = sc->lmc_rxring[i].status) & LMC_RDES_OWN_BIT) != DESC_OWNED_BY_DC21X4)
  1238. {
  1239. rxIntLoopCnt++; /* debug -baz */
  1240. len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER);
  1241. if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */
  1242. if ((stat & 0x0000ffff) != 0x7fff) {
  1243. /* Oversized frame */
  1244. sc->lmc_device->stats.rx_length_errors++;
  1245. goto skip_packet;
  1246. }
  1247. }
  1248. if (stat & 0x00000008) { /* Catch a dribbling bit error */
  1249. sc->lmc_device->stats.rx_errors++;
  1250. sc->lmc_device->stats.rx_frame_errors++;
  1251. goto skip_packet;
  1252. }
  1253. if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */
  1254. sc->lmc_device->stats.rx_errors++;
  1255. sc->lmc_device->stats.rx_crc_errors++;
  1256. goto skip_packet;
  1257. }
  1258. if (len > LMC_PKT_BUF_SZ) {
  1259. sc->lmc_device->stats.rx_length_errors++;
  1260. localLengthErrCnt++;
  1261. goto skip_packet;
  1262. }
  1263. if (len < sc->lmc_crcSize + 2) {
  1264. sc->lmc_device->stats.rx_length_errors++;
  1265. sc->extra_stats.rx_SmallPktCnt++;
  1266. localLengthErrCnt++;
  1267. goto skip_packet;
  1268. }
  1269. if(stat & 0x00004000){
  1270. printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name);
  1271. }
  1272. len -= sc->lmc_crcSize;
  1273. skb = sc->lmc_rxq[i];
  1274. /*
  1275. * We ran out of memory at some point
  1276. * just allocate an skb buff and continue.
  1277. */
  1278. if (!skb) {
  1279. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1280. if (nsb) {
  1281. sc->lmc_rxq[i] = nsb;
  1282. nsb->dev = dev;
  1283. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1284. }
  1285. sc->failed_recv_alloc = 1;
  1286. goto skip_packet;
  1287. }
  1288. sc->lmc_device->stats.rx_packets++;
  1289. sc->lmc_device->stats.rx_bytes += len;
  1290. LMC_CONSOLE_LOG("recv", skb->data, len);
  1291. /*
  1292. * I'm not sure of the sanity of this
  1293. * Packets could be arriving at a constant
  1294. * 44.210mbits/sec and we're going to copy
  1295. * them into a new buffer??
  1296. */
  1297. if(len > (LMC_MTU - (LMC_MTU>>2))){ /* len > LMC_MTU * 0.75 */
  1298. /*
  1299. * If it's a large packet don't copy it just hand it up
  1300. */
  1301. give_it_anyways:
  1302. sc->lmc_rxq[i] = NULL;
  1303. sc->lmc_rxring[i].buffer1 = 0x0;
  1304. skb_put (skb, len);
  1305. skb->protocol = lmc_proto_type(sc, skb);
  1306. skb_reset_mac_header(skb);
  1307. /* skb_reset_network_header(skb); */
  1308. skb->dev = dev;
  1309. lmc_proto_netif(sc, skb);
  1310. /*
  1311. * This skb will be destroyed by the upper layers, make a new one
  1312. */
  1313. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1314. if (nsb) {
  1315. sc->lmc_rxq[i] = nsb;
  1316. nsb->dev = dev;
  1317. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1318. /* Transferred to 21140 below */
  1319. }
  1320. else {
  1321. /*
  1322. * We've run out of memory, stop trying to allocate
  1323. * memory and exit the interrupt handler
  1324. *
  1325. * The chip may run out of receivers and stop
  1326. * in which care we'll try to allocate the buffer
  1327. * again. (once a second)
  1328. */
  1329. sc->extra_stats.rx_BuffAllocErr++;
  1330. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1331. sc->failed_recv_alloc = 1;
  1332. goto skip_out_of_mem;
  1333. }
  1334. }
  1335. else {
  1336. nsb = dev_alloc_skb(len);
  1337. if(!nsb) {
  1338. goto give_it_anyways;
  1339. }
  1340. skb_copy_from_linear_data(skb, skb_put(nsb, len), len);
  1341. nsb->protocol = lmc_proto_type(sc, nsb);
  1342. skb_reset_mac_header(nsb);
  1343. /* skb_reset_network_header(nsb); */
  1344. nsb->dev = dev;
  1345. lmc_proto_netif(sc, nsb);
  1346. }
  1347. skip_packet:
  1348. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1349. sc->lmc_rxring[i].status = DESC_OWNED_BY_DC21X4;
  1350. sc->lmc_next_rx++;
  1351. i = sc->lmc_next_rx % LMC_RXDESCS;
  1352. rx_work_limit--;
  1353. if (rx_work_limit < 0)
  1354. break;
  1355. }
  1356. /* detect condition for LMC1000 where DSU cable attaches and fills
  1357. * descriptors with bogus packets
  1358. *
  1359. if (localLengthErrCnt > LMC_RXDESCS - 3) {
  1360. sc->extra_stats.rx_BadPktSurgeCnt++;
  1361. LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt,
  1362. sc->extra_stats.rx_BadPktSurgeCnt);
  1363. } */
  1364. /* save max count of receive descriptors serviced */
  1365. if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt)
  1366. sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */
  1367. #ifdef DEBUG
  1368. if (rxIntLoopCnt == 0)
  1369. {
  1370. for (i = 0; i < LMC_RXDESCS; i++)
  1371. {
  1372. if ((sc->lmc_rxring[i].status & LMC_RDES_OWN_BIT)
  1373. != DESC_OWNED_BY_DC21X4)
  1374. {
  1375. rxIntLoopCnt++;
  1376. }
  1377. }
  1378. LMC_EVENT_LOG(LMC_EVENT_RCVEND, rxIntLoopCnt, 0);
  1379. }
  1380. #endif
  1381. lmc_led_off(sc, LMC_DS3_LED3);
  1382. skip_out_of_mem:
  1383. lmc_trace(dev, "lmc_rx out");
  1384. return 0;
  1385. }
  1386. static struct net_device_stats *lmc_get_stats(struct net_device *dev)
  1387. {
  1388. lmc_softc_t *sc = dev_to_sc(dev);
  1389. unsigned long flags;
  1390. lmc_trace(dev, "lmc_get_stats in");
  1391. spin_lock_irqsave(&sc->lmc_lock, flags);
  1392. sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  1393. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1394. lmc_trace(dev, "lmc_get_stats out");
  1395. return &sc->lmc_device->stats;
  1396. }
  1397. static struct pci_driver lmc_driver = {
  1398. .name = "lmc",
  1399. .id_table = lmc_pci_tbl,
  1400. .probe = lmc_init_one,
  1401. .remove = lmc_remove_one,
  1402. };
  1403. module_pci_driver(lmc_driver);
  1404. unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno) /*fold00*/
  1405. {
  1406. int i;
  1407. int command = (0xf6 << 10) | (devaddr << 5) | regno;
  1408. int retval = 0;
  1409. lmc_trace(sc->lmc_device, "lmc_mii_readreg in");
  1410. LMC_MII_SYNC (sc);
  1411. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done sync");
  1412. for (i = 15; i >= 0; i--)
  1413. {
  1414. int dataval = (command & (1 << i)) ? 0x20000 : 0;
  1415. LMC_CSR_WRITE (sc, csr_9, dataval);
  1416. lmc_delay ();
  1417. /* __SLOW_DOWN_IO; */
  1418. LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
  1419. lmc_delay ();
  1420. /* __SLOW_DOWN_IO; */
  1421. }
  1422. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done1");
  1423. for (i = 19; i > 0; i--)
  1424. {
  1425. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1426. lmc_delay ();
  1427. /* __SLOW_DOWN_IO; */
  1428. retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
  1429. LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
  1430. lmc_delay ();
  1431. /* __SLOW_DOWN_IO; */
  1432. }
  1433. lmc_trace(sc->lmc_device, "lmc_mii_readreg out");
  1434. return (retval >> 1) & 0xffff;
  1435. }
  1436. void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno, unsigned data) /*fold00*/
  1437. {
  1438. int i = 32;
  1439. int command = (0x5002 << 16) | (devaddr << 23) | (regno << 18) | data;
  1440. lmc_trace(sc->lmc_device, "lmc_mii_writereg in");
  1441. LMC_MII_SYNC (sc);
  1442. i = 31;
  1443. while (i >= 0)
  1444. {
  1445. int datav;
  1446. if (command & (1 << i))
  1447. datav = 0x20000;
  1448. else
  1449. datav = 0x00000;
  1450. LMC_CSR_WRITE (sc, csr_9, datav);
  1451. lmc_delay ();
  1452. /* __SLOW_DOWN_IO; */
  1453. LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
  1454. lmc_delay ();
  1455. /* __SLOW_DOWN_IO; */
  1456. i--;
  1457. }
  1458. i = 2;
  1459. while (i > 0)
  1460. {
  1461. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1462. lmc_delay ();
  1463. /* __SLOW_DOWN_IO; */
  1464. LMC_CSR_WRITE (sc, csr_9, 0x50000);
  1465. lmc_delay ();
  1466. /* __SLOW_DOWN_IO; */
  1467. i--;
  1468. }
  1469. lmc_trace(sc->lmc_device, "lmc_mii_writereg out");
  1470. }
  1471. static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/
  1472. {
  1473. int i;
  1474. lmc_trace(sc->lmc_device, "lmc_softreset in");
  1475. /* Initialize the receive rings and buffers. */
  1476. sc->lmc_txfull = 0;
  1477. sc->lmc_next_rx = 0;
  1478. sc->lmc_next_tx = 0;
  1479. sc->lmc_taint_rx = 0;
  1480. sc->lmc_taint_tx = 0;
  1481. /*
  1482. * Setup each one of the receiver buffers
  1483. * allocate an skbuff for each one, setup the descriptor table
  1484. * and point each buffer at the next one
  1485. */
  1486. for (i = 0; i < LMC_RXDESCS; i++)
  1487. {
  1488. struct sk_buff *skb;
  1489. if (sc->lmc_rxq[i] == NULL)
  1490. {
  1491. skb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1492. if(skb == NULL){
  1493. printk(KERN_WARNING "%s: Failed to allocate receiver ring, will try again\n", sc->name);
  1494. sc->failed_ring = 1;
  1495. break;
  1496. }
  1497. else{
  1498. sc->lmc_rxq[i] = skb;
  1499. }
  1500. }
  1501. else
  1502. {
  1503. skb = sc->lmc_rxq[i];
  1504. }
  1505. skb->dev = sc->lmc_device;
  1506. /* owned by 21140 */
  1507. sc->lmc_rxring[i].status = 0x80000000;
  1508. /* used to be PKT_BUF_SZ now uses skb since we lose some to head room */
  1509. sc->lmc_rxring[i].length = skb_tailroom(skb);
  1510. /* use to be tail which is dumb since you're thinking why write
  1511. * to the end of the packj,et but since there's nothing there tail == data
  1512. */
  1513. sc->lmc_rxring[i].buffer1 = virt_to_bus (skb->data);
  1514. /* This is fair since the structure is static and we have the next address */
  1515. sc->lmc_rxring[i].buffer2 = virt_to_bus (&sc->lmc_rxring[i + 1]);
  1516. }
  1517. /*
  1518. * Sets end of ring
  1519. */
  1520. if (i != 0) {
  1521. sc->lmc_rxring[i - 1].length |= 0x02000000; /* Set end of buffers flag */
  1522. sc->lmc_rxring[i - 1].buffer2 = virt_to_bus(&sc->lmc_rxring[0]); /* Point back to the start */
  1523. }
  1524. LMC_CSR_WRITE (sc, csr_rxlist, virt_to_bus (sc->lmc_rxring)); /* write base address */
  1525. /* Initialize the transmit rings and buffers */
  1526. for (i = 0; i < LMC_TXDESCS; i++)
  1527. {
  1528. if (sc->lmc_txq[i] != NULL){ /* have buffer */
  1529. dev_kfree_skb(sc->lmc_txq[i]); /* free it */
  1530. sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */
  1531. }
  1532. sc->lmc_txq[i] = NULL;
  1533. sc->lmc_txring[i].status = 0x00000000;
  1534. sc->lmc_txring[i].buffer2 = virt_to_bus (&sc->lmc_txring[i + 1]);
  1535. }
  1536. sc->lmc_txring[i - 1].buffer2 = virt_to_bus (&sc->lmc_txring[0]);
  1537. LMC_CSR_WRITE (sc, csr_txlist, virt_to_bus (sc->lmc_txring));
  1538. lmc_trace(sc->lmc_device, "lmc_softreset out");
  1539. }
  1540. void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1541. {
  1542. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in");
  1543. sc->lmc_gpio_io &= ~bits;
  1544. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1545. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out");
  1546. }
  1547. void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1548. {
  1549. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in");
  1550. sc->lmc_gpio_io |= bits;
  1551. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1552. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out");
  1553. }
  1554. void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/
  1555. {
  1556. lmc_trace(sc->lmc_device, "lmc_led_on in");
  1557. if((~sc->lmc_miireg16) & led){ /* Already on! */
  1558. lmc_trace(sc->lmc_device, "lmc_led_on aon out");
  1559. return;
  1560. }
  1561. sc->lmc_miireg16 &= ~led;
  1562. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1563. lmc_trace(sc->lmc_device, "lmc_led_on out");
  1564. }
  1565. void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/
  1566. {
  1567. lmc_trace(sc->lmc_device, "lmc_led_off in");
  1568. if(sc->lmc_miireg16 & led){ /* Already set don't do anything */
  1569. lmc_trace(sc->lmc_device, "lmc_led_off aoff out");
  1570. return;
  1571. }
  1572. sc->lmc_miireg16 |= led;
  1573. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1574. lmc_trace(sc->lmc_device, "lmc_led_off out");
  1575. }
  1576. static void lmc_reset(lmc_softc_t * const sc) /*fold00*/
  1577. {
  1578. lmc_trace(sc->lmc_device, "lmc_reset in");
  1579. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  1580. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1581. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  1582. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1583. /*
  1584. * make some of the GPIO pins be outputs
  1585. */
  1586. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  1587. /*
  1588. * RESET low to force state reset. This also forces
  1589. * the transmitter clock to be internal, but we expect to reset
  1590. * that later anyway.
  1591. */
  1592. sc->lmc_gpio &= ~(LMC_GEP_RESET);
  1593. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  1594. /*
  1595. * hold for more than 10 microseconds
  1596. */
  1597. udelay(50);
  1598. /*
  1599. * stop driving Xilinx-related signals
  1600. */
  1601. lmc_gpio_mkinput(sc, LMC_GEP_RESET);
  1602. /*
  1603. * Call media specific init routine
  1604. */
  1605. sc->lmc_media->init(sc);
  1606. sc->extra_stats.resetCount++;
  1607. lmc_trace(sc->lmc_device, "lmc_reset out");
  1608. }
  1609. static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/
  1610. {
  1611. u32 val;
  1612. lmc_trace(sc->lmc_device, "lmc_dec_reset in");
  1613. /*
  1614. * disable all interrupts
  1615. */
  1616. sc->lmc_intrmask = 0;
  1617. LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
  1618. /*
  1619. * Reset the chip with a software reset command.
  1620. * Wait 10 microseconds (actually 50 PCI cycles but at
  1621. * 33MHz that comes to two microseconds but wait a
  1622. * bit longer anyways)
  1623. */
  1624. LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
  1625. udelay(25);
  1626. #ifdef __sparc__
  1627. sc->lmc_busmode = LMC_CSR_READ(sc, csr_busmode);
  1628. sc->lmc_busmode = 0x00100000;
  1629. sc->lmc_busmode &= ~TULIP_BUSMODE_SWRESET;
  1630. LMC_CSR_WRITE(sc, csr_busmode, sc->lmc_busmode);
  1631. #endif
  1632. sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
  1633. /*
  1634. * We want:
  1635. * no ethernet address in frames we write
  1636. * disable padding (txdesc, padding disable)
  1637. * ignore runt frames (rdes0 bit 15)
  1638. * no receiver watchdog or transmitter jabber timer
  1639. * (csr15 bit 0,14 == 1)
  1640. * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
  1641. */
  1642. sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
  1643. | TULIP_CMD_FULLDUPLEX
  1644. | TULIP_CMD_PASSBADPKT
  1645. | TULIP_CMD_NOHEARTBEAT
  1646. | TULIP_CMD_PORTSELECT
  1647. | TULIP_CMD_RECEIVEALL
  1648. | TULIP_CMD_MUSTBEONE
  1649. );
  1650. sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
  1651. | TULIP_CMD_THRESHOLDCTL
  1652. | TULIP_CMD_STOREFWD
  1653. | TULIP_CMD_TXTHRSHLDCTL
  1654. );
  1655. LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
  1656. /*
  1657. * disable receiver watchdog and transmit jabber
  1658. */
  1659. val = LMC_CSR_READ(sc, csr_sia_general);
  1660. val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
  1661. LMC_CSR_WRITE(sc, csr_sia_general, val);
  1662. lmc_trace(sc->lmc_device, "lmc_dec_reset out");
  1663. }
  1664. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/
  1665. size_t csr_size)
  1666. {
  1667. lmc_trace(sc->lmc_device, "lmc_initcsrs in");
  1668. sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
  1669. sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
  1670. sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
  1671. sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
  1672. sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
  1673. sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
  1674. sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
  1675. sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
  1676. sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
  1677. sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
  1678. sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
  1679. sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
  1680. sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
  1681. sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
  1682. sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
  1683. sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
  1684. lmc_trace(sc->lmc_device, "lmc_initcsrs out");
  1685. }
  1686. static void lmc_driver_timeout(struct net_device *dev)
  1687. {
  1688. lmc_softc_t *sc = dev_to_sc(dev);
  1689. u32 csr6;
  1690. unsigned long flags;
  1691. lmc_trace(dev, "lmc_driver_timeout in");
  1692. spin_lock_irqsave(&sc->lmc_lock, flags);
  1693. printk("%s: Xmitter busy|\n", dev->name);
  1694. sc->extra_stats.tx_tbusy_calls++;
  1695. if (jiffies - dev_trans_start(dev) < TX_TIMEOUT)
  1696. goto bug_out;
  1697. /*
  1698. * Chip seems to have locked up
  1699. * Reset it
  1700. * This whips out all our decriptor
  1701. * table and starts from scartch
  1702. */
  1703. LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO,
  1704. LMC_CSR_READ (sc, csr_status),
  1705. sc->extra_stats.tx_ProcTimeout);
  1706. lmc_running_reset (dev);
  1707. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1708. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1709. lmc_mii_readreg (sc, 0, 16),
  1710. lmc_mii_readreg (sc, 0, 17));
  1711. /* restart the tx processes */
  1712. csr6 = LMC_CSR_READ (sc, csr_command);
  1713. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x0002);
  1714. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x2002);
  1715. /* immediate transmit */
  1716. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1717. sc->lmc_device->stats.tx_errors++;
  1718. sc->extra_stats.tx_ProcTimeout++; /* -baz */
  1719. netif_trans_update(dev); /* prevent tx timeout */
  1720. bug_out:
  1721. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1722. lmc_trace(dev, "lmc_driver_timeout out");
  1723. }