sdio.c 22 KB

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  1. /*
  2. * Copyright (c) 2004-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/mmc/card.h>
  17. #include <linux/mmc/mmc.h>
  18. #include <linux/mmc/host.h>
  19. #include <linux/mmc/sdio_func.h>
  20. #include <linux/mmc/sdio_ids.h>
  21. #include <linux/mmc/sdio.h>
  22. #include <linux/mmc/sd.h>
  23. #include "htc_hif.h"
  24. #include "hif-ops.h"
  25. #include "target.h"
  26. #include "debug.h"
  27. struct ath6kl_sdio {
  28. struct sdio_func *func;
  29. spinlock_t lock;
  30. /* free list */
  31. struct list_head bus_req_freeq;
  32. /* available bus requests */
  33. struct bus_request bus_req[BUS_REQUEST_MAX_NUM];
  34. struct ath6kl *ar;
  35. u8 *dma_buffer;
  36. /* scatter request list head */
  37. struct list_head scat_req;
  38. spinlock_t scat_lock;
  39. bool is_disabled;
  40. atomic_t irq_handling;
  41. const struct sdio_device_id *id;
  42. struct work_struct wr_async_work;
  43. struct list_head wr_asyncq;
  44. spinlock_t wr_async_lock;
  45. };
  46. #define CMD53_ARG_READ 0
  47. #define CMD53_ARG_WRITE 1
  48. #define CMD53_ARG_BLOCK_BASIS 1
  49. #define CMD53_ARG_FIXED_ADDRESS 0
  50. #define CMD53_ARG_INCR_ADDRESS 1
  51. static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar)
  52. {
  53. return ar->hif_priv;
  54. }
  55. /*
  56. * Macro to check if DMA buffer is WORD-aligned and DMA-able.
  57. * Most host controllers assume the buffer is DMA'able and will
  58. * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
  59. * check fails on stack memory.
  60. */
  61. static inline bool buf_needs_bounce(u8 *buf)
  62. {
  63. return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
  64. }
  65. static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar)
  66. {
  67. struct ath6kl_mbox_info *mbox_info = &ar->mbox_info;
  68. /* EP1 has an extended range */
  69. mbox_info->htc_addr = HIF_MBOX_BASE_ADDR;
  70. mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR;
  71. mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH;
  72. mbox_info->block_size = HIF_MBOX_BLOCK_SIZE;
  73. mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR;
  74. mbox_info->gmbox_sz = HIF_GMBOX_WIDTH;
  75. }
  76. static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
  77. u8 mode, u8 opcode, u32 addr,
  78. u16 blksz)
  79. {
  80. *arg = (((rw & 1) << 31) |
  81. ((func & 0x7) << 28) |
  82. ((mode & 1) << 27) |
  83. ((opcode & 1) << 26) |
  84. ((addr & 0x1FFFF) << 9) |
  85. (blksz & 0x1FF));
  86. }
  87. static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
  88. unsigned int address,
  89. unsigned char val)
  90. {
  91. const u8 func = 0;
  92. *arg = ((write & 1) << 31) |
  93. ((func & 0x7) << 28) |
  94. ((raw & 1) << 27) |
  95. (1 << 26) |
  96. ((address & 0x1FFFF) << 9) |
  97. (1 << 8) |
  98. (val & 0xFF);
  99. }
  100. static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
  101. unsigned int address,
  102. unsigned char byte)
  103. {
  104. struct mmc_command io_cmd;
  105. memset(&io_cmd, 0, sizeof(io_cmd));
  106. ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
  107. io_cmd.opcode = SD_IO_RW_DIRECT;
  108. io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
  109. return mmc_wait_for_cmd(card->host, &io_cmd, 0);
  110. }
  111. static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio)
  112. {
  113. struct bus_request *bus_req;
  114. unsigned long flag;
  115. spin_lock_irqsave(&ar_sdio->lock, flag);
  116. if (list_empty(&ar_sdio->bus_req_freeq)) {
  117. spin_unlock_irqrestore(&ar_sdio->lock, flag);
  118. return NULL;
  119. }
  120. bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
  121. struct bus_request, list);
  122. list_del(&bus_req->list);
  123. spin_unlock_irqrestore(&ar_sdio->lock, flag);
  124. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: bus request 0x%p\n", __func__, bus_req);
  125. return bus_req;
  126. }
  127. static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio,
  128. struct bus_request *bus_req)
  129. {
  130. unsigned long flag;
  131. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: bus request 0x%p\n", __func__, bus_req);
  132. spin_lock_irqsave(&ar_sdio->lock, flag);
  133. list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
  134. spin_unlock_irqrestore(&ar_sdio->lock, flag);
  135. }
  136. static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req,
  137. struct mmc_data *data)
  138. {
  139. struct scatterlist *sg;
  140. int i;
  141. data->blksz = HIF_MBOX_BLOCK_SIZE;
  142. data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE;
  143. ath6kl_dbg(ATH6KL_DBG_SCATTER,
  144. "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
  145. (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr,
  146. data->blksz, data->blocks, scat_req->len,
  147. scat_req->scat_entries);
  148. data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE :
  149. MMC_DATA_READ;
  150. /* fill SG entries */
  151. sg = scat_req->sgentries;
  152. sg_init_table(sg, scat_req->scat_entries);
  153. /* assemble SG list */
  154. for (i = 0; i < scat_req->scat_entries; i++, sg++) {
  155. if ((unsigned long)scat_req->scat_list[i].buf & 0x3)
  156. /*
  157. * Some scatter engines can handle unaligned
  158. * buffers, print this as informational only.
  159. */
  160. ath6kl_dbg(ATH6KL_DBG_SCATTER,
  161. "(%s) scatter buffer is unaligned 0x%p\n",
  162. scat_req->req & HIF_WRITE ? "WR" : "RD",
  163. scat_req->scat_list[i].buf);
  164. ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
  165. i, scat_req->scat_list[i].buf,
  166. scat_req->scat_list[i].len);
  167. sg_set_buf(sg, scat_req->scat_list[i].buf,
  168. scat_req->scat_list[i].len);
  169. }
  170. /* set scatter-gather table for request */
  171. data->sg = scat_req->sgentries;
  172. data->sg_len = scat_req->scat_entries;
  173. }
  174. static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio,
  175. struct bus_request *req)
  176. {
  177. struct mmc_request mmc_req;
  178. struct mmc_command cmd;
  179. struct mmc_data data;
  180. struct hif_scatter_req *scat_req;
  181. u8 opcode, rw;
  182. int status;
  183. scat_req = req->scat_req;
  184. memset(&mmc_req, 0, sizeof(struct mmc_request));
  185. memset(&cmd, 0, sizeof(struct mmc_command));
  186. memset(&data, 0, sizeof(struct mmc_data));
  187. ath6kl_sdio_setup_scat_data(scat_req, &data);
  188. opcode = (scat_req->req & HIF_FIXED_ADDRESS) ?
  189. CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS;
  190. rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
  191. /* Fixup the address so that the last byte will fall on MBOX EOM */
  192. if (scat_req->req & HIF_WRITE) {
  193. if (scat_req->addr == HIF_MBOX_BASE_ADDR)
  194. scat_req->addr += HIF_MBOX_WIDTH - scat_req->len;
  195. else
  196. /* Uses extended address range */
  197. scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len;
  198. }
  199. /* set command argument */
  200. ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num,
  201. CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr,
  202. data.blocks);
  203. cmd.opcode = SD_IO_RW_EXTENDED;
  204. cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
  205. mmc_req.cmd = &cmd;
  206. mmc_req.data = &data;
  207. mmc_set_data_timeout(&data, ar_sdio->func->card);
  208. /* synchronous call to process request */
  209. mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req);
  210. status = cmd.error ? cmd.error : data.error;
  211. scat_req->status = status;
  212. if (scat_req->status)
  213. ath6kl_err("Scatter write request failed:%d\n",
  214. scat_req->status);
  215. if (scat_req->req & HIF_ASYNCHRONOUS)
  216. scat_req->complete(ar_sdio->ar->htc_target, scat_req);
  217. return status;
  218. }
  219. static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio,
  220. int n_scat_entry, int n_scat_req,
  221. bool virt_scat)
  222. {
  223. struct hif_scatter_req *s_req;
  224. struct bus_request *bus_req;
  225. int i, scat_req_sz, scat_list_sz, sg_sz = 0;
  226. scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item);
  227. scat_req_sz = sizeof(*s_req) + scat_list_sz;
  228. if (!virt_scat)
  229. sg_sz = sizeof(struct scatterlist) * n_scat_entry;
  230. for (i = 0; i < n_scat_req; i++) {
  231. /* allocate the scatter request */
  232. s_req = kzalloc(scat_req_sz, GFP_KERNEL);
  233. if (!s_req)
  234. return -ENOMEM;
  235. if (sg_sz) {
  236. /* allocate sglist */
  237. s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL);
  238. if (!s_req->sgentries) {
  239. kfree(s_req);
  240. return -ENOMEM;
  241. }
  242. }
  243. /* allocate a bus request for this scatter request */
  244. bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
  245. if (!bus_req) {
  246. kfree(s_req->sgentries);
  247. kfree(s_req);
  248. return -ENOMEM;
  249. }
  250. /* assign the scatter request to this bus request */
  251. bus_req->scat_req = s_req;
  252. s_req->busrequest = bus_req;
  253. /* add it to the scatter pool */
  254. hif_scatter_req_add(ar_sdio->ar, s_req);
  255. }
  256. return 0;
  257. }
  258. static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
  259. u32 len, u32 request)
  260. {
  261. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  262. u8 *tbuf = NULL;
  263. int ret;
  264. bool bounced = false;
  265. if (request & HIF_BLOCK_BASIS)
  266. len = round_down(len, HIF_MBOX_BLOCK_SIZE);
  267. if (buf_needs_bounce(buf)) {
  268. if (!ar_sdio->dma_buffer)
  269. return -ENOMEM;
  270. tbuf = ar_sdio->dma_buffer;
  271. memcpy(tbuf, buf, len);
  272. bounced = true;
  273. } else
  274. tbuf = buf;
  275. sdio_claim_host(ar_sdio->func);
  276. if (request & HIF_WRITE) {
  277. if (addr >= HIF_MBOX_BASE_ADDR &&
  278. addr <= HIF_MBOX_END_ADDR)
  279. addr += (HIF_MBOX_WIDTH - len);
  280. if (addr == HIF_MBOX0_EXT_BASE_ADDR)
  281. addr += HIF_MBOX0_EXT_WIDTH - len;
  282. if (request & HIF_FIXED_ADDRESS)
  283. ret = sdio_writesb(ar_sdio->func, addr, tbuf, len);
  284. else
  285. ret = sdio_memcpy_toio(ar_sdio->func, addr, tbuf, len);
  286. } else {
  287. if (request & HIF_FIXED_ADDRESS)
  288. ret = sdio_readsb(ar_sdio->func, tbuf, addr, len);
  289. else
  290. ret = sdio_memcpy_fromio(ar_sdio->func, tbuf,
  291. addr, len);
  292. if (bounced)
  293. memcpy(buf, tbuf, len);
  294. }
  295. sdio_release_host(ar_sdio->func);
  296. return ret;
  297. }
  298. static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio,
  299. struct bus_request *req)
  300. {
  301. if (req->scat_req)
  302. ath6kl_sdio_scat_rw(ar_sdio, req);
  303. else {
  304. void *context;
  305. int status;
  306. status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address,
  307. req->buffer, req->length,
  308. req->request);
  309. context = req->packet;
  310. ath6kl_sdio_free_bus_req(ar_sdio, req);
  311. ath6kldev_rw_comp_handler(context, status);
  312. }
  313. }
  314. static void ath6kl_sdio_write_async_work(struct work_struct *work)
  315. {
  316. struct ath6kl_sdio *ar_sdio;
  317. unsigned long flags;
  318. struct bus_request *req, *tmp_req;
  319. ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work);
  320. sdio_claim_host(ar_sdio->func);
  321. spin_lock_irqsave(&ar_sdio->wr_async_lock, flags);
  322. list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
  323. list_del(&req->list);
  324. spin_unlock_irqrestore(&ar_sdio->wr_async_lock, flags);
  325. __ath6kl_sdio_write_async(ar_sdio, req);
  326. spin_lock_irqsave(&ar_sdio->wr_async_lock, flags);
  327. }
  328. spin_unlock_irqrestore(&ar_sdio->wr_async_lock, flags);
  329. sdio_release_host(ar_sdio->func);
  330. }
  331. static void ath6kl_sdio_irq_handler(struct sdio_func *func)
  332. {
  333. int status;
  334. struct ath6kl_sdio *ar_sdio;
  335. ar_sdio = sdio_get_drvdata(func);
  336. atomic_set(&ar_sdio->irq_handling, 1);
  337. /*
  338. * Release the host during interrups so we can pick it back up when
  339. * we process commands.
  340. */
  341. sdio_release_host(ar_sdio->func);
  342. status = ath6kldev_intr_bh_handler(ar_sdio->ar);
  343. sdio_claim_host(ar_sdio->func);
  344. atomic_set(&ar_sdio->irq_handling, 0);
  345. WARN_ON(status && status != -ECANCELED);
  346. }
  347. static int ath6kl_sdio_power_on(struct ath6kl_sdio *ar_sdio)
  348. {
  349. struct sdio_func *func = ar_sdio->func;
  350. int ret = 0;
  351. if (!ar_sdio->is_disabled)
  352. return 0;
  353. sdio_claim_host(func);
  354. ret = sdio_enable_func(func);
  355. if (ret) {
  356. ath6kl_err("Unable to enable sdio func: %d)\n", ret);
  357. sdio_release_host(func);
  358. return ret;
  359. }
  360. sdio_release_host(func);
  361. /*
  362. * Wait for hardware to initialise. It should take a lot less than
  363. * 10 ms but let's be conservative here.
  364. */
  365. msleep(10);
  366. ar_sdio->is_disabled = false;
  367. return ret;
  368. }
  369. static int ath6kl_sdio_power_off(struct ath6kl_sdio *ar_sdio)
  370. {
  371. int ret;
  372. if (ar_sdio->is_disabled)
  373. return 0;
  374. /* Disable the card */
  375. sdio_claim_host(ar_sdio->func);
  376. ret = sdio_disable_func(ar_sdio->func);
  377. sdio_release_host(ar_sdio->func);
  378. if (ret)
  379. return ret;
  380. ar_sdio->is_disabled = true;
  381. return ret;
  382. }
  383. static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
  384. u32 length, u32 request,
  385. struct htc_packet *packet)
  386. {
  387. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  388. struct bus_request *bus_req;
  389. unsigned long flags;
  390. bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
  391. if (!bus_req)
  392. return -ENOMEM;
  393. bus_req->address = address;
  394. bus_req->buffer = buffer;
  395. bus_req->length = length;
  396. bus_req->request = request;
  397. bus_req->packet = packet;
  398. spin_lock_irqsave(&ar_sdio->wr_async_lock, flags);
  399. list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
  400. spin_unlock_irqrestore(&ar_sdio->wr_async_lock, flags);
  401. queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
  402. return 0;
  403. }
  404. static void ath6kl_sdio_irq_enable(struct ath6kl *ar)
  405. {
  406. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  407. int ret;
  408. sdio_claim_host(ar_sdio->func);
  409. /* Register the isr */
  410. ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler);
  411. if (ret)
  412. ath6kl_err("Failed to claim sdio irq: %d\n", ret);
  413. sdio_release_host(ar_sdio->func);
  414. }
  415. static void ath6kl_sdio_irq_disable(struct ath6kl *ar)
  416. {
  417. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  418. int ret;
  419. sdio_claim_host(ar_sdio->func);
  420. /* Mask our function IRQ */
  421. while (atomic_read(&ar_sdio->irq_handling)) {
  422. sdio_release_host(ar_sdio->func);
  423. schedule_timeout(HZ / 10);
  424. sdio_claim_host(ar_sdio->func);
  425. }
  426. ret = sdio_release_irq(ar_sdio->func);
  427. if (ret)
  428. ath6kl_err("Failed to release sdio irq: %d\n", ret);
  429. sdio_release_host(ar_sdio->func);
  430. }
  431. static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar)
  432. {
  433. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  434. struct hif_scatter_req *node = NULL;
  435. unsigned long flag;
  436. spin_lock_irqsave(&ar_sdio->scat_lock, flag);
  437. if (!list_empty(&ar_sdio->scat_req)) {
  438. node = list_first_entry(&ar_sdio->scat_req,
  439. struct hif_scatter_req, list);
  440. list_del(&node->list);
  441. }
  442. spin_unlock_irqrestore(&ar_sdio->scat_lock, flag);
  443. return node;
  444. }
  445. static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar,
  446. struct hif_scatter_req *s_req)
  447. {
  448. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  449. unsigned long flag;
  450. spin_lock_irqsave(&ar_sdio->scat_lock, flag);
  451. list_add_tail(&s_req->list, &ar_sdio->scat_req);
  452. spin_unlock_irqrestore(&ar_sdio->scat_lock, flag);
  453. }
  454. /* scatter gather read write request */
  455. static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar,
  456. struct hif_scatter_req *scat_req)
  457. {
  458. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  459. u32 request = scat_req->req;
  460. int status = 0;
  461. unsigned long flags;
  462. if (!scat_req->len)
  463. return -EINVAL;
  464. ath6kl_dbg(ATH6KL_DBG_SCATTER,
  465. "hif-scatter: total len: %d scatter entries: %d\n",
  466. scat_req->len, scat_req->scat_entries);
  467. if (request & HIF_SYNCHRONOUS) {
  468. sdio_claim_host(ar_sdio->func);
  469. status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest);
  470. sdio_release_host(ar_sdio->func);
  471. } else {
  472. spin_lock_irqsave(&ar_sdio->wr_async_lock, flags);
  473. list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq);
  474. spin_unlock_irqrestore(&ar_sdio->wr_async_lock, flags);
  475. queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
  476. }
  477. return status;
  478. }
  479. /* clean up scatter support */
  480. static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar)
  481. {
  482. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  483. struct hif_scatter_req *s_req, *tmp_req;
  484. unsigned long flag;
  485. /* empty the free list */
  486. spin_lock_irqsave(&ar_sdio->scat_lock, flag);
  487. list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) {
  488. list_del(&s_req->list);
  489. spin_unlock_irqrestore(&ar_sdio->scat_lock, flag);
  490. if (s_req->busrequest)
  491. ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest);
  492. kfree(s_req->virt_dma_buf);
  493. kfree(s_req->sgentries);
  494. kfree(s_req);
  495. spin_lock_irqsave(&ar_sdio->scat_lock, flag);
  496. }
  497. spin_unlock_irqrestore(&ar_sdio->scat_lock, flag);
  498. }
  499. /* setup of HIF scatter resources */
  500. static int ath6kl_sdio_enable_scatter(struct ath6kl *ar,
  501. struct hif_dev_scat_sup_info *pinfo)
  502. {
  503. struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
  504. int ret = 0;
  505. /* check if host supports scatter and it meets our requirements */
  506. if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
  507. ath6kl_err("hif-scatter: host only supports scatter of : %d entries, need: %d\n",
  508. ar_sdio->func->card->host->max_segs,
  509. MAX_SCATTER_ENTRIES_PER_REQ);
  510. return -EINVAL;
  511. }
  512. ath6kl_dbg(ATH6KL_DBG_ANY,
  513. "hif-scatter enabled: max scatter req : %d entries: %d\n",
  514. MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ);
  515. ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
  516. MAX_SCATTER_ENTRIES_PER_REQ,
  517. MAX_SCATTER_REQUESTS, 0);
  518. if (ret) {
  519. ath6kl_err("hif-scatter: failed to alloc scatter resources !\n");
  520. ath6kl_sdio_cleanup_scatter(ar);
  521. return ret;
  522. }
  523. pinfo->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ;
  524. pinfo->max_xfer_szper_scatreq = MAX_SCATTER_REQ_TRANSFER_SIZE;
  525. return 0;
  526. }
  527. static const struct ath6kl_hif_ops ath6kl_sdio_ops = {
  528. .read_write_sync = ath6kl_sdio_read_write_sync,
  529. .write_async = ath6kl_sdio_write_async,
  530. .irq_enable = ath6kl_sdio_irq_enable,
  531. .irq_disable = ath6kl_sdio_irq_disable,
  532. .scatter_req_get = ath6kl_sdio_scatter_req_get,
  533. .scatter_req_add = ath6kl_sdio_scatter_req_add,
  534. .enable_scatter = ath6kl_sdio_enable_scatter,
  535. .scat_req_rw = ath6kl_sdio_async_rw_scatter,
  536. .cleanup_scatter = ath6kl_sdio_cleanup_scatter,
  537. };
  538. static int ath6kl_sdio_probe(struct sdio_func *func,
  539. const struct sdio_device_id *id)
  540. {
  541. int ret;
  542. struct ath6kl_sdio *ar_sdio;
  543. struct ath6kl *ar;
  544. int count;
  545. ath6kl_dbg(ATH6KL_DBG_TRC,
  546. "%s: func: 0x%X, vendor id: 0x%X, dev id: 0x%X, block size: 0x%X/0x%X\n",
  547. __func__, func->num, func->vendor,
  548. func->device, func->max_blksize, func->cur_blksize);
  549. ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL);
  550. if (!ar_sdio)
  551. return -ENOMEM;
  552. ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
  553. if (!ar_sdio->dma_buffer) {
  554. ret = -ENOMEM;
  555. goto err_hif;
  556. }
  557. ar_sdio->func = func;
  558. sdio_set_drvdata(func, ar_sdio);
  559. ar_sdio->id = id;
  560. ar_sdio->is_disabled = true;
  561. spin_lock_init(&ar_sdio->lock);
  562. spin_lock_init(&ar_sdio->scat_lock);
  563. spin_lock_init(&ar_sdio->wr_async_lock);
  564. INIT_LIST_HEAD(&ar_sdio->scat_req);
  565. INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
  566. INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
  567. INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work);
  568. for (count = 0; count < BUS_REQUEST_MAX_NUM; count++)
  569. ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]);
  570. ar = ath6kl_core_alloc(&ar_sdio->func->dev);
  571. if (!ar) {
  572. ath6kl_err("Failed to alloc ath6kl core\n");
  573. ret = -ENOMEM;
  574. goto err_dma;
  575. }
  576. ar_sdio->ar = ar;
  577. ar->hif_priv = ar_sdio;
  578. ar->hif_ops = &ath6kl_sdio_ops;
  579. ath6kl_sdio_set_mbox_info(ar);
  580. sdio_claim_host(func);
  581. if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >=
  582. MANUFACTURER_ID_AR6003_BASE) {
  583. /* enable 4-bit ASYNC interrupt on AR6003 or later */
  584. ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card,
  585. CCCR_SDIO_IRQ_MODE_REG,
  586. SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
  587. if (ret) {
  588. ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
  589. ret);
  590. sdio_release_host(func);
  591. goto err_dma;
  592. }
  593. ath6kl_dbg(ATH6KL_DBG_TRC, "4-bit async irq mode enabled\n");
  594. }
  595. /* give us some time to enable, in ms */
  596. func->enable_timeout = 100;
  597. sdio_release_host(func);
  598. ret = ath6kl_sdio_power_on(ar_sdio);
  599. if (ret)
  600. goto err_dma;
  601. sdio_claim_host(func);
  602. ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
  603. if (ret) {
  604. ath6kl_err("Set sdio block size %d failed: %d)\n",
  605. HIF_MBOX_BLOCK_SIZE, ret);
  606. sdio_release_host(func);
  607. goto err_off;
  608. }
  609. sdio_release_host(func);
  610. ret = ath6kl_core_init(ar);
  611. if (ret) {
  612. ath6kl_err("Failed to init ath6kl core\n");
  613. goto err_off;
  614. }
  615. return ret;
  616. err_off:
  617. ath6kl_sdio_power_off(ar_sdio);
  618. err_dma:
  619. kfree(ar_sdio->dma_buffer);
  620. err_hif:
  621. kfree(ar_sdio);
  622. return ret;
  623. }
  624. static void ath6kl_sdio_remove(struct sdio_func *func)
  625. {
  626. struct ath6kl_sdio *ar_sdio;
  627. ar_sdio = sdio_get_drvdata(func);
  628. ath6kl_stop_txrx(ar_sdio->ar);
  629. cancel_work_sync(&ar_sdio->wr_async_work);
  630. ath6kl_unavail_ev(ar_sdio->ar);
  631. ath6kl_sdio_power_off(ar_sdio);
  632. kfree(ar_sdio->dma_buffer);
  633. kfree(ar_sdio);
  634. }
  635. static const struct sdio_device_id ath6kl_sdio_devices[] = {
  636. {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))},
  637. {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))},
  638. {},
  639. };
  640. MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices);
  641. static struct sdio_driver ath6kl_sdio_driver = {
  642. .name = "ath6kl_sdio",
  643. .id_table = ath6kl_sdio_devices,
  644. .probe = ath6kl_sdio_probe,
  645. .remove = ath6kl_sdio_remove,
  646. };
  647. static int __init ath6kl_sdio_init(void)
  648. {
  649. int ret;
  650. ret = sdio_register_driver(&ath6kl_sdio_driver);
  651. if (ret)
  652. ath6kl_err("sdio driver registration failed: %d\n", ret);
  653. return ret;
  654. }
  655. static void __exit ath6kl_sdio_exit(void)
  656. {
  657. sdio_unregister_driver(&ath6kl_sdio_driver);
  658. }
  659. module_init(ath6kl_sdio_init);
  660. module_exit(ath6kl_sdio_exit);
  661. MODULE_AUTHOR("Atheros Communications, Inc.");
  662. MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
  663. MODULE_LICENSE("Dual BSD/GPL");
  664. MODULE_FIRMWARE(AR6003_REV2_OTP_FILE);
  665. MODULE_FIRMWARE(AR6003_REV2_FIRMWARE_FILE);
  666. MODULE_FIRMWARE(AR6003_REV2_PATCH_FILE);
  667. MODULE_FIRMWARE(AR6003_REV2_BOARD_DATA_FILE);
  668. MODULE_FIRMWARE(AR6003_REV2_DEFAULT_BOARD_DATA_FILE);
  669. MODULE_FIRMWARE(AR6003_REV3_OTP_FILE);
  670. MODULE_FIRMWARE(AR6003_REV3_FIRMWARE_FILE);
  671. MODULE_FIRMWARE(AR6003_REV3_PATCH_FILE);
  672. MODULE_FIRMWARE(AR6003_REV3_BOARD_DATA_FILE);
  673. MODULE_FIRMWARE(AR6003_REV3_DEFAULT_BOARD_DATA_FILE);