t2081si-post.dtsi 11 KB

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  1. /*
  2. * T2081 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2013 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &ifc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,ifc", "simple-bus";
  38. interrupts = <25 2 0 0>;
  39. };
  40. /* controller at 0x240000 */
  41. &pci0 {
  42. compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. interrupts = <20 2 0 0>;
  48. fsl,iommu-parent = <&pamu0>;
  49. pcie@0 {
  50. reg = <0 0 0 0 0>;
  51. #interrupt-cells = <1>;
  52. #size-cells = <2>;
  53. #address-cells = <3>;
  54. device_type = "pci";
  55. interrupts = <20 2 0 0>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0 0 1 &mpic 40 1 0 0
  60. 0000 0 0 2 &mpic 1 1 0 0
  61. 0000 0 0 3 &mpic 2 1 0 0
  62. 0000 0 0 4 &mpic 3 1 0 0
  63. >;
  64. };
  65. };
  66. /* controller at 0x250000 */
  67. &pci1 {
  68. compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
  69. device_type = "pci";
  70. #size-cells = <2>;
  71. #address-cells = <3>;
  72. bus-range = <0 0xff>;
  73. interrupts = <21 2 0 0>;
  74. fsl,iommu-parent = <&pamu0>;
  75. pcie@0 {
  76. reg = <0 0 0 0 0>;
  77. #interrupt-cells = <1>;
  78. #size-cells = <2>;
  79. #address-cells = <3>;
  80. device_type = "pci";
  81. interrupts = <21 2 0 0>;
  82. interrupt-map-mask = <0xf800 0 0 7>;
  83. interrupt-map = <
  84. /* IDSEL 0x0 */
  85. 0000 0 0 1 &mpic 41 1 0 0
  86. 0000 0 0 2 &mpic 5 1 0 0
  87. 0000 0 0 3 &mpic 6 1 0 0
  88. 0000 0 0 4 &mpic 7 1 0 0
  89. >;
  90. };
  91. };
  92. /* controller at 0x260000 */
  93. &pci2 {
  94. compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
  95. device_type = "pci";
  96. #size-cells = <2>;
  97. #address-cells = <3>;
  98. bus-range = <0x0 0xff>;
  99. interrupts = <22 2 0 0>;
  100. fsl,iommu-parent = <&pamu0>;
  101. pcie@0 {
  102. reg = <0 0 0 0 0>;
  103. #interrupt-cells = <1>;
  104. #size-cells = <2>;
  105. #address-cells = <3>;
  106. device_type = "pci";
  107. interrupts = <22 2 0 0>;
  108. interrupt-map-mask = <0xf800 0 0 7>;
  109. interrupt-map = <
  110. /* IDSEL 0x0 */
  111. 0000 0 0 1 &mpic 42 1 0 0
  112. 0000 0 0 2 &mpic 9 1 0 0
  113. 0000 0 0 3 &mpic 10 1 0 0
  114. 0000 0 0 4 &mpic 11 1 0 0
  115. >;
  116. };
  117. };
  118. /* controller at 0x270000 */
  119. &pci3 {
  120. compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
  121. device_type = "pci";
  122. #size-cells = <2>;
  123. #address-cells = <3>;
  124. bus-range = <0x0 0xff>;
  125. interrupts = <23 2 0 0>;
  126. fsl,iommu-parent = <&pamu0>;
  127. pcie@0 {
  128. reg = <0 0 0 0 0>;
  129. #interrupt-cells = <1>;
  130. #size-cells = <2>;
  131. #address-cells = <3>;
  132. device_type = "pci";
  133. interrupts = <23 2 0 0>;
  134. interrupt-map-mask = <0xf800 0 0 7>;
  135. interrupt-map = <
  136. /* IDSEL 0x0 */
  137. 0000 0 0 1 &mpic 43 1 0 0
  138. 0000 0 0 2 &mpic 0 1 0 0
  139. 0000 0 0 3 &mpic 4 1 0 0
  140. 0000 0 0 4 &mpic 8 1 0 0
  141. >;
  142. };
  143. };
  144. &dcsr {
  145. #address-cells = <1>;
  146. #size-cells = <1>;
  147. compatible = "fsl,dcsr", "simple-bus";
  148. dcsr-epu@0 {
  149. compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu";
  150. interrupts = <52 2 0 0
  151. 84 2 0 0
  152. 85 2 0 0
  153. 94 2 0 0
  154. 95 2 0 0>;
  155. reg = <0x0 0x1000>;
  156. };
  157. dcsr-npc {
  158. compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc";
  159. reg = <0x1000 0x1000 0x1002000 0x10000>;
  160. };
  161. dcsr-nxc@2000 {
  162. compatible = "fsl,dcsr-nxc";
  163. reg = <0x2000 0x1000>;
  164. };
  165. dcsr-corenet {
  166. compatible = "fsl,dcsr-corenet";
  167. reg = <0x8000 0x1000 0x1A000 0x1000>;
  168. };
  169. dcsr-ocn@11000 {
  170. compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn";
  171. reg = <0x11000 0x1000>;
  172. };
  173. dcsr-ddr@12000 {
  174. compatible = "fsl,dcsr-ddr";
  175. dev-handle = <&ddr1>;
  176. reg = <0x12000 0x1000>;
  177. };
  178. dcsr-nal@18000 {
  179. compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal";
  180. reg = <0x18000 0x1000>;
  181. };
  182. dcsr-rcpm@22000 {
  183. compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm";
  184. reg = <0x22000 0x1000>;
  185. };
  186. dcsr-snpc@30000 {
  187. compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
  188. reg = <0x30000 0x1000 0x1022000 0x10000>;
  189. };
  190. dcsr-snpc@31000 {
  191. compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
  192. reg = <0x31000 0x1000 0x1042000 0x10000>;
  193. };
  194. dcsr-snpc@32000 {
  195. compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
  196. reg = <0x32000 0x1000 0x1062000 0x10000>;
  197. };
  198. dcsr-cpu-sb-proxy@100000 {
  199. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  200. cpu-handle = <&cpu0>;
  201. reg = <0x100000 0x1000 0x101000 0x1000>;
  202. };
  203. dcsr-cpu-sb-proxy@108000 {
  204. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  205. cpu-handle = <&cpu1>;
  206. reg = <0x108000 0x1000 0x109000 0x1000>;
  207. };
  208. dcsr-cpu-sb-proxy@110000 {
  209. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  210. cpu-handle = <&cpu2>;
  211. reg = <0x110000 0x1000 0x111000 0x1000>;
  212. };
  213. dcsr-cpu-sb-proxy@118000 {
  214. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  215. cpu-handle = <&cpu3>;
  216. reg = <0x118000 0x1000 0x119000 0x1000>;
  217. };
  218. };
  219. &soc {
  220. #address-cells = <1>;
  221. #size-cells = <1>;
  222. device_type = "soc";
  223. compatible = "simple-bus";
  224. soc-sram-error {
  225. compatible = "fsl,soc-sram-error";
  226. interrupts = <16 2 1 29>;
  227. };
  228. corenet-law@0 {
  229. compatible = "fsl,corenet-law";
  230. reg = <0x0 0x1000>;
  231. fsl,num-laws = <32>;
  232. };
  233. ddr1: memory-controller@8000 {
  234. compatible = "fsl,qoriq-memory-controller-v4.7",
  235. "fsl,qoriq-memory-controller";
  236. reg = <0x8000 0x1000>;
  237. interrupts = <16 2 1 23>;
  238. };
  239. cpc: l3-cache-controller@10000 {
  240. compatible = "fsl,t2080-l3-cache-controller", "cache";
  241. reg = <0x10000 0x1000
  242. 0x11000 0x1000
  243. 0x12000 0x1000>;
  244. interrupts = <16 2 1 27
  245. 16 2 1 26
  246. 16 2 1 25>;
  247. };
  248. corenet-cf@18000 {
  249. compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
  250. reg = <0x18000 0x1000>;
  251. interrupts = <16 2 1 31>;
  252. fsl,ccf-num-csdids = <32>;
  253. fsl,ccf-num-snoopids = <32>;
  254. };
  255. iommu@20000 {
  256. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  257. reg = <0x20000 0x3000>;
  258. fsl,portid-mapping = <0x8000>;
  259. ranges = <0 0x20000 0x3000>;
  260. #address-cells = <1>;
  261. #size-cells = <1>;
  262. interrupts = <
  263. 24 2 0 0
  264. 16 2 1 30>;
  265. pamu0: pamu@0 {
  266. reg = <0 0x1000>;
  267. fsl,primary-cache-geometry = <32 1>;
  268. fsl,secondary-cache-geometry = <128 2>;
  269. };
  270. pamu1: pamu@1000 {
  271. reg = <0x1000 0x1000>;
  272. fsl,primary-cache-geometry = <32 1>;
  273. fsl,secondary-cache-geometry = <128 2>;
  274. };
  275. pamu2: pamu@2000 {
  276. reg = <0x2000 0x1000>;
  277. fsl,primary-cache-geometry = <32 1>;
  278. fsl,secondary-cache-geometry = <128 2>;
  279. };
  280. };
  281. /include/ "qoriq-mpic4.3.dtsi"
  282. guts: global-utilities@e0000 {
  283. compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0";
  284. reg = <0xe0000 0xe00>;
  285. fsl,has-rstcr;
  286. fsl,liodn-bits = <12>;
  287. };
  288. /include/ "qoriq-clockgen2.dtsi"
  289. global-utilities@e1000 {
  290. compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
  291. mux0: mux0@0 {
  292. #clock-cells = <0>;
  293. reg = <0x0 4>;
  294. compatible = "fsl,qoriq-core-mux-2.0";
  295. clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
  296. <&pll1 0>, <&pll1 1>, <&pll1 2>;
  297. clock-names = "pll0", "pll0-div2", "pll1-div4",
  298. "pll1", "pll1-div2", "pll1-div4";
  299. clock-output-names = "cmux0";
  300. };
  301. mux1: mux1@20 {
  302. #clock-cells = <0>;
  303. reg = <0x20 4>;
  304. compatible = "fsl,qoriq-core-mux-2.0";
  305. clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
  306. <&pll1 0>, <&pll1 1>, <&pll1 2>;
  307. clock-names = "pll0", "pll0-div2", "pll1-div4",
  308. "pll1", "pll1-div2", "pll1-div4";
  309. clock-output-names = "cmux1";
  310. };
  311. };
  312. rcpm: global-utilities@e2000 {
  313. compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0";
  314. reg = <0xe2000 0x1000>;
  315. };
  316. sfp: sfp@e8000 {
  317. compatible = "fsl,t2080-sfp";
  318. reg = <0xe8000 0x1000>;
  319. };
  320. serdes: serdes@ea000 {
  321. compatible = "fsl,t2080-serdes";
  322. reg = <0xea000 0x4000>;
  323. };
  324. /include/ "elo3-dma-0.dtsi"
  325. dma@100300 {
  326. fsl,iommu-parent = <&pamu0>;
  327. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  328. };
  329. /include/ "elo3-dma-1.dtsi"
  330. dma@101300 {
  331. fsl,iommu-parent = <&pamu0>;
  332. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  333. };
  334. /include/ "elo3-dma-2.dtsi"
  335. dma@102300 {
  336. fsl,iommu-parent = <&pamu0>;
  337. fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */
  338. };
  339. /include/ "qoriq-espi-0.dtsi"
  340. spi@110000 {
  341. fsl,espi-num-chipselects = <4>;
  342. };
  343. /include/ "qoriq-esdhc-0.dtsi"
  344. sdhc@114000 {
  345. compatible = "fsl,t2080-esdhc", "fsl,esdhc";
  346. fsl,iommu-parent = <&pamu1>;
  347. fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */
  348. sdhci,auto-cmd12;
  349. };
  350. /include/ "qoriq-i2c-0.dtsi"
  351. /include/ "qoriq-i2c-1.dtsi"
  352. /include/ "qoriq-duart-0.dtsi"
  353. /include/ "qoriq-duart-1.dtsi"
  354. /include/ "qoriq-gpio-0.dtsi"
  355. /include/ "qoriq-gpio-1.dtsi"
  356. /include/ "qoriq-gpio-2.dtsi"
  357. /include/ "qoriq-gpio-3.dtsi"
  358. /include/ "qoriq-usb2-mph-0.dtsi"
  359. usb0: usb@210000 {
  360. compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
  361. fsl,iommu-parent = <&pamu1>;
  362. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  363. phy_type = "utmi";
  364. port0;
  365. };
  366. /include/ "qoriq-usb2-dr-0.dtsi"
  367. usb1: usb@211000 {
  368. compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
  369. fsl,iommu-parent = <&pamu1>;
  370. fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
  371. dr_mode = "host";
  372. phy_type = "utmi";
  373. };
  374. /include/ "qoriq-sec5.2-0.dtsi"
  375. L2_1: l2-cache-controller@c20000 {
  376. /* Cluster 0 L2 cache */
  377. compatible = "fsl,t2080-l2-cache-controller";
  378. reg = <0xc20000 0x40000>;
  379. next-level-cache = <&cpc>;
  380. };
  381. };