nicvf_main.c 51 KB

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  1. /*
  2. * Copyright (C) 2015 Cavium, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of version 2 of the GNU General Public License
  6. * as published by the Free Software Foundation.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/pci.h>
  11. #include <linux/netdevice.h>
  12. #include <linux/if_vlan.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/ethtool.h>
  15. #include <linux/log2.h>
  16. #include <linux/prefetch.h>
  17. #include <linux/irq.h>
  18. #include <linux/iommu.h>
  19. #include <linux/bpf.h>
  20. #include <linux/bpf_trace.h>
  21. #include <linux/filter.h>
  22. #include "nic_reg.h"
  23. #include "nic.h"
  24. #include "nicvf_queues.h"
  25. #include "thunder_bgx.h"
  26. #define DRV_NAME "thunder-nicvf"
  27. #define DRV_VERSION "1.0"
  28. /* Supported devices */
  29. static const struct pci_device_id nicvf_id_table[] = {
  30. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  31. PCI_DEVICE_ID_THUNDER_NIC_VF,
  32. PCI_VENDOR_ID_CAVIUM,
  33. PCI_SUBSYS_DEVID_88XX_NIC_VF) },
  34. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  35. PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,
  36. PCI_VENDOR_ID_CAVIUM,
  37. PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF) },
  38. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  39. PCI_DEVICE_ID_THUNDER_NIC_VF,
  40. PCI_VENDOR_ID_CAVIUM,
  41. PCI_SUBSYS_DEVID_81XX_NIC_VF) },
  42. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  43. PCI_DEVICE_ID_THUNDER_NIC_VF,
  44. PCI_VENDOR_ID_CAVIUM,
  45. PCI_SUBSYS_DEVID_83XX_NIC_VF) },
  46. { 0, } /* end of table */
  47. };
  48. MODULE_AUTHOR("Sunil Goutham");
  49. MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver");
  50. MODULE_LICENSE("GPL v2");
  51. MODULE_VERSION(DRV_VERSION);
  52. MODULE_DEVICE_TABLE(pci, nicvf_id_table);
  53. static int debug = 0x00;
  54. module_param(debug, int, 0644);
  55. MODULE_PARM_DESC(debug, "Debug message level bitmap");
  56. static int cpi_alg = CPI_ALG_NONE;
  57. module_param(cpi_alg, int, S_IRUGO);
  58. MODULE_PARM_DESC(cpi_alg,
  59. "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
  60. struct nicvf_xdp_tx {
  61. u64 dma_addr;
  62. u8 qidx;
  63. };
  64. static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx)
  65. {
  66. if (nic->sqs_mode)
  67. return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS);
  68. else
  69. return qidx;
  70. }
  71. /* The Cavium ThunderX network controller can *only* be found in SoCs
  72. * containing the ThunderX ARM64 CPU implementation. All accesses to the device
  73. * registers on this platform are implicitly strongly ordered with respect
  74. * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
  75. * with no memory barriers in this driver. The readq()/writeq() functions add
  76. * explicit ordering operation which in this case are redundant, and only
  77. * add overhead.
  78. */
  79. /* Register read/write APIs */
  80. void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val)
  81. {
  82. writeq_relaxed(val, nic->reg_base + offset);
  83. }
  84. u64 nicvf_reg_read(struct nicvf *nic, u64 offset)
  85. {
  86. return readq_relaxed(nic->reg_base + offset);
  87. }
  88. void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
  89. u64 qidx, u64 val)
  90. {
  91. void __iomem *addr = nic->reg_base + offset;
  92. writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));
  93. }
  94. u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx)
  95. {
  96. void __iomem *addr = nic->reg_base + offset;
  97. return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
  98. }
  99. /* VF -> PF mailbox communication */
  100. static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx)
  101. {
  102. u64 *msg = (u64 *)mbx;
  103. nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]);
  104. nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]);
  105. }
  106. int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx)
  107. {
  108. int timeout = NIC_MBOX_MSG_TIMEOUT;
  109. int sleep = 10;
  110. nic->pf_acked = false;
  111. nic->pf_nacked = false;
  112. nicvf_write_to_mbx(nic, mbx);
  113. /* Wait for previous message to be acked, timeout 2sec */
  114. while (!nic->pf_acked) {
  115. if (nic->pf_nacked) {
  116. netdev_err(nic->netdev,
  117. "PF NACK to mbox msg 0x%02x from VF%d\n",
  118. (mbx->msg.msg & 0xFF), nic->vf_id);
  119. return -EINVAL;
  120. }
  121. msleep(sleep);
  122. if (nic->pf_acked)
  123. break;
  124. timeout -= sleep;
  125. if (!timeout) {
  126. netdev_err(nic->netdev,
  127. "PF didn't ACK to mbox msg 0x%02x from VF%d\n",
  128. (mbx->msg.msg & 0xFF), nic->vf_id);
  129. return -EBUSY;
  130. }
  131. }
  132. return 0;
  133. }
  134. /* Checks if VF is able to comminicate with PF
  135. * and also gets the VNIC number this VF is associated to.
  136. */
  137. static int nicvf_check_pf_ready(struct nicvf *nic)
  138. {
  139. union nic_mbx mbx = {};
  140. mbx.msg.msg = NIC_MBOX_MSG_READY;
  141. if (nicvf_send_msg_to_pf(nic, &mbx)) {
  142. netdev_err(nic->netdev,
  143. "PF didn't respond to READY msg\n");
  144. return 0;
  145. }
  146. return 1;
  147. }
  148. static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx)
  149. {
  150. if (bgx->rx)
  151. nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats;
  152. else
  153. nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats;
  154. }
  155. static void nicvf_handle_mbx_intr(struct nicvf *nic)
  156. {
  157. union nic_mbx mbx = {};
  158. u64 *mbx_data;
  159. u64 mbx_addr;
  160. int i;
  161. mbx_addr = NIC_VF_PF_MAILBOX_0_1;
  162. mbx_data = (u64 *)&mbx;
  163. for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
  164. *mbx_data = nicvf_reg_read(nic, mbx_addr);
  165. mbx_data++;
  166. mbx_addr += sizeof(u64);
  167. }
  168. netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg);
  169. switch (mbx.msg.msg) {
  170. case NIC_MBOX_MSG_READY:
  171. nic->pf_acked = true;
  172. nic->vf_id = mbx.nic_cfg.vf_id & 0x7F;
  173. nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F;
  174. nic->node = mbx.nic_cfg.node_id;
  175. if (!nic->set_mac_pending)
  176. ether_addr_copy(nic->netdev->dev_addr,
  177. mbx.nic_cfg.mac_addr);
  178. nic->sqs_mode = mbx.nic_cfg.sqs_mode;
  179. nic->loopback_supported = mbx.nic_cfg.loopback_supported;
  180. nic->link_up = false;
  181. nic->duplex = 0;
  182. nic->speed = 0;
  183. break;
  184. case NIC_MBOX_MSG_ACK:
  185. nic->pf_acked = true;
  186. break;
  187. case NIC_MBOX_MSG_NACK:
  188. nic->pf_nacked = true;
  189. break;
  190. case NIC_MBOX_MSG_RSS_SIZE:
  191. nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size;
  192. nic->pf_acked = true;
  193. break;
  194. case NIC_MBOX_MSG_BGX_STATS:
  195. nicvf_read_bgx_stats(nic, &mbx.bgx_stats);
  196. nic->pf_acked = true;
  197. break;
  198. case NIC_MBOX_MSG_BGX_LINK_CHANGE:
  199. nic->pf_acked = true;
  200. nic->link_up = mbx.link_status.link_up;
  201. nic->duplex = mbx.link_status.duplex;
  202. nic->speed = mbx.link_status.speed;
  203. nic->mac_type = mbx.link_status.mac_type;
  204. if (nic->link_up) {
  205. netdev_info(nic->netdev, "Link is Up %d Mbps %s duplex\n",
  206. nic->speed,
  207. nic->duplex == DUPLEX_FULL ?
  208. "Full" : "Half");
  209. netif_carrier_on(nic->netdev);
  210. netif_tx_start_all_queues(nic->netdev);
  211. } else {
  212. netdev_info(nic->netdev, "Link is Down\n");
  213. netif_carrier_off(nic->netdev);
  214. netif_tx_stop_all_queues(nic->netdev);
  215. }
  216. break;
  217. case NIC_MBOX_MSG_ALLOC_SQS:
  218. nic->sqs_count = mbx.sqs_alloc.qs_count;
  219. nic->pf_acked = true;
  220. break;
  221. case NIC_MBOX_MSG_SNICVF_PTR:
  222. /* Primary VF: make note of secondary VF's pointer
  223. * to be used while packet transmission.
  224. */
  225. nic->snicvf[mbx.nicvf.sqs_id] =
  226. (struct nicvf *)mbx.nicvf.nicvf;
  227. nic->pf_acked = true;
  228. break;
  229. case NIC_MBOX_MSG_PNICVF_PTR:
  230. /* Secondary VF/Qset: make note of primary VF's pointer
  231. * to be used while packet reception, to handover packet
  232. * to primary VF's netdev.
  233. */
  234. nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf;
  235. nic->pf_acked = true;
  236. break;
  237. case NIC_MBOX_MSG_PFC:
  238. nic->pfc.autoneg = mbx.pfc.autoneg;
  239. nic->pfc.fc_rx = mbx.pfc.fc_rx;
  240. nic->pfc.fc_tx = mbx.pfc.fc_tx;
  241. nic->pf_acked = true;
  242. break;
  243. default:
  244. netdev_err(nic->netdev,
  245. "Invalid message from PF, msg 0x%x\n", mbx.msg.msg);
  246. break;
  247. }
  248. nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0);
  249. }
  250. static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev)
  251. {
  252. union nic_mbx mbx = {};
  253. mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
  254. mbx.mac.vf_id = nic->vf_id;
  255. ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr);
  256. return nicvf_send_msg_to_pf(nic, &mbx);
  257. }
  258. static void nicvf_config_cpi(struct nicvf *nic)
  259. {
  260. union nic_mbx mbx = {};
  261. mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG;
  262. mbx.cpi_cfg.vf_id = nic->vf_id;
  263. mbx.cpi_cfg.cpi_alg = nic->cpi_alg;
  264. mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt;
  265. nicvf_send_msg_to_pf(nic, &mbx);
  266. }
  267. static void nicvf_get_rss_size(struct nicvf *nic)
  268. {
  269. union nic_mbx mbx = {};
  270. mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
  271. mbx.rss_size.vf_id = nic->vf_id;
  272. nicvf_send_msg_to_pf(nic, &mbx);
  273. }
  274. void nicvf_config_rss(struct nicvf *nic)
  275. {
  276. union nic_mbx mbx = {};
  277. struct nicvf_rss_info *rss = &nic->rss_info;
  278. int ind_tbl_len = rss->rss_size;
  279. int i, nextq = 0;
  280. mbx.rss_cfg.vf_id = nic->vf_id;
  281. mbx.rss_cfg.hash_bits = rss->hash_bits;
  282. while (ind_tbl_len) {
  283. mbx.rss_cfg.tbl_offset = nextq;
  284. mbx.rss_cfg.tbl_len = min(ind_tbl_len,
  285. RSS_IND_TBL_LEN_PER_MBX_MSG);
  286. mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ?
  287. NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG;
  288. for (i = 0; i < mbx.rss_cfg.tbl_len; i++)
  289. mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++];
  290. nicvf_send_msg_to_pf(nic, &mbx);
  291. ind_tbl_len -= mbx.rss_cfg.tbl_len;
  292. }
  293. }
  294. void nicvf_set_rss_key(struct nicvf *nic)
  295. {
  296. struct nicvf_rss_info *rss = &nic->rss_info;
  297. u64 key_addr = NIC_VNIC_RSS_KEY_0_4;
  298. int idx;
  299. for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
  300. nicvf_reg_write(nic, key_addr, rss->key[idx]);
  301. key_addr += sizeof(u64);
  302. }
  303. }
  304. static int nicvf_rss_init(struct nicvf *nic)
  305. {
  306. struct nicvf_rss_info *rss = &nic->rss_info;
  307. int idx;
  308. nicvf_get_rss_size(nic);
  309. if (cpi_alg != CPI_ALG_NONE) {
  310. rss->enable = false;
  311. rss->hash_bits = 0;
  312. return 0;
  313. }
  314. rss->enable = true;
  315. netdev_rss_key_fill(rss->key, RSS_HASH_KEY_SIZE * sizeof(u64));
  316. nicvf_set_rss_key(nic);
  317. rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA;
  318. nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg);
  319. rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size));
  320. for (idx = 0; idx < rss->rss_size; idx++)
  321. rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx,
  322. nic->rx_queues);
  323. nicvf_config_rss(nic);
  324. return 1;
  325. }
  326. /* Request PF to allocate additional Qsets */
  327. static void nicvf_request_sqs(struct nicvf *nic)
  328. {
  329. union nic_mbx mbx = {};
  330. int sqs;
  331. int sqs_count = nic->sqs_count;
  332. int rx_queues = 0, tx_queues = 0;
  333. /* Only primary VF should request */
  334. if (nic->sqs_mode || !nic->sqs_count)
  335. return;
  336. mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
  337. mbx.sqs_alloc.vf_id = nic->vf_id;
  338. mbx.sqs_alloc.qs_count = nic->sqs_count;
  339. if (nicvf_send_msg_to_pf(nic, &mbx)) {
  340. /* No response from PF */
  341. nic->sqs_count = 0;
  342. return;
  343. }
  344. /* Return if no Secondary Qsets available */
  345. if (!nic->sqs_count)
  346. return;
  347. if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS)
  348. rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS;
  349. tx_queues = nic->tx_queues + nic->xdp_tx_queues;
  350. if (tx_queues > MAX_SND_QUEUES_PER_QS)
  351. tx_queues = tx_queues - MAX_SND_QUEUES_PER_QS;
  352. /* Set no of Rx/Tx queues in each of the SQsets */
  353. for (sqs = 0; sqs < nic->sqs_count; sqs++) {
  354. mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
  355. mbx.nicvf.vf_id = nic->vf_id;
  356. mbx.nicvf.sqs_id = sqs;
  357. nicvf_send_msg_to_pf(nic, &mbx);
  358. nic->snicvf[sqs]->sqs_id = sqs;
  359. if (rx_queues > MAX_RCV_QUEUES_PER_QS) {
  360. nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS;
  361. rx_queues -= MAX_RCV_QUEUES_PER_QS;
  362. } else {
  363. nic->snicvf[sqs]->qs->rq_cnt = rx_queues;
  364. rx_queues = 0;
  365. }
  366. if (tx_queues > MAX_SND_QUEUES_PER_QS) {
  367. nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS;
  368. tx_queues -= MAX_SND_QUEUES_PER_QS;
  369. } else {
  370. nic->snicvf[sqs]->qs->sq_cnt = tx_queues;
  371. tx_queues = 0;
  372. }
  373. nic->snicvf[sqs]->qs->cq_cnt =
  374. max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt);
  375. /* Initialize secondary Qset's queues and its interrupts */
  376. nicvf_open(nic->snicvf[sqs]->netdev);
  377. }
  378. /* Update stack with actual Rx/Tx queue count allocated */
  379. if (sqs_count != nic->sqs_count)
  380. nicvf_set_real_num_queues(nic->netdev,
  381. nic->tx_queues, nic->rx_queues);
  382. }
  383. /* Send this Qset's nicvf pointer to PF.
  384. * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs
  385. * so that packets received by these Qsets can use primary VF's netdev
  386. */
  387. static void nicvf_send_vf_struct(struct nicvf *nic)
  388. {
  389. union nic_mbx mbx = {};
  390. mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR;
  391. mbx.nicvf.sqs_mode = nic->sqs_mode;
  392. mbx.nicvf.nicvf = (u64)nic;
  393. nicvf_send_msg_to_pf(nic, &mbx);
  394. }
  395. static void nicvf_get_primary_vf_struct(struct nicvf *nic)
  396. {
  397. union nic_mbx mbx = {};
  398. mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
  399. nicvf_send_msg_to_pf(nic, &mbx);
  400. }
  401. int nicvf_set_real_num_queues(struct net_device *netdev,
  402. int tx_queues, int rx_queues)
  403. {
  404. int err = 0;
  405. err = netif_set_real_num_tx_queues(netdev, tx_queues);
  406. if (err) {
  407. netdev_err(netdev,
  408. "Failed to set no of Tx queues: %d\n", tx_queues);
  409. return err;
  410. }
  411. err = netif_set_real_num_rx_queues(netdev, rx_queues);
  412. if (err)
  413. netdev_err(netdev,
  414. "Failed to set no of Rx queues: %d\n", rx_queues);
  415. return err;
  416. }
  417. static int nicvf_init_resources(struct nicvf *nic)
  418. {
  419. int err;
  420. /* Enable Qset */
  421. nicvf_qset_config(nic, true);
  422. /* Initialize queues and HW for data transfer */
  423. err = nicvf_config_data_transfer(nic, true);
  424. if (err) {
  425. netdev_err(nic->netdev,
  426. "Failed to alloc/config VF's QSet resources\n");
  427. return err;
  428. }
  429. return 0;
  430. }
  431. static void nicvf_unmap_page(struct nicvf *nic, struct page *page, u64 dma_addr)
  432. {
  433. /* Check if it's a recycled page, if not unmap the DMA mapping.
  434. * Recycled page holds an extra reference.
  435. */
  436. if (page_ref_count(page) == 1) {
  437. dma_addr &= PAGE_MASK;
  438. dma_unmap_page_attrs(&nic->pdev->dev, dma_addr,
  439. RCV_FRAG_LEN + XDP_HEADROOM,
  440. DMA_FROM_DEVICE,
  441. DMA_ATTR_SKIP_CPU_SYNC);
  442. }
  443. }
  444. static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
  445. struct cqe_rx_t *cqe_rx, struct snd_queue *sq,
  446. struct rcv_queue *rq, struct sk_buff **skb)
  447. {
  448. struct xdp_buff xdp;
  449. struct page *page;
  450. struct nicvf_xdp_tx *xdp_tx = NULL;
  451. u32 action;
  452. u16 len, err, offset = 0;
  453. u64 dma_addr, cpu_addr;
  454. void *orig_data;
  455. /* Retrieve packet buffer's DMA address and length */
  456. len = *((u16 *)((void *)cqe_rx + (3 * sizeof(u64))));
  457. dma_addr = *((u64 *)((void *)cqe_rx + (7 * sizeof(u64))));
  458. cpu_addr = nicvf_iova_to_phys(nic, dma_addr);
  459. if (!cpu_addr)
  460. return false;
  461. cpu_addr = (u64)phys_to_virt(cpu_addr);
  462. page = virt_to_page((void *)cpu_addr);
  463. xdp.data_hard_start = page_address(page) + RCV_BUF_HEADROOM;
  464. xdp.data = (void *)cpu_addr;
  465. xdp_set_data_meta_invalid(&xdp);
  466. xdp.data_end = xdp.data + len;
  467. xdp.rxq = &rq->xdp_rxq;
  468. orig_data = xdp.data;
  469. rcu_read_lock();
  470. action = bpf_prog_run_xdp(prog, &xdp);
  471. rcu_read_unlock();
  472. /* Check if XDP program has changed headers */
  473. if (orig_data != xdp.data) {
  474. len = xdp.data_end - xdp.data;
  475. offset = orig_data - xdp.data;
  476. dma_addr -= offset;
  477. }
  478. switch (action) {
  479. case XDP_PASS:
  480. nicvf_unmap_page(nic, page, dma_addr);
  481. /* Build SKB and pass on packet to network stack */
  482. *skb = build_skb(xdp.data,
  483. RCV_FRAG_LEN - cqe_rx->align_pad + offset);
  484. if (!*skb)
  485. put_page(page);
  486. else
  487. skb_put(*skb, len);
  488. return false;
  489. case XDP_TX:
  490. nicvf_xdp_sq_append_pkt(nic, sq, (u64)xdp.data, dma_addr, len);
  491. return true;
  492. case XDP_REDIRECT:
  493. /* Save DMA address for use while transmitting */
  494. xdp_tx = (struct nicvf_xdp_tx *)page_address(page);
  495. xdp_tx->dma_addr = dma_addr;
  496. xdp_tx->qidx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx);
  497. err = xdp_do_redirect(nic->pnicvf->netdev, &xdp, prog);
  498. if (!err)
  499. return true;
  500. /* Free the page on error */
  501. nicvf_unmap_page(nic, page, dma_addr);
  502. put_page(page);
  503. break;
  504. default:
  505. bpf_warn_invalid_xdp_action(action);
  506. /* fall through */
  507. case XDP_ABORTED:
  508. trace_xdp_exception(nic->netdev, prog, action);
  509. /* fall through */
  510. case XDP_DROP:
  511. nicvf_unmap_page(nic, page, dma_addr);
  512. put_page(page);
  513. return true;
  514. }
  515. return false;
  516. }
  517. static void nicvf_snd_pkt_handler(struct net_device *netdev,
  518. struct cqe_send_t *cqe_tx,
  519. int budget, int *subdesc_cnt,
  520. unsigned int *tx_pkts, unsigned int *tx_bytes)
  521. {
  522. struct sk_buff *skb = NULL;
  523. struct page *page;
  524. struct nicvf *nic = netdev_priv(netdev);
  525. struct snd_queue *sq;
  526. struct sq_hdr_subdesc *hdr;
  527. struct sq_hdr_subdesc *tso_sqe;
  528. sq = &nic->qs->sq[cqe_tx->sq_idx];
  529. hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
  530. if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
  531. return;
  532. /* Check for errors */
  533. if (cqe_tx->send_status)
  534. nicvf_check_cqe_tx_errs(nic->pnicvf, cqe_tx);
  535. /* Is this a XDP designated Tx queue */
  536. if (sq->is_xdp) {
  537. page = (struct page *)sq->xdp_page[cqe_tx->sqe_ptr];
  538. /* Check if it's recycled page or else unmap DMA mapping */
  539. if (page && (page_ref_count(page) == 1))
  540. nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr,
  541. hdr->subdesc_cnt);
  542. /* Release page reference for recycling */
  543. if (page)
  544. put_page(page);
  545. sq->xdp_page[cqe_tx->sqe_ptr] = (u64)NULL;
  546. *subdesc_cnt += hdr->subdesc_cnt + 1;
  547. return;
  548. }
  549. skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
  550. if (skb) {
  551. /* Check for dummy descriptor used for HW TSO offload on 88xx */
  552. if (hdr->dont_send) {
  553. /* Get actual TSO descriptors and free them */
  554. tso_sqe =
  555. (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2);
  556. nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2,
  557. tso_sqe->subdesc_cnt);
  558. *subdesc_cnt += tso_sqe->subdesc_cnt + 1;
  559. } else {
  560. nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr,
  561. hdr->subdesc_cnt);
  562. }
  563. *subdesc_cnt += hdr->subdesc_cnt + 1;
  564. prefetch(skb);
  565. (*tx_pkts)++;
  566. *tx_bytes += skb->len;
  567. napi_consume_skb(skb, budget);
  568. sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL;
  569. } else {
  570. /* In case of SW TSO on 88xx, only last segment will have
  571. * a SKB attached, so just free SQEs here.
  572. */
  573. if (!nic->hw_tso)
  574. *subdesc_cnt += hdr->subdesc_cnt + 1;
  575. }
  576. }
  577. static inline void nicvf_set_rxhash(struct net_device *netdev,
  578. struct cqe_rx_t *cqe_rx,
  579. struct sk_buff *skb)
  580. {
  581. u8 hash_type;
  582. u32 hash;
  583. if (!(netdev->features & NETIF_F_RXHASH))
  584. return;
  585. switch (cqe_rx->rss_alg) {
  586. case RSS_ALG_TCP_IP:
  587. case RSS_ALG_UDP_IP:
  588. hash_type = PKT_HASH_TYPE_L4;
  589. hash = cqe_rx->rss_tag;
  590. break;
  591. case RSS_ALG_IP:
  592. hash_type = PKT_HASH_TYPE_L3;
  593. hash = cqe_rx->rss_tag;
  594. break;
  595. default:
  596. hash_type = PKT_HASH_TYPE_NONE;
  597. hash = 0;
  598. }
  599. skb_set_hash(skb, hash, hash_type);
  600. }
  601. static void nicvf_rcv_pkt_handler(struct net_device *netdev,
  602. struct napi_struct *napi,
  603. struct cqe_rx_t *cqe_rx,
  604. struct snd_queue *sq, struct rcv_queue *rq)
  605. {
  606. struct sk_buff *skb = NULL;
  607. struct nicvf *nic = netdev_priv(netdev);
  608. struct nicvf *snic = nic;
  609. int err = 0;
  610. int rq_idx;
  611. rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx);
  612. if (nic->sqs_mode) {
  613. /* Use primary VF's 'nicvf' struct */
  614. nic = nic->pnicvf;
  615. netdev = nic->netdev;
  616. }
  617. /* Check for errors */
  618. if (cqe_rx->err_level || cqe_rx->err_opcode) {
  619. err = nicvf_check_cqe_rx_errs(nic, cqe_rx);
  620. if (err && !cqe_rx->rb_cnt)
  621. return;
  622. }
  623. /* For XDP, ignore pkts spanning multiple pages */
  624. if (nic->xdp_prog && (cqe_rx->rb_cnt == 1)) {
  625. /* Packet consumed by XDP */
  626. if (nicvf_xdp_rx(snic, nic->xdp_prog, cqe_rx, sq, rq, &skb))
  627. return;
  628. } else {
  629. skb = nicvf_get_rcv_skb(snic, cqe_rx,
  630. nic->xdp_prog ? true : false);
  631. }
  632. if (!skb)
  633. return;
  634. if (netif_msg_pktdata(nic)) {
  635. netdev_info(nic->netdev, "skb 0x%p, len=%d\n", skb, skb->len);
  636. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
  637. skb->data, skb->len, true);
  638. }
  639. /* If error packet, drop it here */
  640. if (err) {
  641. dev_kfree_skb_any(skb);
  642. return;
  643. }
  644. nicvf_set_rxhash(netdev, cqe_rx, skb);
  645. skb_record_rx_queue(skb, rq_idx);
  646. if (netdev->hw_features & NETIF_F_RXCSUM) {
  647. /* HW by default verifies TCP/UDP/SCTP checksums */
  648. skb->ip_summed = CHECKSUM_UNNECESSARY;
  649. } else {
  650. skb_checksum_none_assert(skb);
  651. }
  652. skb->protocol = eth_type_trans(skb, netdev);
  653. /* Check for stripped VLAN */
  654. if (cqe_rx->vlan_found && cqe_rx->vlan_stripped)
  655. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  656. ntohs((__force __be16)cqe_rx->vlan_tci));
  657. if (napi && (netdev->features & NETIF_F_GRO))
  658. napi_gro_receive(napi, skb);
  659. else
  660. netif_receive_skb(skb);
  661. }
  662. static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
  663. struct napi_struct *napi, int budget)
  664. {
  665. int processed_cqe, work_done = 0, tx_done = 0;
  666. int cqe_count, cqe_head;
  667. int subdesc_cnt = 0;
  668. struct nicvf *nic = netdev_priv(netdev);
  669. struct queue_set *qs = nic->qs;
  670. struct cmp_queue *cq = &qs->cq[cq_idx];
  671. struct cqe_rx_t *cq_desc;
  672. struct netdev_queue *txq;
  673. struct snd_queue *sq = &qs->sq[cq_idx];
  674. struct rcv_queue *rq = &qs->rq[cq_idx];
  675. unsigned int tx_pkts = 0, tx_bytes = 0, txq_idx;
  676. spin_lock_bh(&cq->lock);
  677. loop:
  678. processed_cqe = 0;
  679. /* Get no of valid CQ entries to process */
  680. cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx);
  681. cqe_count &= CQ_CQE_COUNT;
  682. if (!cqe_count)
  683. goto done;
  684. /* Get head of the valid CQ entries */
  685. cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
  686. cqe_head &= 0xFFFF;
  687. while (processed_cqe < cqe_count) {
  688. /* Get the CQ descriptor */
  689. cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
  690. cqe_head++;
  691. cqe_head &= (cq->dmem.q_len - 1);
  692. /* Initiate prefetch for next descriptor */
  693. prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head));
  694. if ((work_done >= budget) && napi &&
  695. (cq_desc->cqe_type != CQE_TYPE_SEND)) {
  696. break;
  697. }
  698. switch (cq_desc->cqe_type) {
  699. case CQE_TYPE_RX:
  700. nicvf_rcv_pkt_handler(netdev, napi, cq_desc, sq, rq);
  701. work_done++;
  702. break;
  703. case CQE_TYPE_SEND:
  704. nicvf_snd_pkt_handler(netdev, (void *)cq_desc,
  705. budget, &subdesc_cnt,
  706. &tx_pkts, &tx_bytes);
  707. tx_done++;
  708. break;
  709. case CQE_TYPE_INVALID:
  710. case CQE_TYPE_RX_SPLIT:
  711. case CQE_TYPE_RX_TCP:
  712. case CQE_TYPE_SEND_PTP:
  713. /* Ignore for now */
  714. break;
  715. }
  716. processed_cqe++;
  717. }
  718. /* Ring doorbell to inform H/W to reuse processed CQEs */
  719. nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
  720. cq_idx, processed_cqe);
  721. if ((work_done < budget) && napi)
  722. goto loop;
  723. done:
  724. /* Update SQ's descriptor free count */
  725. if (subdesc_cnt)
  726. nicvf_put_sq_desc(sq, subdesc_cnt);
  727. txq_idx = nicvf_netdev_qidx(nic, cq_idx);
  728. /* Handle XDP TX queues */
  729. if (nic->pnicvf->xdp_prog) {
  730. if (txq_idx < nic->pnicvf->xdp_tx_queues) {
  731. nicvf_xdp_sq_doorbell(nic, sq, cq_idx);
  732. goto out;
  733. }
  734. nic = nic->pnicvf;
  735. txq_idx -= nic->pnicvf->xdp_tx_queues;
  736. }
  737. /* Wakeup TXQ if its stopped earlier due to SQ full */
  738. if (tx_done ||
  739. (atomic_read(&sq->free_cnt) >= MIN_SQ_DESC_PER_PKT_XMIT)) {
  740. netdev = nic->pnicvf->netdev;
  741. txq = netdev_get_tx_queue(netdev, txq_idx);
  742. if (tx_pkts)
  743. netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
  744. /* To read updated queue and carrier status */
  745. smp_mb();
  746. if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {
  747. netif_tx_wake_queue(txq);
  748. nic = nic->pnicvf;
  749. this_cpu_inc(nic->drv_stats->txq_wake);
  750. netif_warn(nic, tx_err, netdev,
  751. "Transmit queue wakeup SQ%d\n", txq_idx);
  752. }
  753. }
  754. out:
  755. spin_unlock_bh(&cq->lock);
  756. return work_done;
  757. }
  758. static int nicvf_poll(struct napi_struct *napi, int budget)
  759. {
  760. u64 cq_head;
  761. int work_done = 0;
  762. struct net_device *netdev = napi->dev;
  763. struct nicvf *nic = netdev_priv(netdev);
  764. struct nicvf_cq_poll *cq;
  765. cq = container_of(napi, struct nicvf_cq_poll, napi);
  766. work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
  767. if (work_done < budget) {
  768. /* Slow packet rate, exit polling */
  769. napi_complete_done(napi, work_done);
  770. /* Re-enable interrupts */
  771. cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD,
  772. cq->cq_idx);
  773. nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
  774. nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD,
  775. cq->cq_idx, cq_head);
  776. nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
  777. }
  778. return work_done;
  779. }
  780. /* Qset error interrupt handler
  781. *
  782. * As of now only CQ errors are handled
  783. */
  784. static void nicvf_handle_qs_err(unsigned long data)
  785. {
  786. struct nicvf *nic = (struct nicvf *)data;
  787. struct queue_set *qs = nic->qs;
  788. int qidx;
  789. u64 status;
  790. netif_tx_disable(nic->netdev);
  791. /* Check if it is CQ err */
  792. for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
  793. status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS,
  794. qidx);
  795. if (!(status & CQ_ERR_MASK))
  796. continue;
  797. /* Process already queued CQEs and reconfig CQ */
  798. nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
  799. nicvf_sq_disable(nic, qidx);
  800. nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0);
  801. nicvf_cmp_queue_config(nic, qs, qidx, true);
  802. nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx);
  803. nicvf_sq_enable(nic, &qs->sq[qidx], qidx);
  804. nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
  805. }
  806. netif_tx_start_all_queues(nic->netdev);
  807. /* Re-enable Qset error interrupt */
  808. nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
  809. }
  810. static void nicvf_dump_intr_status(struct nicvf *nic)
  811. {
  812. netif_info(nic, intr, nic->netdev, "interrupt status 0x%llx\n",
  813. nicvf_reg_read(nic, NIC_VF_INT));
  814. }
  815. static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq)
  816. {
  817. struct nicvf *nic = (struct nicvf *)nicvf_irq;
  818. u64 intr;
  819. nicvf_dump_intr_status(nic);
  820. intr = nicvf_reg_read(nic, NIC_VF_INT);
  821. /* Check for spurious interrupt */
  822. if (!(intr & NICVF_INTR_MBOX_MASK))
  823. return IRQ_HANDLED;
  824. nicvf_handle_mbx_intr(nic);
  825. return IRQ_HANDLED;
  826. }
  827. static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq)
  828. {
  829. struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq;
  830. struct nicvf *nic = cq_poll->nicvf;
  831. int qidx = cq_poll->cq_idx;
  832. nicvf_dump_intr_status(nic);
  833. /* Disable interrupts */
  834. nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
  835. /* Schedule NAPI */
  836. napi_schedule_irqoff(&cq_poll->napi);
  837. /* Clear interrupt */
  838. nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
  839. return IRQ_HANDLED;
  840. }
  841. static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq)
  842. {
  843. struct nicvf *nic = (struct nicvf *)nicvf_irq;
  844. u8 qidx;
  845. nicvf_dump_intr_status(nic);
  846. /* Disable RBDR interrupt and schedule softirq */
  847. for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) {
  848. if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx))
  849. continue;
  850. nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
  851. tasklet_hi_schedule(&nic->rbdr_task);
  852. /* Clear interrupt */
  853. nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
  854. }
  855. return IRQ_HANDLED;
  856. }
  857. static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq)
  858. {
  859. struct nicvf *nic = (struct nicvf *)nicvf_irq;
  860. nicvf_dump_intr_status(nic);
  861. /* Disable Qset err interrupt and schedule softirq */
  862. nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
  863. tasklet_hi_schedule(&nic->qs_err_task);
  864. nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
  865. return IRQ_HANDLED;
  866. }
  867. static void nicvf_set_irq_affinity(struct nicvf *nic)
  868. {
  869. int vec, cpu;
  870. for (vec = 0; vec < nic->num_vec; vec++) {
  871. if (!nic->irq_allocated[vec])
  872. continue;
  873. if (!zalloc_cpumask_var(&nic->affinity_mask[vec], GFP_KERNEL))
  874. return;
  875. /* CQ interrupts */
  876. if (vec < NICVF_INTR_ID_SQ)
  877. /* Leave CPU0 for RBDR and other interrupts */
  878. cpu = nicvf_netdev_qidx(nic, vec) + 1;
  879. else
  880. cpu = 0;
  881. cpumask_set_cpu(cpumask_local_spread(cpu, nic->node),
  882. nic->affinity_mask[vec]);
  883. irq_set_affinity_hint(pci_irq_vector(nic->pdev, vec),
  884. nic->affinity_mask[vec]);
  885. }
  886. }
  887. static int nicvf_register_interrupts(struct nicvf *nic)
  888. {
  889. int irq, ret = 0;
  890. for_each_cq_irq(irq)
  891. sprintf(nic->irq_name[irq], "%s-rxtx-%d",
  892. nic->pnicvf->netdev->name,
  893. nicvf_netdev_qidx(nic, irq));
  894. for_each_sq_irq(irq)
  895. sprintf(nic->irq_name[irq], "%s-sq-%d",
  896. nic->pnicvf->netdev->name,
  897. nicvf_netdev_qidx(nic, irq - NICVF_INTR_ID_SQ));
  898. for_each_rbdr_irq(irq)
  899. sprintf(nic->irq_name[irq], "%s-rbdr-%d",
  900. nic->pnicvf->netdev->name,
  901. nic->sqs_mode ? (nic->sqs_id + 1) : 0);
  902. /* Register CQ interrupts */
  903. for (irq = 0; irq < nic->qs->cq_cnt; irq++) {
  904. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  905. nicvf_intr_handler,
  906. 0, nic->irq_name[irq], nic->napi[irq]);
  907. if (ret)
  908. goto err;
  909. nic->irq_allocated[irq] = true;
  910. }
  911. /* Register RBDR interrupt */
  912. for (irq = NICVF_INTR_ID_RBDR;
  913. irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) {
  914. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  915. nicvf_rbdr_intr_handler,
  916. 0, nic->irq_name[irq], nic);
  917. if (ret)
  918. goto err;
  919. nic->irq_allocated[irq] = true;
  920. }
  921. /* Register QS error interrupt */
  922. sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR], "%s-qset-err-%d",
  923. nic->pnicvf->netdev->name,
  924. nic->sqs_mode ? (nic->sqs_id + 1) : 0);
  925. irq = NICVF_INTR_ID_QS_ERR;
  926. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  927. nicvf_qs_err_intr_handler,
  928. 0, nic->irq_name[irq], nic);
  929. if (ret)
  930. goto err;
  931. nic->irq_allocated[irq] = true;
  932. /* Set IRQ affinities */
  933. nicvf_set_irq_affinity(nic);
  934. err:
  935. if (ret)
  936. netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq);
  937. return ret;
  938. }
  939. static void nicvf_unregister_interrupts(struct nicvf *nic)
  940. {
  941. struct pci_dev *pdev = nic->pdev;
  942. int irq;
  943. /* Free registered interrupts */
  944. for (irq = 0; irq < nic->num_vec; irq++) {
  945. if (!nic->irq_allocated[irq])
  946. continue;
  947. irq_set_affinity_hint(pci_irq_vector(pdev, irq), NULL);
  948. free_cpumask_var(nic->affinity_mask[irq]);
  949. if (irq < NICVF_INTR_ID_SQ)
  950. free_irq(pci_irq_vector(pdev, irq), nic->napi[irq]);
  951. else
  952. free_irq(pci_irq_vector(pdev, irq), nic);
  953. nic->irq_allocated[irq] = false;
  954. }
  955. /* Disable MSI-X */
  956. pci_free_irq_vectors(pdev);
  957. nic->num_vec = 0;
  958. }
  959. /* Initialize MSIX vectors and register MISC interrupt.
  960. * Send READY message to PF to check if its alive
  961. */
  962. static int nicvf_register_misc_interrupt(struct nicvf *nic)
  963. {
  964. int ret = 0;
  965. int irq = NICVF_INTR_ID_MISC;
  966. /* Return if mailbox interrupt is already registered */
  967. if (nic->pdev->msix_enabled)
  968. return 0;
  969. /* Enable MSI-X */
  970. nic->num_vec = pci_msix_vec_count(nic->pdev);
  971. ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec,
  972. PCI_IRQ_MSIX);
  973. if (ret < 0) {
  974. netdev_err(nic->netdev,
  975. "Req for #%d msix vectors failed\n", nic->num_vec);
  976. return 1;
  977. }
  978. sprintf(nic->irq_name[irq], "%s Mbox", "NICVF");
  979. /* Register Misc interrupt */
  980. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  981. nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic);
  982. if (ret)
  983. return ret;
  984. nic->irq_allocated[irq] = true;
  985. /* Enable mailbox interrupt */
  986. nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0);
  987. /* Check if VF is able to communicate with PF */
  988. if (!nicvf_check_pf_ready(nic)) {
  989. nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
  990. nicvf_unregister_interrupts(nic);
  991. return 1;
  992. }
  993. return 0;
  994. }
  995. static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
  996. {
  997. struct nicvf *nic = netdev_priv(netdev);
  998. int qid = skb_get_queue_mapping(skb);
  999. struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
  1000. struct nicvf *snic;
  1001. struct snd_queue *sq;
  1002. int tmp;
  1003. /* Check for minimum packet length */
  1004. if (skb->len <= ETH_HLEN) {
  1005. dev_kfree_skb(skb);
  1006. return NETDEV_TX_OK;
  1007. }
  1008. /* In XDP case, initial HW tx queues are used for XDP,
  1009. * but stack's queue mapping starts at '0', so skip the
  1010. * Tx queues attached to Rx queues for XDP.
  1011. */
  1012. if (nic->xdp_prog)
  1013. qid += nic->xdp_tx_queues;
  1014. snic = nic;
  1015. /* Get secondary Qset's SQ structure */
  1016. if (qid >= MAX_SND_QUEUES_PER_QS) {
  1017. tmp = qid / MAX_SND_QUEUES_PER_QS;
  1018. snic = (struct nicvf *)nic->snicvf[tmp - 1];
  1019. if (!snic) {
  1020. netdev_warn(nic->netdev,
  1021. "Secondary Qset#%d's ptr not initialized\n",
  1022. tmp - 1);
  1023. dev_kfree_skb(skb);
  1024. return NETDEV_TX_OK;
  1025. }
  1026. qid = qid % MAX_SND_QUEUES_PER_QS;
  1027. }
  1028. sq = &snic->qs->sq[qid];
  1029. if (!netif_tx_queue_stopped(txq) &&
  1030. !nicvf_sq_append_skb(snic, sq, skb, qid)) {
  1031. netif_tx_stop_queue(txq);
  1032. /* Barrier, so that stop_queue visible to other cpus */
  1033. smp_mb();
  1034. /* Check again, incase another cpu freed descriptors */
  1035. if (atomic_read(&sq->free_cnt) > MIN_SQ_DESC_PER_PKT_XMIT) {
  1036. netif_tx_wake_queue(txq);
  1037. } else {
  1038. this_cpu_inc(nic->drv_stats->txq_stop);
  1039. netif_warn(nic, tx_err, netdev,
  1040. "Transmit ring full, stopping SQ%d\n", qid);
  1041. }
  1042. return NETDEV_TX_BUSY;
  1043. }
  1044. return NETDEV_TX_OK;
  1045. }
  1046. static inline void nicvf_free_cq_poll(struct nicvf *nic)
  1047. {
  1048. struct nicvf_cq_poll *cq_poll;
  1049. int qidx;
  1050. for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
  1051. cq_poll = nic->napi[qidx];
  1052. if (!cq_poll)
  1053. continue;
  1054. nic->napi[qidx] = NULL;
  1055. kfree(cq_poll);
  1056. }
  1057. }
  1058. int nicvf_stop(struct net_device *netdev)
  1059. {
  1060. int irq, qidx;
  1061. struct nicvf *nic = netdev_priv(netdev);
  1062. struct queue_set *qs = nic->qs;
  1063. struct nicvf_cq_poll *cq_poll = NULL;
  1064. union nic_mbx mbx = {};
  1065. mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN;
  1066. nicvf_send_msg_to_pf(nic, &mbx);
  1067. netif_carrier_off(netdev);
  1068. netif_tx_stop_all_queues(nic->netdev);
  1069. nic->link_up = false;
  1070. /* Teardown secondary qsets first */
  1071. if (!nic->sqs_mode) {
  1072. for (qidx = 0; qidx < nic->sqs_count; qidx++) {
  1073. if (!nic->snicvf[qidx])
  1074. continue;
  1075. nicvf_stop(nic->snicvf[qidx]->netdev);
  1076. nic->snicvf[qidx] = NULL;
  1077. }
  1078. }
  1079. /* Disable RBDR & QS error interrupts */
  1080. for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
  1081. nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
  1082. nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
  1083. }
  1084. nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
  1085. nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
  1086. /* Wait for pending IRQ handlers to finish */
  1087. for (irq = 0; irq < nic->num_vec; irq++)
  1088. synchronize_irq(pci_irq_vector(nic->pdev, irq));
  1089. tasklet_kill(&nic->rbdr_task);
  1090. tasklet_kill(&nic->qs_err_task);
  1091. if (nic->rb_work_scheduled)
  1092. cancel_delayed_work_sync(&nic->rbdr_work);
  1093. for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
  1094. cq_poll = nic->napi[qidx];
  1095. if (!cq_poll)
  1096. continue;
  1097. napi_synchronize(&cq_poll->napi);
  1098. /* CQ intr is enabled while napi_complete,
  1099. * so disable it now
  1100. */
  1101. nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
  1102. nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
  1103. napi_disable(&cq_poll->napi);
  1104. netif_napi_del(&cq_poll->napi);
  1105. }
  1106. netif_tx_disable(netdev);
  1107. for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
  1108. netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
  1109. /* Free resources */
  1110. nicvf_config_data_transfer(nic, false);
  1111. /* Disable HW Qset */
  1112. nicvf_qset_config(nic, false);
  1113. /* disable mailbox interrupt */
  1114. nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
  1115. nicvf_unregister_interrupts(nic);
  1116. nicvf_free_cq_poll(nic);
  1117. /* Clear multiqset info */
  1118. nic->pnicvf = nic;
  1119. return 0;
  1120. }
  1121. static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
  1122. {
  1123. union nic_mbx mbx = {};
  1124. mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
  1125. mbx.frs.max_frs = mtu;
  1126. mbx.frs.vf_id = nic->vf_id;
  1127. return nicvf_send_msg_to_pf(nic, &mbx);
  1128. }
  1129. int nicvf_open(struct net_device *netdev)
  1130. {
  1131. int cpu, err, qidx;
  1132. struct nicvf *nic = netdev_priv(netdev);
  1133. struct queue_set *qs = nic->qs;
  1134. struct nicvf_cq_poll *cq_poll = NULL;
  1135. union nic_mbx mbx = {};
  1136. netif_carrier_off(netdev);
  1137. err = nicvf_register_misc_interrupt(nic);
  1138. if (err)
  1139. return err;
  1140. /* Register NAPI handler for processing CQEs */
  1141. for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
  1142. cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL);
  1143. if (!cq_poll) {
  1144. err = -ENOMEM;
  1145. goto napi_del;
  1146. }
  1147. cq_poll->cq_idx = qidx;
  1148. cq_poll->nicvf = nic;
  1149. netif_napi_add(netdev, &cq_poll->napi, nicvf_poll,
  1150. NAPI_POLL_WEIGHT);
  1151. napi_enable(&cq_poll->napi);
  1152. nic->napi[qidx] = cq_poll;
  1153. }
  1154. /* Check if we got MAC address from PF or else generate a radom MAC */
  1155. if (!nic->sqs_mode && is_zero_ether_addr(netdev->dev_addr)) {
  1156. eth_hw_addr_random(netdev);
  1157. nicvf_hw_set_mac_addr(nic, netdev);
  1158. }
  1159. if (nic->set_mac_pending) {
  1160. nic->set_mac_pending = false;
  1161. nicvf_hw_set_mac_addr(nic, netdev);
  1162. }
  1163. /* Init tasklet for handling Qset err interrupt */
  1164. tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err,
  1165. (unsigned long)nic);
  1166. /* Init RBDR tasklet which will refill RBDR */
  1167. tasklet_init(&nic->rbdr_task, nicvf_rbdr_task,
  1168. (unsigned long)nic);
  1169. INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work);
  1170. /* Configure CPI alorithm */
  1171. nic->cpi_alg = cpi_alg;
  1172. if (!nic->sqs_mode)
  1173. nicvf_config_cpi(nic);
  1174. nicvf_request_sqs(nic);
  1175. if (nic->sqs_mode)
  1176. nicvf_get_primary_vf_struct(nic);
  1177. /* Configure receive side scaling and MTU */
  1178. if (!nic->sqs_mode) {
  1179. nicvf_rss_init(nic);
  1180. err = nicvf_update_hw_max_frs(nic, netdev->mtu);
  1181. if (err)
  1182. goto cleanup;
  1183. /* Clear percpu stats */
  1184. for_each_possible_cpu(cpu)
  1185. memset(per_cpu_ptr(nic->drv_stats, cpu), 0,
  1186. sizeof(struct nicvf_drv_stats));
  1187. }
  1188. err = nicvf_register_interrupts(nic);
  1189. if (err)
  1190. goto cleanup;
  1191. /* Initialize the queues */
  1192. err = nicvf_init_resources(nic);
  1193. if (err)
  1194. goto cleanup;
  1195. /* Make sure queue initialization is written */
  1196. wmb();
  1197. nicvf_reg_write(nic, NIC_VF_INT, -1);
  1198. /* Enable Qset err interrupt */
  1199. nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
  1200. /* Enable completion queue interrupt */
  1201. for (qidx = 0; qidx < qs->cq_cnt; qidx++)
  1202. nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
  1203. /* Enable RBDR threshold interrupt */
  1204. for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
  1205. nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
  1206. /* Send VF config done msg to PF */
  1207. mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
  1208. nicvf_write_to_mbx(nic, &mbx);
  1209. return 0;
  1210. cleanup:
  1211. nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
  1212. nicvf_unregister_interrupts(nic);
  1213. tasklet_kill(&nic->qs_err_task);
  1214. tasklet_kill(&nic->rbdr_task);
  1215. napi_del:
  1216. for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
  1217. cq_poll = nic->napi[qidx];
  1218. if (!cq_poll)
  1219. continue;
  1220. napi_disable(&cq_poll->napi);
  1221. netif_napi_del(&cq_poll->napi);
  1222. }
  1223. nicvf_free_cq_poll(nic);
  1224. return err;
  1225. }
  1226. static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
  1227. {
  1228. struct nicvf *nic = netdev_priv(netdev);
  1229. int orig_mtu = netdev->mtu;
  1230. netdev->mtu = new_mtu;
  1231. if (!netif_running(netdev))
  1232. return 0;
  1233. if (nicvf_update_hw_max_frs(nic, new_mtu)) {
  1234. netdev->mtu = orig_mtu;
  1235. return -EINVAL;
  1236. }
  1237. return 0;
  1238. }
  1239. static int nicvf_set_mac_address(struct net_device *netdev, void *p)
  1240. {
  1241. struct sockaddr *addr = p;
  1242. struct nicvf *nic = netdev_priv(netdev);
  1243. if (!is_valid_ether_addr(addr->sa_data))
  1244. return -EADDRNOTAVAIL;
  1245. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1246. if (nic->pdev->msix_enabled) {
  1247. if (nicvf_hw_set_mac_addr(nic, netdev))
  1248. return -EBUSY;
  1249. } else {
  1250. nic->set_mac_pending = true;
  1251. }
  1252. return 0;
  1253. }
  1254. void nicvf_update_lmac_stats(struct nicvf *nic)
  1255. {
  1256. int stat = 0;
  1257. union nic_mbx mbx = {};
  1258. if (!netif_running(nic->netdev))
  1259. return;
  1260. mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
  1261. mbx.bgx_stats.vf_id = nic->vf_id;
  1262. /* Rx stats */
  1263. mbx.bgx_stats.rx = 1;
  1264. while (stat < BGX_RX_STATS_COUNT) {
  1265. mbx.bgx_stats.idx = stat;
  1266. if (nicvf_send_msg_to_pf(nic, &mbx))
  1267. return;
  1268. stat++;
  1269. }
  1270. stat = 0;
  1271. /* Tx stats */
  1272. mbx.bgx_stats.rx = 0;
  1273. while (stat < BGX_TX_STATS_COUNT) {
  1274. mbx.bgx_stats.idx = stat;
  1275. if (nicvf_send_msg_to_pf(nic, &mbx))
  1276. return;
  1277. stat++;
  1278. }
  1279. }
  1280. void nicvf_update_stats(struct nicvf *nic)
  1281. {
  1282. int qidx, cpu;
  1283. u64 tmp_stats = 0;
  1284. struct nicvf_hw_stats *stats = &nic->hw_stats;
  1285. struct nicvf_drv_stats *drv_stats;
  1286. struct queue_set *qs = nic->qs;
  1287. #define GET_RX_STATS(reg) \
  1288. nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
  1289. #define GET_TX_STATS(reg) \
  1290. nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
  1291. stats->rx_bytes = GET_RX_STATS(RX_OCTS);
  1292. stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST);
  1293. stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST);
  1294. stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST);
  1295. stats->rx_fcs_errors = GET_RX_STATS(RX_FCS);
  1296. stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR);
  1297. stats->rx_drop_red = GET_RX_STATS(RX_RED);
  1298. stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS);
  1299. stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN);
  1300. stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS);
  1301. stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST);
  1302. stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST);
  1303. stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
  1304. stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
  1305. stats->tx_bytes = GET_TX_STATS(TX_OCTS);
  1306. stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST);
  1307. stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST);
  1308. stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST);
  1309. stats->tx_drops = GET_TX_STATS(TX_DROP);
  1310. /* On T88 pass 2.0, the dummy SQE added for TSO notification
  1311. * via CQE has 'dont_send' set. Hence HW drops the pkt pointed
  1312. * pointed by dummy SQE and results in tx_drops counter being
  1313. * incremented. Subtracting it from tx_tso counter will give
  1314. * exact tx_drops counter.
  1315. */
  1316. if (nic->t88 && nic->hw_tso) {
  1317. for_each_possible_cpu(cpu) {
  1318. drv_stats = per_cpu_ptr(nic->drv_stats, cpu);
  1319. tmp_stats += drv_stats->tx_tso;
  1320. }
  1321. stats->tx_drops = tmp_stats - stats->tx_drops;
  1322. }
  1323. stats->tx_frames = stats->tx_ucast_frames +
  1324. stats->tx_bcast_frames +
  1325. stats->tx_mcast_frames;
  1326. stats->rx_frames = stats->rx_ucast_frames +
  1327. stats->rx_bcast_frames +
  1328. stats->rx_mcast_frames;
  1329. stats->rx_drops = stats->rx_drop_red +
  1330. stats->rx_drop_overrun;
  1331. /* Update RQ and SQ stats */
  1332. for (qidx = 0; qidx < qs->rq_cnt; qidx++)
  1333. nicvf_update_rq_stats(nic, qidx);
  1334. for (qidx = 0; qidx < qs->sq_cnt; qidx++)
  1335. nicvf_update_sq_stats(nic, qidx);
  1336. }
  1337. static void nicvf_get_stats64(struct net_device *netdev,
  1338. struct rtnl_link_stats64 *stats)
  1339. {
  1340. struct nicvf *nic = netdev_priv(netdev);
  1341. struct nicvf_hw_stats *hw_stats = &nic->hw_stats;
  1342. nicvf_update_stats(nic);
  1343. stats->rx_bytes = hw_stats->rx_bytes;
  1344. stats->rx_packets = hw_stats->rx_frames;
  1345. stats->rx_dropped = hw_stats->rx_drops;
  1346. stats->multicast = hw_stats->rx_mcast_frames;
  1347. stats->tx_bytes = hw_stats->tx_bytes;
  1348. stats->tx_packets = hw_stats->tx_frames;
  1349. stats->tx_dropped = hw_stats->tx_drops;
  1350. }
  1351. static void nicvf_tx_timeout(struct net_device *dev)
  1352. {
  1353. struct nicvf *nic = netdev_priv(dev);
  1354. netif_warn(nic, tx_err, dev, "Transmit timed out, resetting\n");
  1355. this_cpu_inc(nic->drv_stats->tx_timeout);
  1356. schedule_work(&nic->reset_task);
  1357. }
  1358. static void nicvf_reset_task(struct work_struct *work)
  1359. {
  1360. struct nicvf *nic;
  1361. nic = container_of(work, struct nicvf, reset_task);
  1362. if (!netif_running(nic->netdev))
  1363. return;
  1364. nicvf_stop(nic->netdev);
  1365. nicvf_open(nic->netdev);
  1366. netif_trans_update(nic->netdev);
  1367. }
  1368. static int nicvf_config_loopback(struct nicvf *nic,
  1369. netdev_features_t features)
  1370. {
  1371. union nic_mbx mbx = {};
  1372. mbx.lbk.msg = NIC_MBOX_MSG_LOOPBACK;
  1373. mbx.lbk.vf_id = nic->vf_id;
  1374. mbx.lbk.enable = (features & NETIF_F_LOOPBACK) != 0;
  1375. return nicvf_send_msg_to_pf(nic, &mbx);
  1376. }
  1377. static netdev_features_t nicvf_fix_features(struct net_device *netdev,
  1378. netdev_features_t features)
  1379. {
  1380. struct nicvf *nic = netdev_priv(netdev);
  1381. if ((features & NETIF_F_LOOPBACK) &&
  1382. netif_running(netdev) && !nic->loopback_supported)
  1383. features &= ~NETIF_F_LOOPBACK;
  1384. return features;
  1385. }
  1386. static int nicvf_set_features(struct net_device *netdev,
  1387. netdev_features_t features)
  1388. {
  1389. struct nicvf *nic = netdev_priv(netdev);
  1390. netdev_features_t changed = features ^ netdev->features;
  1391. if (changed & NETIF_F_HW_VLAN_CTAG_RX)
  1392. nicvf_config_vlan_stripping(nic, features);
  1393. if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
  1394. return nicvf_config_loopback(nic, features);
  1395. return 0;
  1396. }
  1397. static void nicvf_set_xdp_queues(struct nicvf *nic, bool bpf_attached)
  1398. {
  1399. u8 cq_count, txq_count;
  1400. /* Set XDP Tx queue count same as Rx queue count */
  1401. if (!bpf_attached)
  1402. nic->xdp_tx_queues = 0;
  1403. else
  1404. nic->xdp_tx_queues = nic->rx_queues;
  1405. /* If queue count > MAX_CMP_QUEUES_PER_QS, then additional qsets
  1406. * needs to be allocated, check how many.
  1407. */
  1408. txq_count = nic->xdp_tx_queues + nic->tx_queues;
  1409. cq_count = max(nic->rx_queues, txq_count);
  1410. if (cq_count > MAX_CMP_QUEUES_PER_QS) {
  1411. nic->sqs_count = roundup(cq_count, MAX_CMP_QUEUES_PER_QS);
  1412. nic->sqs_count = (nic->sqs_count / MAX_CMP_QUEUES_PER_QS) - 1;
  1413. } else {
  1414. nic->sqs_count = 0;
  1415. }
  1416. /* Set primary Qset's resources */
  1417. nic->qs->rq_cnt = min_t(u8, nic->rx_queues, MAX_RCV_QUEUES_PER_QS);
  1418. nic->qs->sq_cnt = min_t(u8, txq_count, MAX_SND_QUEUES_PER_QS);
  1419. nic->qs->cq_cnt = max_t(u8, nic->qs->rq_cnt, nic->qs->sq_cnt);
  1420. /* Update stack */
  1421. nicvf_set_real_num_queues(nic->netdev, nic->tx_queues, nic->rx_queues);
  1422. }
  1423. static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog)
  1424. {
  1425. struct net_device *dev = nic->netdev;
  1426. bool if_up = netif_running(nic->netdev);
  1427. struct bpf_prog *old_prog;
  1428. bool bpf_attached = false;
  1429. /* For now just support only the usual MTU sized frames */
  1430. if (prog && (dev->mtu > 1500)) {
  1431. netdev_warn(dev, "Jumbo frames not yet supported with XDP, current MTU %d.\n",
  1432. dev->mtu);
  1433. return -EOPNOTSUPP;
  1434. }
  1435. /* ALL SQs attached to CQs i.e same as RQs, are treated as
  1436. * XDP Tx queues and more Tx queues are allocated for
  1437. * network stack to send pkts out.
  1438. *
  1439. * No of Tx queues are either same as Rx queues or whatever
  1440. * is left in max no of queues possible.
  1441. */
  1442. if ((nic->rx_queues + nic->tx_queues) > nic->max_queues) {
  1443. netdev_warn(dev,
  1444. "Failed to attach BPF prog, RXQs + TXQs > Max %d\n",
  1445. nic->max_queues);
  1446. return -ENOMEM;
  1447. }
  1448. if (if_up)
  1449. nicvf_stop(nic->netdev);
  1450. old_prog = xchg(&nic->xdp_prog, prog);
  1451. /* Detach old prog, if any */
  1452. if (old_prog)
  1453. bpf_prog_put(old_prog);
  1454. if (nic->xdp_prog) {
  1455. /* Attach BPF program */
  1456. nic->xdp_prog = bpf_prog_add(nic->xdp_prog, nic->rx_queues - 1);
  1457. if (!IS_ERR(nic->xdp_prog))
  1458. bpf_attached = true;
  1459. }
  1460. /* Calculate Tx queues needed for XDP and network stack */
  1461. nicvf_set_xdp_queues(nic, bpf_attached);
  1462. if (if_up) {
  1463. /* Reinitialize interface, clean slate */
  1464. nicvf_open(nic->netdev);
  1465. netif_trans_update(nic->netdev);
  1466. }
  1467. return 0;
  1468. }
  1469. static int nicvf_xdp(struct net_device *netdev, struct netdev_bpf *xdp)
  1470. {
  1471. struct nicvf *nic = netdev_priv(netdev);
  1472. /* To avoid checks while retrieving buffer address from CQE_RX,
  1473. * do not support XDP for T88 pass1.x silicons which are anyway
  1474. * not in use widely.
  1475. */
  1476. if (pass1_silicon(nic->pdev))
  1477. return -EOPNOTSUPP;
  1478. switch (xdp->command) {
  1479. case XDP_SETUP_PROG:
  1480. return nicvf_xdp_setup(nic, xdp->prog);
  1481. case XDP_QUERY_PROG:
  1482. xdp->prog_attached = !!nic->xdp_prog;
  1483. xdp->prog_id = nic->xdp_prog ? nic->xdp_prog->aux->id : 0;
  1484. return 0;
  1485. default:
  1486. return -EINVAL;
  1487. }
  1488. }
  1489. static int nicvf_xdp_xmit(struct net_device *netdev, struct xdp_buff *xdp)
  1490. {
  1491. struct nicvf *nic = netdev_priv(netdev);
  1492. struct nicvf *snic = nic;
  1493. struct nicvf_xdp_tx *xdp_tx;
  1494. struct snd_queue *sq;
  1495. struct page *page;
  1496. int err, qidx;
  1497. if (!netif_running(netdev) || !nic->xdp_prog)
  1498. return -EINVAL;
  1499. page = virt_to_page(xdp->data);
  1500. xdp_tx = (struct nicvf_xdp_tx *)page_address(page);
  1501. qidx = xdp_tx->qidx;
  1502. if (xdp_tx->qidx >= nic->xdp_tx_queues)
  1503. return -EINVAL;
  1504. /* Get secondary Qset's info */
  1505. if (xdp_tx->qidx >= MAX_SND_QUEUES_PER_QS) {
  1506. qidx = xdp_tx->qidx / MAX_SND_QUEUES_PER_QS;
  1507. snic = (struct nicvf *)nic->snicvf[qidx - 1];
  1508. if (!snic)
  1509. return -EINVAL;
  1510. qidx = xdp_tx->qidx % MAX_SND_QUEUES_PER_QS;
  1511. }
  1512. sq = &snic->qs->sq[qidx];
  1513. err = nicvf_xdp_sq_append_pkt(snic, sq, (u64)xdp->data,
  1514. xdp_tx->dma_addr,
  1515. xdp->data_end - xdp->data);
  1516. if (err)
  1517. return -ENOMEM;
  1518. nicvf_xdp_sq_doorbell(snic, sq, qidx);
  1519. return 0;
  1520. }
  1521. static void nicvf_xdp_flush(struct net_device *dev)
  1522. {
  1523. return;
  1524. }
  1525. static const struct net_device_ops nicvf_netdev_ops = {
  1526. .ndo_open = nicvf_open,
  1527. .ndo_stop = nicvf_stop,
  1528. .ndo_start_xmit = nicvf_xmit,
  1529. .ndo_change_mtu = nicvf_change_mtu,
  1530. .ndo_set_mac_address = nicvf_set_mac_address,
  1531. .ndo_get_stats64 = nicvf_get_stats64,
  1532. .ndo_tx_timeout = nicvf_tx_timeout,
  1533. .ndo_fix_features = nicvf_fix_features,
  1534. .ndo_set_features = nicvf_set_features,
  1535. .ndo_bpf = nicvf_xdp,
  1536. .ndo_xdp_xmit = nicvf_xdp_xmit,
  1537. .ndo_xdp_flush = nicvf_xdp_flush,
  1538. };
  1539. static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1540. {
  1541. struct device *dev = &pdev->dev;
  1542. struct net_device *netdev;
  1543. struct nicvf *nic;
  1544. int err, qcount;
  1545. u16 sdevid;
  1546. err = pci_enable_device(pdev);
  1547. if (err) {
  1548. dev_err(dev, "Failed to enable PCI device\n");
  1549. return err;
  1550. }
  1551. err = pci_request_regions(pdev, DRV_NAME);
  1552. if (err) {
  1553. dev_err(dev, "PCI request regions failed 0x%x\n", err);
  1554. goto err_disable_device;
  1555. }
  1556. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
  1557. if (err) {
  1558. dev_err(dev, "Unable to get usable DMA configuration\n");
  1559. goto err_release_regions;
  1560. }
  1561. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
  1562. if (err) {
  1563. dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n");
  1564. goto err_release_regions;
  1565. }
  1566. qcount = netif_get_num_default_rss_queues();
  1567. /* Restrict multiqset support only for host bound VFs */
  1568. if (pdev->is_virtfn) {
  1569. /* Set max number of queues per VF */
  1570. qcount = min_t(int, num_online_cpus(),
  1571. (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS);
  1572. }
  1573. netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount);
  1574. if (!netdev) {
  1575. err = -ENOMEM;
  1576. goto err_release_regions;
  1577. }
  1578. pci_set_drvdata(pdev, netdev);
  1579. SET_NETDEV_DEV(netdev, &pdev->dev);
  1580. nic = netdev_priv(netdev);
  1581. nic->netdev = netdev;
  1582. nic->pdev = pdev;
  1583. nic->pnicvf = nic;
  1584. nic->max_queues = qcount;
  1585. /* If no of CPUs are too low, there won't be any queues left
  1586. * for XDP_TX, hence double it.
  1587. */
  1588. if (!nic->t88)
  1589. nic->max_queues *= 2;
  1590. /* MAP VF's configuration registers */
  1591. nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
  1592. if (!nic->reg_base) {
  1593. dev_err(dev, "Cannot map config register space, aborting\n");
  1594. err = -ENOMEM;
  1595. goto err_free_netdev;
  1596. }
  1597. nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats);
  1598. if (!nic->drv_stats) {
  1599. err = -ENOMEM;
  1600. goto err_free_netdev;
  1601. }
  1602. err = nicvf_set_qset_resources(nic);
  1603. if (err)
  1604. goto err_free_netdev;
  1605. /* Check if PF is alive and get MAC address for this VF */
  1606. err = nicvf_register_misc_interrupt(nic);
  1607. if (err)
  1608. goto err_free_netdev;
  1609. nicvf_send_vf_struct(nic);
  1610. if (!pass1_silicon(nic->pdev))
  1611. nic->hw_tso = true;
  1612. /* Get iommu domain for iova to physical addr conversion */
  1613. nic->iommu_domain = iommu_get_domain_for_dev(dev);
  1614. pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
  1615. if (sdevid == 0xA134)
  1616. nic->t88 = true;
  1617. /* Check if this VF is in QS only mode */
  1618. if (nic->sqs_mode)
  1619. return 0;
  1620. err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues);
  1621. if (err)
  1622. goto err_unregister_interrupts;
  1623. netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_SG |
  1624. NETIF_F_TSO | NETIF_F_GRO | NETIF_F_TSO6 |
  1625. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1626. NETIF_F_HW_VLAN_CTAG_RX);
  1627. netdev->hw_features |= NETIF_F_RXHASH;
  1628. netdev->features |= netdev->hw_features;
  1629. netdev->hw_features |= NETIF_F_LOOPBACK;
  1630. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM |
  1631. NETIF_F_IPV6_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
  1632. netdev->netdev_ops = &nicvf_netdev_ops;
  1633. netdev->watchdog_timeo = NICVF_TX_TIMEOUT;
  1634. /* MTU range: 64 - 9200 */
  1635. netdev->min_mtu = NIC_HW_MIN_FRS;
  1636. netdev->max_mtu = NIC_HW_MAX_FRS;
  1637. INIT_WORK(&nic->reset_task, nicvf_reset_task);
  1638. err = register_netdev(netdev);
  1639. if (err) {
  1640. dev_err(dev, "Failed to register netdevice\n");
  1641. goto err_unregister_interrupts;
  1642. }
  1643. nic->msg_enable = debug;
  1644. nicvf_set_ethtool_ops(netdev);
  1645. return 0;
  1646. err_unregister_interrupts:
  1647. nicvf_unregister_interrupts(nic);
  1648. err_free_netdev:
  1649. pci_set_drvdata(pdev, NULL);
  1650. if (nic->drv_stats)
  1651. free_percpu(nic->drv_stats);
  1652. free_netdev(netdev);
  1653. err_release_regions:
  1654. pci_release_regions(pdev);
  1655. err_disable_device:
  1656. pci_disable_device(pdev);
  1657. return err;
  1658. }
  1659. static void nicvf_remove(struct pci_dev *pdev)
  1660. {
  1661. struct net_device *netdev = pci_get_drvdata(pdev);
  1662. struct nicvf *nic;
  1663. struct net_device *pnetdev;
  1664. if (!netdev)
  1665. return;
  1666. nic = netdev_priv(netdev);
  1667. pnetdev = nic->pnicvf->netdev;
  1668. /* Check if this Qset is assigned to different VF.
  1669. * If yes, clean primary and all secondary Qsets.
  1670. */
  1671. if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED))
  1672. unregister_netdev(pnetdev);
  1673. nicvf_unregister_interrupts(nic);
  1674. pci_set_drvdata(pdev, NULL);
  1675. if (nic->drv_stats)
  1676. free_percpu(nic->drv_stats);
  1677. free_netdev(netdev);
  1678. pci_release_regions(pdev);
  1679. pci_disable_device(pdev);
  1680. }
  1681. static void nicvf_shutdown(struct pci_dev *pdev)
  1682. {
  1683. nicvf_remove(pdev);
  1684. }
  1685. static struct pci_driver nicvf_driver = {
  1686. .name = DRV_NAME,
  1687. .id_table = nicvf_id_table,
  1688. .probe = nicvf_probe,
  1689. .remove = nicvf_remove,
  1690. .shutdown = nicvf_shutdown,
  1691. };
  1692. static int __init nicvf_init_module(void)
  1693. {
  1694. pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
  1695. return pci_register_driver(&nicvf_driver);
  1696. }
  1697. static void __exit nicvf_cleanup_module(void)
  1698. {
  1699. pci_unregister_driver(&nicvf_driver);
  1700. }
  1701. module_init(nicvf_init_module);
  1702. module_exit(nicvf_cleanup_module);