mpt2sas_base.c 138 KB

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  1. /*
  2. * This is the Fusion MPT base driver providing common API layer interface
  3. * for access to MPT (Message Passing Technology) firmware.
  4. *
  5. * This code is based on drivers/scsi/mpt2sas/mpt2_base.c
  6. * Copyright (C) 2007-2014 LSI Corporation
  7. * Copyright (C) 20013-2014 Avago Technologies
  8. * (mailto: MPT-FusionLinux.pdl@avagotech.com)
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * as published by the Free Software Foundation; either version 2
  13. * of the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * NO WARRANTY
  21. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25. * solely responsible for determining the appropriateness of using and
  26. * distributing the Program and assumes all risks associated with its
  27. * exercise of rights under this Agreement, including but not limited to
  28. * the risks and costs of program errors, damage to or loss of data,
  29. * programs or equipment, and unavailability or interruption of operations.
  30. * DISCLAIMER OF LIABILITY
  31. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  32. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  34. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  35. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  36. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  37. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  38. * You should have received a copy of the GNU General Public License
  39. * along with this program; if not, write to the Free Software
  40. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  41. * USA.
  42. */
  43. #include <linux/kernel.h>
  44. #include <linux/module.h>
  45. #include <linux/errno.h>
  46. #include <linux/init.h>
  47. #include <linux/slab.h>
  48. #include <linux/types.h>
  49. #include <linux/pci.h>
  50. #include <linux/kdev_t.h>
  51. #include <linux/blkdev.h>
  52. #include <linux/delay.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/dma-mapping.h>
  55. #include <linux/sort.h>
  56. #include <linux/io.h>
  57. #include <linux/time.h>
  58. #include <linux/kthread.h>
  59. #include <linux/aer.h>
  60. #include "mpt2sas_base.h"
  61. static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
  62. #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  63. #define MAX_HBA_QUEUE_DEPTH 30000
  64. #define MAX_CHAIN_DEPTH 100000
  65. static int max_queue_depth = -1;
  66. module_param(max_queue_depth, int, 0);
  67. MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  68. static int max_sgl_entries = -1;
  69. module_param(max_sgl_entries, int, 0);
  70. MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  71. static int msix_disable = -1;
  72. module_param(msix_disable, int, 0);
  73. MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  74. static int max_msix_vectors = -1;
  75. module_param(max_msix_vectors, int, 0);
  76. MODULE_PARM_DESC(max_msix_vectors, " max msix vectors ");
  77. static int mpt2sas_fwfault_debug;
  78. MODULE_PARM_DESC(mpt2sas_fwfault_debug, " enable detection of firmware fault "
  79. "and halt firmware - (default=0)");
  80. static int disable_discovery = -1;
  81. module_param(disable_discovery, int, 0);
  82. MODULE_PARM_DESC(disable_discovery, " disable discovery ");
  83. static int
  84. _base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag);
  85. static int
  86. _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag);
  87. /**
  88. * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
  89. *
  90. */
  91. static int
  92. _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
  93. {
  94. int ret = param_set_int(val, kp);
  95. struct MPT2SAS_ADAPTER *ioc;
  96. if (ret)
  97. return ret;
  98. /* global ioc spinlock to protect controller list on list operations */
  99. printk(KERN_INFO "setting fwfault_debug(%d)\n", mpt2sas_fwfault_debug);
  100. spin_lock(&gioc_lock);
  101. list_for_each_entry(ioc, &mpt2sas_ioc_list, list)
  102. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  103. spin_unlock(&gioc_lock);
  104. return 0;
  105. }
  106. module_param_call(mpt2sas_fwfault_debug, _scsih_set_fwfault_debug,
  107. param_get_int, &mpt2sas_fwfault_debug, 0644);
  108. /**
  109. * mpt2sas_remove_dead_ioc_func - kthread context to remove dead ioc
  110. * @arg: input argument, used to derive ioc
  111. *
  112. * Return 0 if controller is removed from pci subsystem.
  113. * Return -1 for other case.
  114. */
  115. static int mpt2sas_remove_dead_ioc_func(void *arg)
  116. {
  117. struct MPT2SAS_ADAPTER *ioc = (struct MPT2SAS_ADAPTER *)arg;
  118. struct pci_dev *pdev;
  119. if ((ioc == NULL))
  120. return -1;
  121. pdev = ioc->pdev;
  122. if ((pdev == NULL))
  123. return -1;
  124. pci_stop_and_remove_bus_device_locked(pdev);
  125. return 0;
  126. }
  127. /**
  128. * _base_fault_reset_work - workq handling ioc fault conditions
  129. * @work: input argument, used to derive ioc
  130. * Context: sleep.
  131. *
  132. * Return nothing.
  133. */
  134. static void
  135. _base_fault_reset_work(struct work_struct *work)
  136. {
  137. struct MPT2SAS_ADAPTER *ioc =
  138. container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work);
  139. unsigned long flags;
  140. u32 doorbell;
  141. int rc;
  142. struct task_struct *p;
  143. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  144. if (ioc->shost_recovery || ioc->pci_error_recovery)
  145. goto rearm_timer;
  146. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  147. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  148. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
  149. printk(MPT2SAS_INFO_FMT "%s : SAS host is non-operational !!!!\n",
  150. ioc->name, __func__);
  151. /* It may be possible that EEH recovery can resolve some of
  152. * pci bus failure issues rather removing the dead ioc function
  153. * by considering controller is in a non-operational state. So
  154. * here priority is given to the EEH recovery. If it doesn't
  155. * not resolve this issue, mpt2sas driver will consider this
  156. * controller to non-operational state and remove the dead ioc
  157. * function.
  158. */
  159. if (ioc->non_operational_loop++ < 5) {
  160. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
  161. flags);
  162. goto rearm_timer;
  163. }
  164. /*
  165. * Call _scsih_flush_pending_cmds callback so that we flush all
  166. * pending commands back to OS. This call is required to aovid
  167. * deadlock at block layer. Dead IOC will fail to do diag reset,
  168. * and this call is safe since dead ioc will never return any
  169. * command back from HW.
  170. */
  171. ioc->schedule_dead_ioc_flush_running_cmds(ioc);
  172. /*
  173. * Set remove_host flag early since kernel thread will
  174. * take some time to execute.
  175. */
  176. ioc->remove_host = 1;
  177. /*Remove the Dead Host */
  178. p = kthread_run(mpt2sas_remove_dead_ioc_func, ioc,
  179. "mpt2sas_dead_ioc_%d", ioc->id);
  180. if (IS_ERR(p)) {
  181. printk(MPT2SAS_ERR_FMT
  182. "%s: Running mpt2sas_dead_ioc thread failed !!!!\n",
  183. ioc->name, __func__);
  184. } else {
  185. printk(MPT2SAS_ERR_FMT
  186. "%s: Running mpt2sas_dead_ioc thread success !!!!\n",
  187. ioc->name, __func__);
  188. }
  189. return; /* don't rearm timer */
  190. }
  191. ioc->non_operational_loop = 0;
  192. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  193. rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  194. FORCE_BIG_HAMMER);
  195. printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name,
  196. __func__, (rc == 0) ? "success" : "failed");
  197. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  198. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  199. mpt2sas_base_fault_info(ioc, doorbell &
  200. MPI2_DOORBELL_DATA_MASK);
  201. }
  202. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  203. rearm_timer:
  204. if (ioc->fault_reset_work_q)
  205. queue_delayed_work(ioc->fault_reset_work_q,
  206. &ioc->fault_reset_work,
  207. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  208. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  209. }
  210. /**
  211. * mpt2sas_base_start_watchdog - start the fault_reset_work_q
  212. * @ioc: per adapter object
  213. * Context: sleep.
  214. *
  215. * Return nothing.
  216. */
  217. void
  218. mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc)
  219. {
  220. unsigned long flags;
  221. if (ioc->fault_reset_work_q)
  222. return;
  223. /* initialize fault polling */
  224. INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
  225. snprintf(ioc->fault_reset_work_q_name,
  226. sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
  227. ioc->fault_reset_work_q =
  228. create_singlethread_workqueue(ioc->fault_reset_work_q_name);
  229. if (!ioc->fault_reset_work_q) {
  230. printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n",
  231. ioc->name, __func__, __LINE__);
  232. return;
  233. }
  234. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  235. if (ioc->fault_reset_work_q)
  236. queue_delayed_work(ioc->fault_reset_work_q,
  237. &ioc->fault_reset_work,
  238. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  239. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  240. }
  241. /**
  242. * mpt2sas_base_stop_watchdog - stop the fault_reset_work_q
  243. * @ioc: per adapter object
  244. * Context: sleep.
  245. *
  246. * Return nothing.
  247. */
  248. void
  249. mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc)
  250. {
  251. unsigned long flags;
  252. struct workqueue_struct *wq;
  253. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  254. wq = ioc->fault_reset_work_q;
  255. ioc->fault_reset_work_q = NULL;
  256. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  257. if (wq) {
  258. if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
  259. flush_workqueue(wq);
  260. destroy_workqueue(wq);
  261. }
  262. }
  263. /**
  264. * mpt2sas_base_fault_info - verbose translation of firmware FAULT code
  265. * @ioc: per adapter object
  266. * @fault_code: fault code
  267. *
  268. * Return nothing.
  269. */
  270. void
  271. mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code)
  272. {
  273. printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n",
  274. ioc->name, fault_code);
  275. }
  276. /**
  277. * mpt2sas_halt_firmware - halt's mpt controller firmware
  278. * @ioc: per adapter object
  279. *
  280. * For debugging timeout related issues. Writing 0xCOFFEE00
  281. * to the doorbell register will halt controller firmware. With
  282. * the purpose to stop both driver and firmware, the enduser can
  283. * obtain a ring buffer from controller UART.
  284. */
  285. void
  286. mpt2sas_halt_firmware(struct MPT2SAS_ADAPTER *ioc)
  287. {
  288. u32 doorbell;
  289. if (!ioc->fwfault_debug)
  290. return;
  291. dump_stack();
  292. doorbell = readl(&ioc->chip->Doorbell);
  293. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  294. mpt2sas_base_fault_info(ioc , doorbell);
  295. else {
  296. writel(0xC0FFEE00, &ioc->chip->Doorbell);
  297. printk(MPT2SAS_ERR_FMT "Firmware is halted due to command "
  298. "timeout\n", ioc->name);
  299. }
  300. panic("panic in %s\n", __func__);
  301. }
  302. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  303. /**
  304. * _base_sas_ioc_info - verbose translation of the ioc status
  305. * @ioc: per adapter object
  306. * @mpi_reply: reply mf payload returned from firmware
  307. * @request_hdr: request mf
  308. *
  309. * Return nothing.
  310. */
  311. static void
  312. _base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
  313. MPI2RequestHeader_t *request_hdr)
  314. {
  315. u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
  316. MPI2_IOCSTATUS_MASK;
  317. char *desc = NULL;
  318. u16 frame_sz;
  319. char *func_str = NULL;
  320. /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
  321. if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
  322. request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
  323. request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
  324. return;
  325. if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
  326. return;
  327. switch (ioc_status) {
  328. /****************************************************************************
  329. * Common IOCStatus values for all replies
  330. ****************************************************************************/
  331. case MPI2_IOCSTATUS_INVALID_FUNCTION:
  332. desc = "invalid function";
  333. break;
  334. case MPI2_IOCSTATUS_BUSY:
  335. desc = "busy";
  336. break;
  337. case MPI2_IOCSTATUS_INVALID_SGL:
  338. desc = "invalid sgl";
  339. break;
  340. case MPI2_IOCSTATUS_INTERNAL_ERROR:
  341. desc = "internal error";
  342. break;
  343. case MPI2_IOCSTATUS_INVALID_VPID:
  344. desc = "invalid vpid";
  345. break;
  346. case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
  347. desc = "insufficient resources";
  348. break;
  349. case MPI2_IOCSTATUS_INVALID_FIELD:
  350. desc = "invalid field";
  351. break;
  352. case MPI2_IOCSTATUS_INVALID_STATE:
  353. desc = "invalid state";
  354. break;
  355. case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
  356. desc = "op state not supported";
  357. break;
  358. /****************************************************************************
  359. * Config IOCStatus values
  360. ****************************************************************************/
  361. case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
  362. desc = "config invalid action";
  363. break;
  364. case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
  365. desc = "config invalid type";
  366. break;
  367. case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
  368. desc = "config invalid page";
  369. break;
  370. case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
  371. desc = "config invalid data";
  372. break;
  373. case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
  374. desc = "config no defaults";
  375. break;
  376. case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
  377. desc = "config cant commit";
  378. break;
  379. /****************************************************************************
  380. * SCSI IO Reply
  381. ****************************************************************************/
  382. case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
  383. case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
  384. case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
  385. case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
  386. case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
  387. case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
  388. case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
  389. case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
  390. case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
  391. case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
  392. case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
  393. case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
  394. break;
  395. /****************************************************************************
  396. * For use by SCSI Initiator and SCSI Target end-to-end data protection
  397. ****************************************************************************/
  398. case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
  399. desc = "eedp guard error";
  400. break;
  401. case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
  402. desc = "eedp ref tag error";
  403. break;
  404. case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
  405. desc = "eedp app tag error";
  406. break;
  407. /****************************************************************************
  408. * SCSI Target values
  409. ****************************************************************************/
  410. case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
  411. desc = "target invalid io index";
  412. break;
  413. case MPI2_IOCSTATUS_TARGET_ABORTED:
  414. desc = "target aborted";
  415. break;
  416. case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
  417. desc = "target no conn retryable";
  418. break;
  419. case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
  420. desc = "target no connection";
  421. break;
  422. case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
  423. desc = "target xfer count mismatch";
  424. break;
  425. case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
  426. desc = "target data offset error";
  427. break;
  428. case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
  429. desc = "target too much write data";
  430. break;
  431. case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
  432. desc = "target iu too short";
  433. break;
  434. case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
  435. desc = "target ack nak timeout";
  436. break;
  437. case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
  438. desc = "target nak received";
  439. break;
  440. /****************************************************************************
  441. * Serial Attached SCSI values
  442. ****************************************************************************/
  443. case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
  444. desc = "smp request failed";
  445. break;
  446. case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
  447. desc = "smp data overrun";
  448. break;
  449. /****************************************************************************
  450. * Diagnostic Buffer Post / Diagnostic Release values
  451. ****************************************************************************/
  452. case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
  453. desc = "diagnostic released";
  454. break;
  455. default:
  456. break;
  457. }
  458. if (!desc)
  459. return;
  460. switch (request_hdr->Function) {
  461. case MPI2_FUNCTION_CONFIG:
  462. frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
  463. func_str = "config_page";
  464. break;
  465. case MPI2_FUNCTION_SCSI_TASK_MGMT:
  466. frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
  467. func_str = "task_mgmt";
  468. break;
  469. case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
  470. frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
  471. func_str = "sas_iounit_ctl";
  472. break;
  473. case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
  474. frame_sz = sizeof(Mpi2SepRequest_t);
  475. func_str = "enclosure";
  476. break;
  477. case MPI2_FUNCTION_IOC_INIT:
  478. frame_sz = sizeof(Mpi2IOCInitRequest_t);
  479. func_str = "ioc_init";
  480. break;
  481. case MPI2_FUNCTION_PORT_ENABLE:
  482. frame_sz = sizeof(Mpi2PortEnableRequest_t);
  483. func_str = "port_enable";
  484. break;
  485. case MPI2_FUNCTION_SMP_PASSTHROUGH:
  486. frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
  487. func_str = "smp_passthru";
  488. break;
  489. default:
  490. frame_sz = 32;
  491. func_str = "unknown";
  492. break;
  493. }
  494. printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p),"
  495. " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str);
  496. _debug_dump_mf(request_hdr, frame_sz/4);
  497. }
  498. /**
  499. * _base_display_event_data - verbose translation of firmware asyn events
  500. * @ioc: per adapter object
  501. * @mpi_reply: reply mf payload returned from firmware
  502. *
  503. * Return nothing.
  504. */
  505. static void
  506. _base_display_event_data(struct MPT2SAS_ADAPTER *ioc,
  507. Mpi2EventNotificationReply_t *mpi_reply)
  508. {
  509. char *desc = NULL;
  510. u16 event;
  511. if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
  512. return;
  513. event = le16_to_cpu(mpi_reply->Event);
  514. switch (event) {
  515. case MPI2_EVENT_LOG_DATA:
  516. desc = "Log Data";
  517. break;
  518. case MPI2_EVENT_STATE_CHANGE:
  519. desc = "Status Change";
  520. break;
  521. case MPI2_EVENT_HARD_RESET_RECEIVED:
  522. desc = "Hard Reset Received";
  523. break;
  524. case MPI2_EVENT_EVENT_CHANGE:
  525. desc = "Event Change";
  526. break;
  527. case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
  528. desc = "Device Status Change";
  529. break;
  530. case MPI2_EVENT_IR_OPERATION_STATUS:
  531. if (!ioc->hide_ir_msg)
  532. desc = "IR Operation Status";
  533. break;
  534. case MPI2_EVENT_SAS_DISCOVERY:
  535. {
  536. Mpi2EventDataSasDiscovery_t *event_data =
  537. (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
  538. printk(MPT2SAS_INFO_FMT "Discovery: (%s)", ioc->name,
  539. (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
  540. "start" : "stop");
  541. if (event_data->DiscoveryStatus)
  542. printk("discovery_status(0x%08x)",
  543. le32_to_cpu(event_data->DiscoveryStatus));
  544. printk("\n");
  545. return;
  546. }
  547. case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
  548. desc = "SAS Broadcast Primitive";
  549. break;
  550. case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  551. desc = "SAS Init Device Status Change";
  552. break;
  553. case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
  554. desc = "SAS Init Table Overflow";
  555. break;
  556. case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
  557. desc = "SAS Topology Change List";
  558. break;
  559. case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
  560. desc = "SAS Enclosure Device Status Change";
  561. break;
  562. case MPI2_EVENT_IR_VOLUME:
  563. if (!ioc->hide_ir_msg)
  564. desc = "IR Volume";
  565. break;
  566. case MPI2_EVENT_IR_PHYSICAL_DISK:
  567. if (!ioc->hide_ir_msg)
  568. desc = "IR Physical Disk";
  569. break;
  570. case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
  571. if (!ioc->hide_ir_msg)
  572. desc = "IR Configuration Change List";
  573. break;
  574. case MPI2_EVENT_LOG_ENTRY_ADDED:
  575. if (!ioc->hide_ir_msg)
  576. desc = "Log Entry Added";
  577. break;
  578. case MPI2_EVENT_TEMP_THRESHOLD:
  579. desc = "Temperature Threshold";
  580. break;
  581. }
  582. if (!desc)
  583. return;
  584. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc);
  585. }
  586. #endif
  587. /**
  588. * _base_sas_log_info - verbose translation of firmware log info
  589. * @ioc: per adapter object
  590. * @log_info: log info
  591. *
  592. * Return nothing.
  593. */
  594. static void
  595. _base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info)
  596. {
  597. union loginfo_type {
  598. u32 loginfo;
  599. struct {
  600. u32 subcode:16;
  601. u32 code:8;
  602. u32 originator:4;
  603. u32 bus_type:4;
  604. } dw;
  605. };
  606. union loginfo_type sas_loginfo;
  607. char *originator_str = NULL;
  608. sas_loginfo.loginfo = log_info;
  609. if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
  610. return;
  611. /* each nexus loss loginfo */
  612. if (log_info == 0x31170000)
  613. return;
  614. /* eat the loginfos associated with task aborts */
  615. if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
  616. 0x31140000 || log_info == 0x31130000))
  617. return;
  618. switch (sas_loginfo.dw.originator) {
  619. case 0:
  620. originator_str = "IOP";
  621. break;
  622. case 1:
  623. originator_str = "PL";
  624. break;
  625. case 2:
  626. if (!ioc->hide_ir_msg)
  627. originator_str = "IR";
  628. else
  629. originator_str = "WarpDrive";
  630. break;
  631. }
  632. printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), "
  633. "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info,
  634. originator_str, sas_loginfo.dw.code,
  635. sas_loginfo.dw.subcode);
  636. }
  637. /**
  638. * _base_display_reply_info -
  639. * @ioc: per adapter object
  640. * @smid: system request message index
  641. * @msix_index: MSIX table index supplied by the OS
  642. * @reply: reply message frame(lower 32bit addr)
  643. *
  644. * Return nothing.
  645. */
  646. static void
  647. _base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  648. u32 reply)
  649. {
  650. MPI2DefaultReply_t *mpi_reply;
  651. u16 ioc_status;
  652. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  653. if (unlikely(!mpi_reply)) {
  654. printk(MPT2SAS_ERR_FMT "mpi_reply not valid at %s:%d/%s()!\n",
  655. ioc->name, __FILE__, __LINE__, __func__);
  656. return;
  657. }
  658. ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
  659. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  660. if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
  661. (ioc->logging_level & MPT_DEBUG_REPLY)) {
  662. _base_sas_ioc_info(ioc , mpi_reply,
  663. mpt2sas_base_get_msg_frame(ioc, smid));
  664. }
  665. #endif
  666. if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
  667. _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo));
  668. }
  669. /**
  670. * mpt2sas_base_done - base internal command completion routine
  671. * @ioc: per adapter object
  672. * @smid: system request message index
  673. * @msix_index: MSIX table index supplied by the OS
  674. * @reply: reply message frame(lower 32bit addr)
  675. *
  676. * Return 1 meaning mf should be freed from _base_interrupt
  677. * 0 means the mf is freed from this function.
  678. */
  679. u8
  680. mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  681. u32 reply)
  682. {
  683. MPI2DefaultReply_t *mpi_reply;
  684. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  685. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  686. return 1;
  687. if (ioc->base_cmds.status == MPT2_CMD_NOT_USED)
  688. return 1;
  689. ioc->base_cmds.status |= MPT2_CMD_COMPLETE;
  690. if (mpi_reply) {
  691. ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID;
  692. memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  693. }
  694. ioc->base_cmds.status &= ~MPT2_CMD_PENDING;
  695. complete(&ioc->base_cmds.done);
  696. return 1;
  697. }
  698. /**
  699. * _base_async_event - main callback handler for firmware asyn events
  700. * @ioc: per adapter object
  701. * @msix_index: MSIX table index supplied by the OS
  702. * @reply: reply message frame(lower 32bit addr)
  703. *
  704. * Returns void.
  705. */
  706. static void
  707. _base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
  708. {
  709. Mpi2EventNotificationReply_t *mpi_reply;
  710. Mpi2EventAckRequest_t *ack_request;
  711. u16 smid;
  712. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  713. if (!mpi_reply)
  714. return;
  715. if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
  716. return;
  717. #ifdef CONFIG_SCSI_MPT2SAS_LOGGING
  718. _base_display_event_data(ioc, mpi_reply);
  719. #endif
  720. if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
  721. goto out;
  722. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  723. if (!smid) {
  724. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  725. ioc->name, __func__);
  726. goto out;
  727. }
  728. ack_request = mpt2sas_base_get_msg_frame(ioc, smid);
  729. memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
  730. ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
  731. ack_request->Event = mpi_reply->Event;
  732. ack_request->EventContext = mpi_reply->EventContext;
  733. ack_request->VF_ID = 0; /* TODO */
  734. ack_request->VP_ID = 0;
  735. mpt2sas_base_put_smid_default(ioc, smid);
  736. out:
  737. /* scsih callback handler */
  738. mpt2sas_scsih_event_callback(ioc, msix_index, reply);
  739. /* ctl callback handler */
  740. mpt2sas_ctl_event_callback(ioc, msix_index, reply);
  741. return;
  742. }
  743. /**
  744. * _base_get_cb_idx - obtain the callback index
  745. * @ioc: per adapter object
  746. * @smid: system request message index
  747. *
  748. * Return callback index.
  749. */
  750. static u8
  751. _base_get_cb_idx(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  752. {
  753. int i;
  754. u8 cb_idx;
  755. if (smid < ioc->hi_priority_smid) {
  756. i = smid - 1;
  757. cb_idx = ioc->scsi_lookup[i].cb_idx;
  758. } else if (smid < ioc->internal_smid) {
  759. i = smid - ioc->hi_priority_smid;
  760. cb_idx = ioc->hpr_lookup[i].cb_idx;
  761. } else if (smid <= ioc->hba_queue_depth) {
  762. i = smid - ioc->internal_smid;
  763. cb_idx = ioc->internal_lookup[i].cb_idx;
  764. } else
  765. cb_idx = 0xFF;
  766. return cb_idx;
  767. }
  768. /**
  769. * _base_mask_interrupts - disable interrupts
  770. * @ioc: per adapter object
  771. *
  772. * Disabling ResetIRQ, Reply and Doorbell Interrupts
  773. *
  774. * Return nothing.
  775. */
  776. static void
  777. _base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  778. {
  779. u32 him_register;
  780. ioc->mask_interrupts = 1;
  781. him_register = readl(&ioc->chip->HostInterruptMask);
  782. him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
  783. writel(him_register, &ioc->chip->HostInterruptMask);
  784. readl(&ioc->chip->HostInterruptMask);
  785. }
  786. /**
  787. * _base_unmask_interrupts - enable interrupts
  788. * @ioc: per adapter object
  789. *
  790. * Enabling only Reply Interrupts
  791. *
  792. * Return nothing.
  793. */
  794. static void
  795. _base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc)
  796. {
  797. u32 him_register;
  798. him_register = readl(&ioc->chip->HostInterruptMask);
  799. him_register &= ~MPI2_HIM_RIM;
  800. writel(him_register, &ioc->chip->HostInterruptMask);
  801. ioc->mask_interrupts = 0;
  802. }
  803. union reply_descriptor {
  804. u64 word;
  805. struct {
  806. u32 low;
  807. u32 high;
  808. } u;
  809. };
  810. /**
  811. * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
  812. * @irq: irq number (not used)
  813. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  814. * @r: pt_regs pointer (not used)
  815. *
  816. * Return IRQ_HANDLE if processed, else IRQ_NONE.
  817. */
  818. static irqreturn_t
  819. _base_interrupt(int irq, void *bus_id)
  820. {
  821. struct adapter_reply_queue *reply_q = bus_id;
  822. union reply_descriptor rd;
  823. u32 completed_cmds;
  824. u8 request_desript_type;
  825. u16 smid;
  826. u8 cb_idx;
  827. u32 reply;
  828. u8 msix_index = reply_q->msix_index;
  829. struct MPT2SAS_ADAPTER *ioc = reply_q->ioc;
  830. Mpi2ReplyDescriptorsUnion_t *rpf;
  831. u8 rc;
  832. if (ioc->mask_interrupts)
  833. return IRQ_NONE;
  834. if (!atomic_add_unless(&reply_q->busy, 1, 1))
  835. return IRQ_NONE;
  836. rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
  837. request_desript_type = rpf->Default.ReplyFlags
  838. & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  839. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
  840. atomic_dec(&reply_q->busy);
  841. return IRQ_NONE;
  842. }
  843. completed_cmds = 0;
  844. cb_idx = 0xFF;
  845. do {
  846. rd.word = le64_to_cpu(rpf->Words);
  847. if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
  848. goto out;
  849. reply = 0;
  850. smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
  851. if (request_desript_type ==
  852. MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
  853. reply = le32_to_cpu
  854. (rpf->AddressReply.ReplyFrameAddress);
  855. if (reply > ioc->reply_dma_max_address ||
  856. reply < ioc->reply_dma_min_address)
  857. reply = 0;
  858. } else if (request_desript_type ==
  859. MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER)
  860. goto next;
  861. else if (request_desript_type ==
  862. MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS)
  863. goto next;
  864. if (smid) {
  865. cb_idx = _base_get_cb_idx(ioc, smid);
  866. if ((likely(cb_idx < MPT_MAX_CALLBACKS))
  867. && (likely(mpt_callbacks[cb_idx] != NULL))) {
  868. rc = mpt_callbacks[cb_idx](ioc, smid,
  869. msix_index, reply);
  870. if (reply)
  871. _base_display_reply_info(ioc, smid,
  872. msix_index, reply);
  873. if (rc)
  874. mpt2sas_base_free_smid(ioc, smid);
  875. }
  876. }
  877. if (!smid)
  878. _base_async_event(ioc, msix_index, reply);
  879. /* reply free queue handling */
  880. if (reply) {
  881. ioc->reply_free_host_index =
  882. (ioc->reply_free_host_index ==
  883. (ioc->reply_free_queue_depth - 1)) ?
  884. 0 : ioc->reply_free_host_index + 1;
  885. ioc->reply_free[ioc->reply_free_host_index] =
  886. cpu_to_le32(reply);
  887. wmb();
  888. writel(ioc->reply_free_host_index,
  889. &ioc->chip->ReplyFreeHostIndex);
  890. }
  891. next:
  892. rpf->Words = cpu_to_le64(ULLONG_MAX);
  893. reply_q->reply_post_host_index =
  894. (reply_q->reply_post_host_index ==
  895. (ioc->reply_post_queue_depth - 1)) ? 0 :
  896. reply_q->reply_post_host_index + 1;
  897. request_desript_type =
  898. reply_q->reply_post_free[reply_q->reply_post_host_index].
  899. Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  900. completed_cmds++;
  901. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  902. goto out;
  903. if (!reply_q->reply_post_host_index)
  904. rpf = reply_q->reply_post_free;
  905. else
  906. rpf++;
  907. } while (1);
  908. out:
  909. if (!completed_cmds) {
  910. atomic_dec(&reply_q->busy);
  911. return IRQ_NONE;
  912. }
  913. wmb();
  914. if (ioc->is_warpdrive) {
  915. writel(reply_q->reply_post_host_index,
  916. ioc->reply_post_host_index[msix_index]);
  917. atomic_dec(&reply_q->busy);
  918. return IRQ_HANDLED;
  919. }
  920. writel(reply_q->reply_post_host_index | (msix_index <<
  921. MPI2_RPHI_MSIX_INDEX_SHIFT), &ioc->chip->ReplyPostHostIndex);
  922. atomic_dec(&reply_q->busy);
  923. return IRQ_HANDLED;
  924. }
  925. /**
  926. * _base_is_controller_msix_enabled - is controller support muli-reply queues
  927. * @ioc: per adapter object
  928. *
  929. */
  930. static inline int
  931. _base_is_controller_msix_enabled(struct MPT2SAS_ADAPTER *ioc)
  932. {
  933. return (ioc->facts.IOCCapabilities &
  934. MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
  935. }
  936. /**
  937. * mpt2sas_base_flush_reply_queues - flushing the MSIX reply queues
  938. * @ioc: per adapter object
  939. * Context: ISR conext
  940. *
  941. * Called when a Task Management request has completed. We want
  942. * to flush the other reply queues so all the outstanding IO has been
  943. * completed back to OS before we process the TM completetion.
  944. *
  945. * Return nothing.
  946. */
  947. void
  948. mpt2sas_base_flush_reply_queues(struct MPT2SAS_ADAPTER *ioc)
  949. {
  950. struct adapter_reply_queue *reply_q;
  951. /* If MSIX capability is turned off
  952. * then multi-queues are not enabled
  953. */
  954. if (!_base_is_controller_msix_enabled(ioc))
  955. return;
  956. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  957. if (ioc->shost_recovery)
  958. return;
  959. /* TMs are on msix_index == 0 */
  960. if (reply_q->msix_index == 0)
  961. continue;
  962. _base_interrupt(reply_q->vector, (void *)reply_q);
  963. }
  964. }
  965. /**
  966. * mpt2sas_base_release_callback_handler - clear interrupt callback handler
  967. * @cb_idx: callback index
  968. *
  969. * Return nothing.
  970. */
  971. void
  972. mpt2sas_base_release_callback_handler(u8 cb_idx)
  973. {
  974. mpt_callbacks[cb_idx] = NULL;
  975. }
  976. /**
  977. * mpt2sas_base_register_callback_handler - obtain index for the interrupt callback handler
  978. * @cb_func: callback function
  979. *
  980. * Returns cb_func.
  981. */
  982. u8
  983. mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func)
  984. {
  985. u8 cb_idx;
  986. for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
  987. if (mpt_callbacks[cb_idx] == NULL)
  988. break;
  989. mpt_callbacks[cb_idx] = cb_func;
  990. return cb_idx;
  991. }
  992. /**
  993. * mpt2sas_base_initialize_callback_handler - initialize the interrupt callback handler
  994. *
  995. * Return nothing.
  996. */
  997. void
  998. mpt2sas_base_initialize_callback_handler(void)
  999. {
  1000. u8 cb_idx;
  1001. for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
  1002. mpt2sas_base_release_callback_handler(cb_idx);
  1003. }
  1004. /**
  1005. * mpt2sas_base_build_zero_len_sge - build zero length sg entry
  1006. * @ioc: per adapter object
  1007. * @paddr: virtual address for SGE
  1008. *
  1009. * Create a zero length scatter gather entry to insure the IOCs hardware has
  1010. * something to use if the target device goes brain dead and tries
  1011. * to send data even when none is asked for.
  1012. *
  1013. * Return nothing.
  1014. */
  1015. void
  1016. mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr)
  1017. {
  1018. u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
  1019. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
  1020. MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
  1021. MPI2_SGE_FLAGS_SHIFT);
  1022. ioc->base_add_sg_single(paddr, flags_length, -1);
  1023. }
  1024. /**
  1025. * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
  1026. * @paddr: virtual address for SGE
  1027. * @flags_length: SGE flags and data transfer length
  1028. * @dma_addr: Physical address
  1029. *
  1030. * Return nothing.
  1031. */
  1032. static void
  1033. _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  1034. {
  1035. Mpi2SGESimple32_t *sgel = paddr;
  1036. flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
  1037. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  1038. sgel->FlagsLength = cpu_to_le32(flags_length);
  1039. sgel->Address = cpu_to_le32(dma_addr);
  1040. }
  1041. /**
  1042. * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
  1043. * @paddr: virtual address for SGE
  1044. * @flags_length: SGE flags and data transfer length
  1045. * @dma_addr: Physical address
  1046. *
  1047. * Return nothing.
  1048. */
  1049. static void
  1050. _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  1051. {
  1052. Mpi2SGESimple64_t *sgel = paddr;
  1053. flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
  1054. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  1055. sgel->FlagsLength = cpu_to_le32(flags_length);
  1056. sgel->Address = cpu_to_le64(dma_addr);
  1057. }
  1058. #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
  1059. /**
  1060. * _base_config_dma_addressing - set dma addressing
  1061. * @ioc: per adapter object
  1062. * @pdev: PCI device struct
  1063. *
  1064. * Returns 0 for success, non-zero for failure.
  1065. */
  1066. static int
  1067. _base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev)
  1068. {
  1069. struct sysinfo s;
  1070. u64 consistent_dma_mask;
  1071. if (ioc->dma_mask)
  1072. consistent_dma_mask = DMA_BIT_MASK(64);
  1073. else
  1074. consistent_dma_mask = DMA_BIT_MASK(32);
  1075. if (sizeof(dma_addr_t) > 4) {
  1076. const uint64_t required_mask =
  1077. dma_get_required_mask(&pdev->dev);
  1078. if ((required_mask > DMA_BIT_MASK(32)) &&
  1079. !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
  1080. !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
  1081. ioc->base_add_sg_single = &_base_add_sg_single_64;
  1082. ioc->sge_size = sizeof(Mpi2SGESimple64_t);
  1083. ioc->dma_mask = 64;
  1084. goto out;
  1085. }
  1086. }
  1087. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  1088. && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  1089. ioc->base_add_sg_single = &_base_add_sg_single_32;
  1090. ioc->sge_size = sizeof(Mpi2SGESimple32_t);
  1091. ioc->dma_mask = 32;
  1092. } else
  1093. return -ENODEV;
  1094. out:
  1095. si_meminfo(&s);
  1096. printk(MPT2SAS_INFO_FMT
  1097. "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
  1098. ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
  1099. return 0;
  1100. }
  1101. static int
  1102. _base_change_consistent_dma_mask(struct MPT2SAS_ADAPTER *ioc,
  1103. struct pci_dev *pdev)
  1104. {
  1105. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
  1106. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
  1107. return -ENODEV;
  1108. }
  1109. return 0;
  1110. }
  1111. /**
  1112. * _base_check_enable_msix - checks MSIX capabable.
  1113. * @ioc: per adapter object
  1114. *
  1115. * Check to see if card is capable of MSIX, and set number
  1116. * of available msix vectors
  1117. */
  1118. static int
  1119. _base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  1120. {
  1121. int base;
  1122. u16 message_control;
  1123. /* Check whether controller SAS2008 B0 controller,
  1124. if it is SAS2008 B0 controller use IO-APIC instead of MSIX */
  1125. if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
  1126. ioc->pdev->revision == 0x01) {
  1127. return -EINVAL;
  1128. }
  1129. base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
  1130. if (!base) {
  1131. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not "
  1132. "supported\n", ioc->name));
  1133. return -EINVAL;
  1134. }
  1135. /* get msix vector count */
  1136. /* NUMA_IO not supported for older controllers */
  1137. if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
  1138. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
  1139. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
  1140. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
  1141. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
  1142. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
  1143. ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
  1144. ioc->msix_vector_count = 1;
  1145. else {
  1146. pci_read_config_word(ioc->pdev, base + 2, &message_control);
  1147. ioc->msix_vector_count = (message_control & 0x3FF) + 1;
  1148. }
  1149. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, "
  1150. "vector_count(%d)\n", ioc->name, ioc->msix_vector_count));
  1151. return 0;
  1152. }
  1153. /**
  1154. * _base_free_irq - free irq
  1155. * @ioc: per adapter object
  1156. *
  1157. * Freeing respective reply_queue from the list.
  1158. */
  1159. static void
  1160. _base_free_irq(struct MPT2SAS_ADAPTER *ioc)
  1161. {
  1162. struct adapter_reply_queue *reply_q, *next;
  1163. if (list_empty(&ioc->reply_queue_list))
  1164. return;
  1165. list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
  1166. list_del(&reply_q->list);
  1167. irq_set_affinity_hint(reply_q->vector, NULL);
  1168. free_cpumask_var(reply_q->affinity_hint);
  1169. synchronize_irq(reply_q->vector);
  1170. free_irq(reply_q->vector, reply_q);
  1171. kfree(reply_q);
  1172. }
  1173. }
  1174. /**
  1175. * _base_request_irq - request irq
  1176. * @ioc: per adapter object
  1177. * @index: msix index into vector table
  1178. * @vector: irq vector
  1179. *
  1180. * Inserting respective reply_queue into the list.
  1181. */
  1182. static int
  1183. _base_request_irq(struct MPT2SAS_ADAPTER *ioc, u8 index, u32 vector)
  1184. {
  1185. struct adapter_reply_queue *reply_q;
  1186. int r;
  1187. reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
  1188. if (!reply_q) {
  1189. printk(MPT2SAS_ERR_FMT "unable to allocate memory %d!\n",
  1190. ioc->name, (int)sizeof(struct adapter_reply_queue));
  1191. return -ENOMEM;
  1192. }
  1193. reply_q->ioc = ioc;
  1194. reply_q->msix_index = index;
  1195. reply_q->vector = vector;
  1196. if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL))
  1197. return -ENOMEM;
  1198. cpumask_clear(reply_q->affinity_hint);
  1199. atomic_set(&reply_q->busy, 0);
  1200. if (ioc->msix_enable)
  1201. snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
  1202. MPT2SAS_DRIVER_NAME, ioc->id, index);
  1203. else
  1204. snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
  1205. MPT2SAS_DRIVER_NAME, ioc->id);
  1206. r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
  1207. reply_q);
  1208. if (r) {
  1209. printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n",
  1210. reply_q->name, vector);
  1211. kfree(reply_q);
  1212. return -EBUSY;
  1213. }
  1214. INIT_LIST_HEAD(&reply_q->list);
  1215. list_add_tail(&reply_q->list, &ioc->reply_queue_list);
  1216. return 0;
  1217. }
  1218. /**
  1219. * _base_assign_reply_queues - assigning msix index for each cpu
  1220. * @ioc: per adapter object
  1221. *
  1222. * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
  1223. *
  1224. * It would nice if we could call irq_set_affinity, however it is not
  1225. * an exported symbol
  1226. */
  1227. static void
  1228. _base_assign_reply_queues(struct MPT2SAS_ADAPTER *ioc)
  1229. {
  1230. unsigned int cpu, nr_cpus, nr_msix, index = 0;
  1231. struct adapter_reply_queue *reply_q;
  1232. if (!_base_is_controller_msix_enabled(ioc))
  1233. return;
  1234. memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
  1235. nr_cpus = num_online_cpus();
  1236. nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
  1237. ioc->facts.MaxMSIxVectors);
  1238. if (!nr_msix)
  1239. return;
  1240. cpu = cpumask_first(cpu_online_mask);
  1241. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  1242. unsigned int i, group = nr_cpus / nr_msix;
  1243. if (cpu >= nr_cpus)
  1244. break;
  1245. if (index < nr_cpus % nr_msix)
  1246. group++;
  1247. for (i = 0 ; i < group ; i++) {
  1248. ioc->cpu_msix_table[cpu] = index;
  1249. cpumask_or(reply_q->affinity_hint,
  1250. reply_q->affinity_hint, get_cpu_mask(cpu));
  1251. cpu = cpumask_next(cpu, cpu_online_mask);
  1252. }
  1253. if (irq_set_affinity_hint(reply_q->vector,
  1254. reply_q->affinity_hint))
  1255. dinitprintk(ioc, pr_info(MPT2SAS_FMT
  1256. "error setting affinity hint for irq vector %d\n",
  1257. ioc->name, reply_q->vector));
  1258. index++;
  1259. }
  1260. }
  1261. /**
  1262. * _base_disable_msix - disables msix
  1263. * @ioc: per adapter object
  1264. *
  1265. */
  1266. static void
  1267. _base_disable_msix(struct MPT2SAS_ADAPTER *ioc)
  1268. {
  1269. if (ioc->msix_enable) {
  1270. pci_disable_msix(ioc->pdev);
  1271. ioc->msix_enable = 0;
  1272. }
  1273. }
  1274. /**
  1275. * _base_enable_msix - enables msix, failback to io_apic
  1276. * @ioc: per adapter object
  1277. *
  1278. */
  1279. static int
  1280. _base_enable_msix(struct MPT2SAS_ADAPTER *ioc)
  1281. {
  1282. struct msix_entry *entries, *a;
  1283. int r;
  1284. int i;
  1285. u8 try_msix = 0;
  1286. if (msix_disable == -1 || msix_disable == 0)
  1287. try_msix = 1;
  1288. if (!try_msix)
  1289. goto try_ioapic;
  1290. if (_base_check_enable_msix(ioc) != 0)
  1291. goto try_ioapic;
  1292. ioc->reply_queue_count = min_t(int, ioc->cpu_count,
  1293. ioc->msix_vector_count);
  1294. if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
  1295. max_msix_vectors = 8;
  1296. if (max_msix_vectors > 0) {
  1297. ioc->reply_queue_count = min_t(int, max_msix_vectors,
  1298. ioc->reply_queue_count);
  1299. ioc->msix_vector_count = ioc->reply_queue_count;
  1300. } else if (max_msix_vectors == 0)
  1301. goto try_ioapic;
  1302. printk(MPT2SAS_INFO_FMT
  1303. "MSI-X vectors supported: %d, no of cores: %d, max_msix_vectors: %d\n",
  1304. ioc->name, ioc->msix_vector_count, ioc->cpu_count, max_msix_vectors);
  1305. entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
  1306. GFP_KERNEL);
  1307. if (!entries) {
  1308. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "kcalloc "
  1309. "failed @ at %s:%d/%s() !!!\n", ioc->name, __FILE__,
  1310. __LINE__, __func__));
  1311. goto try_ioapic;
  1312. }
  1313. for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
  1314. a->entry = i;
  1315. r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
  1316. if (r) {
  1317. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT
  1318. "pci_enable_msix_exact failed (r=%d) !!!\n", ioc->name, r));
  1319. kfree(entries);
  1320. goto try_ioapic;
  1321. }
  1322. ioc->msix_enable = 1;
  1323. for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
  1324. r = _base_request_irq(ioc, i, a->vector);
  1325. if (r) {
  1326. _base_free_irq(ioc);
  1327. _base_disable_msix(ioc);
  1328. kfree(entries);
  1329. goto try_ioapic;
  1330. }
  1331. }
  1332. kfree(entries);
  1333. return 0;
  1334. /* failback to io_apic interrupt routing */
  1335. try_ioapic:
  1336. ioc->reply_queue_count = 1;
  1337. r = _base_request_irq(ioc, 0, ioc->pdev->irq);
  1338. return r;
  1339. }
  1340. /**
  1341. * mpt2sas_base_map_resources - map in controller resources (io/irq/memap)
  1342. * @ioc: per adapter object
  1343. *
  1344. * Returns 0 for success, non-zero for failure.
  1345. */
  1346. int
  1347. mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc)
  1348. {
  1349. struct pci_dev *pdev = ioc->pdev;
  1350. u32 memap_sz;
  1351. u32 pio_sz;
  1352. int i, r = 0;
  1353. u64 pio_chip = 0;
  1354. u64 chip_phys = 0;
  1355. struct adapter_reply_queue *reply_q;
  1356. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n",
  1357. ioc->name, __func__));
  1358. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1359. if (pci_enable_device_mem(pdev)) {
  1360. printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: "
  1361. "failed\n", ioc->name);
  1362. ioc->bars = 0;
  1363. return -ENODEV;
  1364. }
  1365. if (pci_request_selected_regions(pdev, ioc->bars,
  1366. MPT2SAS_DRIVER_NAME)) {
  1367. printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: "
  1368. "failed\n", ioc->name);
  1369. ioc->bars = 0;
  1370. r = -ENODEV;
  1371. goto out_fail;
  1372. }
  1373. /* AER (Advanced Error Reporting) hooks */
  1374. pci_enable_pcie_error_reporting(pdev);
  1375. pci_set_master(pdev);
  1376. if (_base_config_dma_addressing(ioc, pdev) != 0) {
  1377. printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n",
  1378. ioc->name, pci_name(pdev));
  1379. r = -ENODEV;
  1380. goto out_fail;
  1381. }
  1382. for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
  1383. (!memap_sz || !pio_sz); i++) {
  1384. if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  1385. if (pio_sz)
  1386. continue;
  1387. pio_chip = (u64)pci_resource_start(pdev, i);
  1388. pio_sz = pci_resource_len(pdev, i);
  1389. } else {
  1390. if (memap_sz)
  1391. continue;
  1392. /* verify memory resource is valid before using */
  1393. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  1394. ioc->chip_phys = pci_resource_start(pdev, i);
  1395. chip_phys = (u64)ioc->chip_phys;
  1396. memap_sz = pci_resource_len(pdev, i);
  1397. ioc->chip = ioremap(ioc->chip_phys, memap_sz);
  1398. }
  1399. }
  1400. }
  1401. if (ioc->chip == NULL) {
  1402. printk(MPT2SAS_ERR_FMT "unable to map adapter memory! "
  1403. "or resource not found\n", ioc->name);
  1404. r = -EINVAL;
  1405. goto out_fail;
  1406. }
  1407. _base_mask_interrupts(ioc);
  1408. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  1409. if (r)
  1410. goto out_fail;
  1411. if (!ioc->rdpq_array_enable_assigned) {
  1412. ioc->rdpq_array_enable = ioc->rdpq_array_capable;
  1413. ioc->rdpq_array_enable_assigned = 1;
  1414. }
  1415. r = _base_enable_msix(ioc);
  1416. if (r)
  1417. goto out_fail;
  1418. list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
  1419. printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n",
  1420. reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
  1421. "IO-APIC enabled"), reply_q->vector);
  1422. printk(MPT2SAS_INFO_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
  1423. ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
  1424. printk(MPT2SAS_INFO_FMT "ioport(0x%016llx), size(%d)\n",
  1425. ioc->name, (unsigned long long)pio_chip, pio_sz);
  1426. /* Save PCI configuration state for recovery from PCI AER/EEH errors */
  1427. pci_save_state(pdev);
  1428. return 0;
  1429. out_fail:
  1430. if (ioc->chip_phys)
  1431. iounmap(ioc->chip);
  1432. ioc->chip_phys = 0;
  1433. pci_release_selected_regions(ioc->pdev, ioc->bars);
  1434. pci_disable_pcie_error_reporting(pdev);
  1435. pci_disable_device(pdev);
  1436. return r;
  1437. }
  1438. /**
  1439. * mpt2sas_base_get_msg_frame - obtain request mf pointer
  1440. * @ioc: per adapter object
  1441. * @smid: system request message index(smid zero is invalid)
  1442. *
  1443. * Returns virt pointer to message frame.
  1444. */
  1445. void *
  1446. mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1447. {
  1448. return (void *)(ioc->request + (smid * ioc->request_sz));
  1449. }
  1450. /**
  1451. * mpt2sas_base_get_sense_buffer - obtain a sense buffer assigned to a mf request
  1452. * @ioc: per adapter object
  1453. * @smid: system request message index
  1454. *
  1455. * Returns virt pointer to sense buffer.
  1456. */
  1457. void *
  1458. mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1459. {
  1460. return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1461. }
  1462. /**
  1463. * mpt2sas_base_get_sense_buffer_dma - obtain a sense buffer assigned to a mf request
  1464. * @ioc: per adapter object
  1465. * @smid: system request message index
  1466. *
  1467. * Returns phys pointer to the low 32bit address of the sense buffer.
  1468. */
  1469. __le32
  1470. mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1471. {
  1472. return cpu_to_le32(ioc->sense_dma +
  1473. ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1474. }
  1475. /**
  1476. * mpt2sas_base_get_reply_virt_addr - obtain reply frames virt address
  1477. * @ioc: per adapter object
  1478. * @phys_addr: lower 32 physical addr of the reply
  1479. *
  1480. * Converts 32bit lower physical addr into a virt address.
  1481. */
  1482. void *
  1483. mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr)
  1484. {
  1485. if (!phys_addr)
  1486. return NULL;
  1487. return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
  1488. }
  1489. /**
  1490. * mpt2sas_base_get_smid - obtain a free smid from internal queue
  1491. * @ioc: per adapter object
  1492. * @cb_idx: callback index
  1493. *
  1494. * Returns smid (zero is invalid)
  1495. */
  1496. u16
  1497. mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1498. {
  1499. unsigned long flags;
  1500. struct request_tracker *request;
  1501. u16 smid;
  1502. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1503. if (list_empty(&ioc->internal_free_list)) {
  1504. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1505. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1506. ioc->name, __func__);
  1507. return 0;
  1508. }
  1509. request = list_entry(ioc->internal_free_list.next,
  1510. struct request_tracker, tracker_list);
  1511. request->cb_idx = cb_idx;
  1512. smid = request->smid;
  1513. list_del(&request->tracker_list);
  1514. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1515. return smid;
  1516. }
  1517. /**
  1518. * mpt2sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
  1519. * @ioc: per adapter object
  1520. * @cb_idx: callback index
  1521. * @scmd: pointer to scsi command object
  1522. *
  1523. * Returns smid (zero is invalid)
  1524. */
  1525. u16
  1526. mpt2sas_base_get_smid_scsiio(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx,
  1527. struct scsi_cmnd *scmd)
  1528. {
  1529. unsigned long flags;
  1530. struct scsiio_tracker *request;
  1531. u16 smid;
  1532. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1533. if (list_empty(&ioc->free_list)) {
  1534. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1535. printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
  1536. ioc->name, __func__);
  1537. return 0;
  1538. }
  1539. request = list_entry(ioc->free_list.next,
  1540. struct scsiio_tracker, tracker_list);
  1541. request->scmd = scmd;
  1542. request->cb_idx = cb_idx;
  1543. smid = request->smid;
  1544. list_del(&request->tracker_list);
  1545. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1546. return smid;
  1547. }
  1548. /**
  1549. * mpt2sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
  1550. * @ioc: per adapter object
  1551. * @cb_idx: callback index
  1552. *
  1553. * Returns smid (zero is invalid)
  1554. */
  1555. u16
  1556. mpt2sas_base_get_smid_hpr(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
  1557. {
  1558. unsigned long flags;
  1559. struct request_tracker *request;
  1560. u16 smid;
  1561. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1562. if (list_empty(&ioc->hpr_free_list)) {
  1563. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1564. return 0;
  1565. }
  1566. request = list_entry(ioc->hpr_free_list.next,
  1567. struct request_tracker, tracker_list);
  1568. request->cb_idx = cb_idx;
  1569. smid = request->smid;
  1570. list_del(&request->tracker_list);
  1571. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1572. return smid;
  1573. }
  1574. /**
  1575. * mpt2sas_base_free_smid - put smid back on free_list
  1576. * @ioc: per adapter object
  1577. * @smid: system request message index
  1578. *
  1579. * Return nothing.
  1580. */
  1581. void
  1582. mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1583. {
  1584. unsigned long flags;
  1585. int i;
  1586. struct chain_tracker *chain_req, *next;
  1587. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1588. if (smid < ioc->hi_priority_smid) {
  1589. /* scsiio queue */
  1590. i = smid - 1;
  1591. if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
  1592. list_for_each_entry_safe(chain_req, next,
  1593. &ioc->scsi_lookup[i].chain_list, tracker_list) {
  1594. list_del_init(&chain_req->tracker_list);
  1595. list_add(&chain_req->tracker_list,
  1596. &ioc->free_chain_list);
  1597. }
  1598. }
  1599. ioc->scsi_lookup[i].cb_idx = 0xFF;
  1600. ioc->scsi_lookup[i].scmd = NULL;
  1601. ioc->scsi_lookup[i].direct_io = 0;
  1602. list_add(&ioc->scsi_lookup[i].tracker_list,
  1603. &ioc->free_list);
  1604. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1605. /*
  1606. * See _wait_for_commands_to_complete() call with regards
  1607. * to this code.
  1608. */
  1609. if (ioc->shost_recovery && ioc->pending_io_count) {
  1610. if (ioc->pending_io_count == 1)
  1611. wake_up(&ioc->reset_wq);
  1612. ioc->pending_io_count--;
  1613. }
  1614. return;
  1615. } else if (smid < ioc->internal_smid) {
  1616. /* hi-priority */
  1617. i = smid - ioc->hi_priority_smid;
  1618. ioc->hpr_lookup[i].cb_idx = 0xFF;
  1619. list_add(&ioc->hpr_lookup[i].tracker_list,
  1620. &ioc->hpr_free_list);
  1621. } else if (smid <= ioc->hba_queue_depth) {
  1622. /* internal queue */
  1623. i = smid - ioc->internal_smid;
  1624. ioc->internal_lookup[i].cb_idx = 0xFF;
  1625. list_add(&ioc->internal_lookup[i].tracker_list,
  1626. &ioc->internal_free_list);
  1627. }
  1628. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1629. }
  1630. /**
  1631. * _base_writeq - 64 bit write to MMIO
  1632. * @ioc: per adapter object
  1633. * @b: data payload
  1634. * @addr: address in MMIO space
  1635. * @writeq_lock: spin lock
  1636. *
  1637. * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
  1638. * care of 32 bit environment where its not quarenteed to send the entire word
  1639. * in one transfer.
  1640. */
  1641. #ifndef writeq
  1642. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1643. spinlock_t *writeq_lock)
  1644. {
  1645. unsigned long flags;
  1646. __u64 data_out = cpu_to_le64(b);
  1647. spin_lock_irqsave(writeq_lock, flags);
  1648. writel((u32)(data_out), addr);
  1649. writel((u32)(data_out >> 32), (addr + 4));
  1650. spin_unlock_irqrestore(writeq_lock, flags);
  1651. }
  1652. #else
  1653. static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
  1654. spinlock_t *writeq_lock)
  1655. {
  1656. writeq(cpu_to_le64(b), addr);
  1657. }
  1658. #endif
  1659. static inline u8
  1660. _base_get_msix_index(struct MPT2SAS_ADAPTER *ioc)
  1661. {
  1662. return ioc->cpu_msix_table[raw_smp_processor_id()];
  1663. }
  1664. /**
  1665. * mpt2sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
  1666. * @ioc: per adapter object
  1667. * @smid: system request message index
  1668. * @handle: device handle
  1669. *
  1670. * Return nothing.
  1671. */
  1672. void
  1673. mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u16 handle)
  1674. {
  1675. Mpi2RequestDescriptorUnion_t descriptor;
  1676. u64 *request = (u64 *)&descriptor;
  1677. descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
  1678. descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
  1679. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  1680. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  1681. descriptor.SCSIIO.LMID = 0;
  1682. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1683. &ioc->scsi_lookup_lock);
  1684. }
  1685. /**
  1686. * mpt2sas_base_put_smid_hi_priority - send Task Management request to firmware
  1687. * @ioc: per adapter object
  1688. * @smid: system request message index
  1689. *
  1690. * Return nothing.
  1691. */
  1692. void
  1693. mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1694. {
  1695. Mpi2RequestDescriptorUnion_t descriptor;
  1696. u64 *request = (u64 *)&descriptor;
  1697. descriptor.HighPriority.RequestFlags =
  1698. MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
  1699. descriptor.HighPriority.MSIxIndex = 0;
  1700. descriptor.HighPriority.SMID = cpu_to_le16(smid);
  1701. descriptor.HighPriority.LMID = 0;
  1702. descriptor.HighPriority.Reserved1 = 0;
  1703. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1704. &ioc->scsi_lookup_lock);
  1705. }
  1706. /**
  1707. * mpt2sas_base_put_smid_default - Default, primarily used for config pages
  1708. * @ioc: per adapter object
  1709. * @smid: system request message index
  1710. *
  1711. * Return nothing.
  1712. */
  1713. void
  1714. mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid)
  1715. {
  1716. Mpi2RequestDescriptorUnion_t descriptor;
  1717. u64 *request = (u64 *)&descriptor;
  1718. descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
  1719. descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
  1720. descriptor.Default.SMID = cpu_to_le16(smid);
  1721. descriptor.Default.LMID = 0;
  1722. descriptor.Default.DescriptorTypeDependent = 0;
  1723. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1724. &ioc->scsi_lookup_lock);
  1725. }
  1726. /**
  1727. * mpt2sas_base_put_smid_target_assist - send Target Assist/Status to firmware
  1728. * @ioc: per adapter object
  1729. * @smid: system request message index
  1730. * @io_index: value used to track the IO
  1731. *
  1732. * Return nothing.
  1733. */
  1734. void
  1735. mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid,
  1736. u16 io_index)
  1737. {
  1738. Mpi2RequestDescriptorUnion_t descriptor;
  1739. u64 *request = (u64 *)&descriptor;
  1740. descriptor.SCSITarget.RequestFlags =
  1741. MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET;
  1742. descriptor.SCSITarget.MSIxIndex = _base_get_msix_index(ioc);
  1743. descriptor.SCSITarget.SMID = cpu_to_le16(smid);
  1744. descriptor.SCSITarget.LMID = 0;
  1745. descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index);
  1746. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1747. &ioc->scsi_lookup_lock);
  1748. }
  1749. /**
  1750. * _base_display_dell_branding - Disply branding string
  1751. * @ioc: per adapter object
  1752. *
  1753. * Return nothing.
  1754. */
  1755. static void
  1756. _base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc)
  1757. {
  1758. char dell_branding[MPT2SAS_DELL_BRANDING_SIZE];
  1759. if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
  1760. return;
  1761. memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE);
  1762. switch (ioc->pdev->subsystem_device) {
  1763. case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
  1764. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING,
  1765. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1766. break;
  1767. case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
  1768. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING,
  1769. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1770. break;
  1771. case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
  1772. strncpy(dell_branding,
  1773. MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING,
  1774. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1775. break;
  1776. case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
  1777. strncpy(dell_branding,
  1778. MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING,
  1779. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1780. break;
  1781. case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
  1782. strncpy(dell_branding,
  1783. MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING,
  1784. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1785. break;
  1786. case MPT2SAS_DELL_PERC_H200_SSDID:
  1787. strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING,
  1788. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1789. break;
  1790. case MPT2SAS_DELL_6GBPS_SAS_SSDID:
  1791. strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING,
  1792. MPT2SAS_DELL_BRANDING_SIZE - 1);
  1793. break;
  1794. default:
  1795. sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device);
  1796. break;
  1797. }
  1798. printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X),"
  1799. " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding,
  1800. ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor,
  1801. ioc->pdev->subsystem_device);
  1802. }
  1803. /**
  1804. * _base_display_intel_branding - Display branding string
  1805. * @ioc: per adapter object
  1806. *
  1807. * Return nothing.
  1808. */
  1809. static void
  1810. _base_display_intel_branding(struct MPT2SAS_ADAPTER *ioc)
  1811. {
  1812. if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
  1813. return;
  1814. switch (ioc->pdev->device) {
  1815. case MPI2_MFGPAGE_DEVID_SAS2008:
  1816. switch (ioc->pdev->subsystem_device) {
  1817. case MPT2SAS_INTEL_RMS2LL080_SSDID:
  1818. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1819. MPT2SAS_INTEL_RMS2LL080_BRANDING);
  1820. break;
  1821. case MPT2SAS_INTEL_RMS2LL040_SSDID:
  1822. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1823. MPT2SAS_INTEL_RMS2LL040_BRANDING);
  1824. break;
  1825. case MPT2SAS_INTEL_SSD910_SSDID:
  1826. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1827. MPT2SAS_INTEL_SSD910_BRANDING);
  1828. break;
  1829. default:
  1830. break;
  1831. }
  1832. case MPI2_MFGPAGE_DEVID_SAS2308_2:
  1833. switch (ioc->pdev->subsystem_device) {
  1834. case MPT2SAS_INTEL_RS25GB008_SSDID:
  1835. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1836. MPT2SAS_INTEL_RS25GB008_BRANDING);
  1837. break;
  1838. case MPT2SAS_INTEL_RMS25JB080_SSDID:
  1839. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1840. MPT2SAS_INTEL_RMS25JB080_BRANDING);
  1841. break;
  1842. case MPT2SAS_INTEL_RMS25JB040_SSDID:
  1843. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1844. MPT2SAS_INTEL_RMS25JB040_BRANDING);
  1845. break;
  1846. case MPT2SAS_INTEL_RMS25KB080_SSDID:
  1847. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1848. MPT2SAS_INTEL_RMS25KB080_BRANDING);
  1849. break;
  1850. case MPT2SAS_INTEL_RMS25KB040_SSDID:
  1851. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1852. MPT2SAS_INTEL_RMS25KB040_BRANDING);
  1853. break;
  1854. case MPT2SAS_INTEL_RMS25LB040_SSDID:
  1855. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1856. MPT2SAS_INTEL_RMS25LB040_BRANDING);
  1857. break;
  1858. case MPT2SAS_INTEL_RMS25LB080_SSDID:
  1859. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1860. MPT2SAS_INTEL_RMS25LB080_BRANDING);
  1861. break;
  1862. default:
  1863. break;
  1864. }
  1865. default:
  1866. break;
  1867. }
  1868. }
  1869. /**
  1870. * _base_display_hp_branding - Display branding string
  1871. * @ioc: per adapter object
  1872. *
  1873. * Return nothing.
  1874. */
  1875. static void
  1876. _base_display_hp_branding(struct MPT2SAS_ADAPTER *ioc)
  1877. {
  1878. if (ioc->pdev->subsystem_vendor != MPT2SAS_HP_3PAR_SSVID)
  1879. return;
  1880. switch (ioc->pdev->device) {
  1881. case MPI2_MFGPAGE_DEVID_SAS2004:
  1882. switch (ioc->pdev->subsystem_device) {
  1883. case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
  1884. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1885. MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
  1886. break;
  1887. default:
  1888. break;
  1889. }
  1890. case MPI2_MFGPAGE_DEVID_SAS2308_2:
  1891. switch (ioc->pdev->subsystem_device) {
  1892. case MPT2SAS_HP_2_4_INTERNAL_SSDID:
  1893. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1894. MPT2SAS_HP_2_4_INTERNAL_BRANDING);
  1895. break;
  1896. case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
  1897. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1898. MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
  1899. break;
  1900. case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
  1901. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1902. MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
  1903. break;
  1904. case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
  1905. printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  1906. MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
  1907. break;
  1908. default:
  1909. break;
  1910. }
  1911. default:
  1912. break;
  1913. }
  1914. }
  1915. /**
  1916. * _base_display_ioc_capabilities - Disply IOC's capabilities.
  1917. * @ioc: per adapter object
  1918. *
  1919. * Return nothing.
  1920. */
  1921. static void
  1922. _base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
  1923. {
  1924. int i = 0;
  1925. char desc[16];
  1926. u32 iounit_pg1_flags;
  1927. u32 bios_version;
  1928. bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
  1929. strncpy(desc, ioc->manu_pg0.ChipName, 16);
  1930. printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "
  1931. "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
  1932. ioc->name, desc,
  1933. (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
  1934. (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
  1935. (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
  1936. ioc->facts.FWVersion.Word & 0x000000FF,
  1937. ioc->pdev->revision,
  1938. (bios_version & 0xFF000000) >> 24,
  1939. (bios_version & 0x00FF0000) >> 16,
  1940. (bios_version & 0x0000FF00) >> 8,
  1941. bios_version & 0x000000FF);
  1942. _base_display_dell_branding(ioc);
  1943. _base_display_intel_branding(ioc);
  1944. _base_display_hp_branding(ioc);
  1945. printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
  1946. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
  1947. printk("Initiator");
  1948. i++;
  1949. }
  1950. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
  1951. printk("%sTarget", i ? "," : "");
  1952. i++;
  1953. }
  1954. i = 0;
  1955. printk("), ");
  1956. printk("Capabilities=(");
  1957. if (!ioc->hide_ir_msg) {
  1958. if (ioc->facts.IOCCapabilities &
  1959. MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
  1960. printk("Raid");
  1961. i++;
  1962. }
  1963. }
  1964. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
  1965. printk("%sTLR", i ? "," : "");
  1966. i++;
  1967. }
  1968. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
  1969. printk("%sMulticast", i ? "," : "");
  1970. i++;
  1971. }
  1972. if (ioc->facts.IOCCapabilities &
  1973. MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
  1974. printk("%sBIDI Target", i ? "," : "");
  1975. i++;
  1976. }
  1977. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
  1978. printk("%sEEDP", i ? "," : "");
  1979. i++;
  1980. }
  1981. if (ioc->facts.IOCCapabilities &
  1982. MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
  1983. printk("%sSnapshot Buffer", i ? "," : "");
  1984. i++;
  1985. }
  1986. if (ioc->facts.IOCCapabilities &
  1987. MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
  1988. printk("%sDiag Trace Buffer", i ? "," : "");
  1989. i++;
  1990. }
  1991. if (ioc->facts.IOCCapabilities &
  1992. MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
  1993. printk(KERN_INFO "%sDiag Extended Buffer", i ? "," : "");
  1994. i++;
  1995. }
  1996. if (ioc->facts.IOCCapabilities &
  1997. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
  1998. printk("%sTask Set Full", i ? "," : "");
  1999. i++;
  2000. }
  2001. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  2002. if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
  2003. printk("%sNCQ", i ? "," : "");
  2004. i++;
  2005. }
  2006. printk(")\n");
  2007. }
  2008. /**
  2009. * mpt2sas_base_update_missing_delay - change the missing delay timers
  2010. * @ioc: per adapter object
  2011. * @device_missing_delay: amount of time till device is reported missing
  2012. * @io_missing_delay: interval IO is returned when there is a missing device
  2013. *
  2014. * Return nothing.
  2015. *
  2016. * Passed on the command line, this function will modify the device missing
  2017. * delay, as well as the io missing delay. This should be called at driver
  2018. * load time.
  2019. */
  2020. void
  2021. mpt2sas_base_update_missing_delay(struct MPT2SAS_ADAPTER *ioc,
  2022. u16 device_missing_delay, u8 io_missing_delay)
  2023. {
  2024. u16 dmd, dmd_new, dmd_orignal;
  2025. u8 io_missing_delay_original;
  2026. u16 sz;
  2027. Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
  2028. Mpi2ConfigReply_t mpi_reply;
  2029. u8 num_phys = 0;
  2030. u16 ioc_status;
  2031. mpt2sas_config_get_number_hba_phys(ioc, &num_phys);
  2032. if (!num_phys)
  2033. return;
  2034. sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
  2035. sizeof(Mpi2SasIOUnit1PhyData_t));
  2036. sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
  2037. if (!sas_iounit_pg1) {
  2038. printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
  2039. ioc->name, __FILE__, __LINE__, __func__);
  2040. goto out;
  2041. }
  2042. if ((mpt2sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
  2043. sas_iounit_pg1, sz))) {
  2044. printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
  2045. ioc->name, __FILE__, __LINE__, __func__);
  2046. goto out;
  2047. }
  2048. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
  2049. MPI2_IOCSTATUS_MASK;
  2050. if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
  2051. printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
  2052. ioc->name, __FILE__, __LINE__, __func__);
  2053. goto out;
  2054. }
  2055. /* device missing delay */
  2056. dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
  2057. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  2058. dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  2059. else
  2060. dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  2061. dmd_orignal = dmd;
  2062. if (device_missing_delay > 0x7F) {
  2063. dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
  2064. device_missing_delay;
  2065. dmd = dmd / 16;
  2066. dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
  2067. } else
  2068. dmd = device_missing_delay;
  2069. sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
  2070. /* io missing delay */
  2071. io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
  2072. sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
  2073. if (!mpt2sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
  2074. sz)) {
  2075. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  2076. dmd_new = (dmd &
  2077. MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  2078. else
  2079. dmd_new =
  2080. dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  2081. printk(MPT2SAS_INFO_FMT "device_missing_delay: old(%d), "
  2082. "new(%d)\n", ioc->name, dmd_orignal, dmd_new);
  2083. printk(MPT2SAS_INFO_FMT "ioc_missing_delay: old(%d), "
  2084. "new(%d)\n", ioc->name, io_missing_delay_original,
  2085. io_missing_delay);
  2086. ioc->device_missing_delay = dmd_new;
  2087. ioc->io_missing_delay = io_missing_delay;
  2088. }
  2089. out:
  2090. kfree(sas_iounit_pg1);
  2091. }
  2092. /**
  2093. * _base_static_config_pages - static start of day config pages
  2094. * @ioc: per adapter object
  2095. *
  2096. * Return nothing.
  2097. */
  2098. static void
  2099. _base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
  2100. {
  2101. Mpi2ConfigReply_t mpi_reply;
  2102. u32 iounit_pg1_flags;
  2103. mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
  2104. if (ioc->ir_firmware)
  2105. mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
  2106. &ioc->manu_pg10);
  2107. mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
  2108. mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
  2109. mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
  2110. mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
  2111. mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  2112. mpt2sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
  2113. _base_display_ioc_capabilities(ioc);
  2114. /*
  2115. * Enable task_set_full handling in iounit_pg1 when the
  2116. * facts capabilities indicate that its supported.
  2117. */
  2118. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  2119. if ((ioc->facts.IOCCapabilities &
  2120. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
  2121. iounit_pg1_flags &=
  2122. ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  2123. else
  2124. iounit_pg1_flags |=
  2125. MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  2126. ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
  2127. mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  2128. if (ioc->iounit_pg8.NumSensors)
  2129. ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
  2130. }
  2131. /**
  2132. * _base_release_memory_pools - release memory
  2133. * @ioc: per adapter object
  2134. *
  2135. * Free memory allocated from _base_allocate_memory_pools.
  2136. *
  2137. * Return nothing.
  2138. */
  2139. static void
  2140. _base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
  2141. {
  2142. int i = 0;
  2143. struct reply_post_struct *rps;
  2144. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2145. __func__));
  2146. if (ioc->request) {
  2147. pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
  2148. ioc->request, ioc->request_dma);
  2149. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)"
  2150. ": free\n", ioc->name, ioc->request));
  2151. ioc->request = NULL;
  2152. }
  2153. if (ioc->sense) {
  2154. pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
  2155. if (ioc->sense_dma_pool)
  2156. pci_pool_destroy(ioc->sense_dma_pool);
  2157. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)"
  2158. ": free\n", ioc->name, ioc->sense));
  2159. ioc->sense = NULL;
  2160. }
  2161. if (ioc->reply) {
  2162. pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
  2163. if (ioc->reply_dma_pool)
  2164. pci_pool_destroy(ioc->reply_dma_pool);
  2165. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)"
  2166. ": free\n", ioc->name, ioc->reply));
  2167. ioc->reply = NULL;
  2168. }
  2169. if (ioc->reply_free) {
  2170. pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
  2171. ioc->reply_free_dma);
  2172. if (ioc->reply_free_dma_pool)
  2173. pci_pool_destroy(ioc->reply_free_dma_pool);
  2174. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool"
  2175. "(0x%p): free\n", ioc->name, ioc->reply_free));
  2176. ioc->reply_free = NULL;
  2177. }
  2178. if (ioc->reply_post) {
  2179. do {
  2180. rps = &ioc->reply_post[i];
  2181. if (rps->reply_post_free) {
  2182. pci_pool_free(
  2183. ioc->reply_post_free_dma_pool,
  2184. rps->reply_post_free,
  2185. rps->reply_post_free_dma);
  2186. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  2187. "reply_post_free_pool(0x%p): free\n",
  2188. ioc->name, rps->reply_post_free));
  2189. rps->reply_post_free = NULL;
  2190. }
  2191. } while (ioc->rdpq_array_enable &&
  2192. (++i < ioc->reply_queue_count));
  2193. if (ioc->reply_post_free_dma_pool)
  2194. pci_pool_destroy(ioc->reply_post_free_dma_pool);
  2195. kfree(ioc->reply_post);
  2196. }
  2197. if (ioc->config_page) {
  2198. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
  2199. "config_page(0x%p): free\n", ioc->name,
  2200. ioc->config_page));
  2201. pci_free_consistent(ioc->pdev, ioc->config_page_sz,
  2202. ioc->config_page, ioc->config_page_dma);
  2203. }
  2204. if (ioc->scsi_lookup) {
  2205. free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
  2206. ioc->scsi_lookup = NULL;
  2207. }
  2208. kfree(ioc->hpr_lookup);
  2209. kfree(ioc->internal_lookup);
  2210. if (ioc->chain_lookup) {
  2211. for (i = 0; i < ioc->chain_depth; i++) {
  2212. if (ioc->chain_lookup[i].chain_buffer)
  2213. pci_pool_free(ioc->chain_dma_pool,
  2214. ioc->chain_lookup[i].chain_buffer,
  2215. ioc->chain_lookup[i].chain_buffer_dma);
  2216. }
  2217. if (ioc->chain_dma_pool)
  2218. pci_pool_destroy(ioc->chain_dma_pool);
  2219. free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
  2220. ioc->chain_lookup = NULL;
  2221. }
  2222. }
  2223. /**
  2224. * _base_allocate_memory_pools - allocate start of day memory pools
  2225. * @ioc: per adapter object
  2226. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2227. *
  2228. * Returns 0 success, anything else error
  2229. */
  2230. static int
  2231. _base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  2232. {
  2233. struct mpt2sas_facts *facts;
  2234. u16 max_sge_elements;
  2235. u16 chains_needed_per_io;
  2236. u32 sz, total_sz, reply_post_free_sz;
  2237. u32 retry_sz;
  2238. u16 max_request_credit;
  2239. int i;
  2240. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2241. __func__));
  2242. retry_sz = 0;
  2243. facts = &ioc->facts;
  2244. /* command line tunables for max sgl entries */
  2245. if (max_sgl_entries != -1) {
  2246. ioc->shost->sg_tablesize = min_t(unsigned short,
  2247. max_sgl_entries, SCSI_MAX_SG_CHAIN_SEGMENTS);
  2248. if (ioc->shost->sg_tablesize > MPT2SAS_SG_DEPTH)
  2249. printk(MPT2SAS_WARN_FMT
  2250. "sg_tablesize(%u) is bigger than kernel defined"
  2251. " SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
  2252. ioc->shost->sg_tablesize, MPT2SAS_SG_DEPTH);
  2253. } else {
  2254. ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH;
  2255. }
  2256. /* command line tunables for max controller queue depth */
  2257. if (max_queue_depth != -1 && max_queue_depth != 0) {
  2258. max_request_credit = min_t(u16, max_queue_depth +
  2259. ioc->hi_priority_depth + ioc->internal_depth,
  2260. facts->RequestCredit);
  2261. if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
  2262. max_request_credit = MAX_HBA_QUEUE_DEPTH;
  2263. } else
  2264. max_request_credit = min_t(u16, facts->RequestCredit,
  2265. MAX_HBA_QUEUE_DEPTH);
  2266. ioc->hba_queue_depth = max_request_credit;
  2267. ioc->hi_priority_depth = facts->HighPriorityCredit;
  2268. ioc->internal_depth = ioc->hi_priority_depth + 5;
  2269. /* request frame size */
  2270. ioc->request_sz = facts->IOCRequestFrameSize * 4;
  2271. /* reply frame size */
  2272. ioc->reply_sz = facts->ReplyFrameSize * 4;
  2273. retry_allocation:
  2274. total_sz = 0;
  2275. /* calculate number of sg elements left over in the 1st frame */
  2276. max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
  2277. sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size);
  2278. ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size;
  2279. /* now do the same for a chain buffer */
  2280. max_sge_elements = ioc->request_sz - ioc->sge_size;
  2281. ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size;
  2282. ioc->chain_offset_value_for_main_message =
  2283. ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) +
  2284. (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4;
  2285. /*
  2286. * MPT2SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
  2287. */
  2288. chains_needed_per_io = ((ioc->shost->sg_tablesize -
  2289. ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
  2290. + 1;
  2291. if (chains_needed_per_io > facts->MaxChainDepth) {
  2292. chains_needed_per_io = facts->MaxChainDepth;
  2293. ioc->shost->sg_tablesize = min_t(u16,
  2294. ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
  2295. * chains_needed_per_io), ioc->shost->sg_tablesize);
  2296. }
  2297. ioc->chains_needed_per_io = chains_needed_per_io;
  2298. /* reply free queue sizing - taking into account for 64 FW events */
  2299. ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
  2300. /* calculate reply descriptor post queue depth */
  2301. ioc->reply_post_queue_depth = ioc->hba_queue_depth +
  2302. ioc->reply_free_queue_depth + 1;
  2303. /* align the reply post queue on the next 16 count boundary */
  2304. if (ioc->reply_post_queue_depth % 16)
  2305. ioc->reply_post_queue_depth += 16 -
  2306. (ioc->reply_post_queue_depth % 16);
  2307. if (ioc->reply_post_queue_depth >
  2308. facts->MaxReplyDescriptorPostQueueDepth) {
  2309. ioc->reply_post_queue_depth =
  2310. facts->MaxReplyDescriptorPostQueueDepth -
  2311. (facts->MaxReplyDescriptorPostQueueDepth % 16);
  2312. ioc->hba_queue_depth =
  2313. ((ioc->reply_post_queue_depth - 64) / 2) - 1;
  2314. ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
  2315. }
  2316. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: "
  2317. "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
  2318. "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
  2319. ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
  2320. ioc->chains_needed_per_io));
  2321. /* reply post queue, 16 byte align */
  2322. reply_post_free_sz = ioc->reply_post_queue_depth *
  2323. sizeof(Mpi2DefaultReplyDescriptor_t);
  2324. sz = reply_post_free_sz;
  2325. if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
  2326. sz *= ioc->reply_queue_count;
  2327. ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
  2328. (ioc->reply_queue_count):1,
  2329. sizeof(struct reply_post_struct), GFP_KERNEL);
  2330. if (!ioc->reply_post) {
  2331. printk(MPT2SAS_ERR_FMT "reply_post_free pool: kcalloc failed\n",
  2332. ioc->name);
  2333. goto out;
  2334. }
  2335. ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
  2336. ioc->pdev, sz, 16, 0);
  2337. if (!ioc->reply_post_free_dma_pool) {
  2338. printk(MPT2SAS_ERR_FMT
  2339. "reply_post_free pool: pci_pool_create failed\n",
  2340. ioc->name);
  2341. goto out;
  2342. }
  2343. i = 0;
  2344. do {
  2345. ioc->reply_post[i].reply_post_free =
  2346. pci_pool_alloc(ioc->reply_post_free_dma_pool,
  2347. GFP_KERNEL,
  2348. &ioc->reply_post[i].reply_post_free_dma);
  2349. if (!ioc->reply_post[i].reply_post_free) {
  2350. printk(MPT2SAS_ERR_FMT
  2351. "reply_post_free pool: pci_pool_alloc failed\n",
  2352. ioc->name);
  2353. goto out;
  2354. }
  2355. memset(ioc->reply_post[i].reply_post_free, 0, sz);
  2356. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
  2357. "reply post free pool (0x%p): depth(%d),"
  2358. "element_size(%d), pool_size(%d kB)\n", ioc->name,
  2359. ioc->reply_post[i].reply_post_free,
  2360. ioc->reply_post_queue_depth, 8, sz/1024));
  2361. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
  2362. "reply_post_free_dma = (0x%llx)\n", ioc->name,
  2363. (unsigned long long)
  2364. ioc->reply_post[i].reply_post_free_dma));
  2365. total_sz += sz;
  2366. } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
  2367. if (ioc->dma_mask == 64) {
  2368. if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
  2369. printk(MPT2SAS_WARN_FMT
  2370. "no suitable consistent DMA mask for %s\n",
  2371. ioc->name, pci_name(ioc->pdev));
  2372. goto out;
  2373. }
  2374. }
  2375. ioc->scsiio_depth = ioc->hba_queue_depth -
  2376. ioc->hi_priority_depth - ioc->internal_depth;
  2377. /* set the scsi host can_queue depth
  2378. * with some internal commands that could be outstanding
  2379. */
  2380. ioc->shost->can_queue = ioc->scsiio_depth;
  2381. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host: "
  2382. "can_queue depth (%d)\n", ioc->name, ioc->shost->can_queue));
  2383. /* contiguous pool for request and chains, 16 byte align, one extra "
  2384. * "frame for smid=0
  2385. */
  2386. ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
  2387. sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
  2388. /* hi-priority queue */
  2389. sz += (ioc->hi_priority_depth * ioc->request_sz);
  2390. /* internal queue */
  2391. sz += (ioc->internal_depth * ioc->request_sz);
  2392. ioc->request_dma_sz = sz;
  2393. ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
  2394. if (!ioc->request) {
  2395. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  2396. "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  2397. "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
  2398. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  2399. if (ioc->scsiio_depth < MPT2SAS_SAS_QUEUE_DEPTH)
  2400. goto out;
  2401. retry_sz += 64;
  2402. ioc->hba_queue_depth = max_request_credit - retry_sz;
  2403. goto retry_allocation;
  2404. }
  2405. if (retry_sz)
  2406. printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
  2407. "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  2408. "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
  2409. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  2410. /* hi-priority queue */
  2411. ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
  2412. ioc->request_sz);
  2413. ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
  2414. ioc->request_sz);
  2415. /* internal queue */
  2416. ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
  2417. ioc->request_sz);
  2418. ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
  2419. ioc->request_sz);
  2420. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): "
  2421. "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
  2422. ioc->request, ioc->hba_queue_depth, ioc->request_sz,
  2423. (ioc->hba_queue_depth * ioc->request_sz)/1024));
  2424. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n",
  2425. ioc->name, (unsigned long long) ioc->request_dma));
  2426. total_sz += sz;
  2427. sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
  2428. ioc->scsi_lookup_pages = get_order(sz);
  2429. ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
  2430. GFP_KERNEL, ioc->scsi_lookup_pages);
  2431. if (!ioc->scsi_lookup) {
  2432. printk(MPT2SAS_ERR_FMT "scsi_lookup: get_free_pages failed, "
  2433. "sz(%d)\n", ioc->name, (int)sz);
  2434. goto out;
  2435. }
  2436. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsiio(0x%p): "
  2437. "depth(%d)\n", ioc->name, ioc->request,
  2438. ioc->scsiio_depth));
  2439. ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
  2440. sz = ioc->chain_depth * sizeof(struct chain_tracker);
  2441. ioc->chain_pages = get_order(sz);
  2442. ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
  2443. GFP_KERNEL, ioc->chain_pages);
  2444. if (!ioc->chain_lookup) {
  2445. printk(MPT2SAS_ERR_FMT "chain_lookup: get_free_pages failed, "
  2446. "sz(%d)\n", ioc->name, (int)sz);
  2447. goto out;
  2448. }
  2449. ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
  2450. ioc->request_sz, 16, 0);
  2451. if (!ioc->chain_dma_pool) {
  2452. printk(MPT2SAS_ERR_FMT "chain_dma_pool: pci_pool_create "
  2453. "failed\n", ioc->name);
  2454. goto out;
  2455. }
  2456. for (i = 0; i < ioc->chain_depth; i++) {
  2457. ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
  2458. ioc->chain_dma_pool , GFP_KERNEL,
  2459. &ioc->chain_lookup[i].chain_buffer_dma);
  2460. if (!ioc->chain_lookup[i].chain_buffer) {
  2461. ioc->chain_depth = i;
  2462. goto chain_done;
  2463. }
  2464. total_sz += ioc->request_sz;
  2465. }
  2466. chain_done:
  2467. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool depth"
  2468. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
  2469. ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth *
  2470. ioc->request_sz))/1024));
  2471. /* initialize hi-priority queue smid's */
  2472. ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
  2473. sizeof(struct request_tracker), GFP_KERNEL);
  2474. if (!ioc->hpr_lookup) {
  2475. printk(MPT2SAS_ERR_FMT "hpr_lookup: kcalloc failed\n",
  2476. ioc->name);
  2477. goto out;
  2478. }
  2479. ioc->hi_priority_smid = ioc->scsiio_depth + 1;
  2480. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hi_priority(0x%p): "
  2481. "depth(%d), start smid(%d)\n", ioc->name, ioc->hi_priority,
  2482. ioc->hi_priority_depth, ioc->hi_priority_smid));
  2483. /* initialize internal queue smid's */
  2484. ioc->internal_lookup = kcalloc(ioc->internal_depth,
  2485. sizeof(struct request_tracker), GFP_KERNEL);
  2486. if (!ioc->internal_lookup) {
  2487. printk(MPT2SAS_ERR_FMT "internal_lookup: kcalloc failed\n",
  2488. ioc->name);
  2489. goto out;
  2490. }
  2491. ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
  2492. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "internal(0x%p): "
  2493. "depth(%d), start smid(%d)\n", ioc->name, ioc->internal,
  2494. ioc->internal_depth, ioc->internal_smid));
  2495. /* sense buffers, 4 byte align */
  2496. sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
  2497. ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
  2498. 0);
  2499. if (!ioc->sense_dma_pool) {
  2500. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n",
  2501. ioc->name);
  2502. goto out;
  2503. }
  2504. ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
  2505. &ioc->sense_dma);
  2506. if (!ioc->sense) {
  2507. printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n",
  2508. ioc->name);
  2509. goto out;
  2510. }
  2511. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
  2512. "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
  2513. "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
  2514. SCSI_SENSE_BUFFERSIZE, sz/1024));
  2515. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n",
  2516. ioc->name, (unsigned long long)ioc->sense_dma));
  2517. total_sz += sz;
  2518. /* reply pool, 4 byte align */
  2519. sz = ioc->reply_free_queue_depth * ioc->reply_sz;
  2520. ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
  2521. 0);
  2522. if (!ioc->reply_dma_pool) {
  2523. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n",
  2524. ioc->name);
  2525. goto out;
  2526. }
  2527. ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
  2528. &ioc->reply_dma);
  2529. if (!ioc->reply) {
  2530. printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n",
  2531. ioc->name);
  2532. goto out;
  2533. }
  2534. ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
  2535. ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
  2536. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth"
  2537. "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply,
  2538. ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
  2539. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n",
  2540. ioc->name, (unsigned long long)ioc->reply_dma));
  2541. total_sz += sz;
  2542. /* reply free queue, 16 byte align */
  2543. sz = ioc->reply_free_queue_depth * 4;
  2544. ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
  2545. ioc->pdev, sz, 16, 0);
  2546. if (!ioc->reply_free_dma_pool) {
  2547. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create "
  2548. "failed\n", ioc->name);
  2549. goto out;
  2550. }
  2551. ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
  2552. &ioc->reply_free_dma);
  2553. if (!ioc->reply_free) {
  2554. printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc "
  2555. "failed\n", ioc->name);
  2556. goto out;
  2557. }
  2558. memset(ioc->reply_free, 0, sz);
  2559. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): "
  2560. "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
  2561. ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
  2562. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma"
  2563. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma));
  2564. total_sz += sz;
  2565. ioc->config_page_sz = 512;
  2566. ioc->config_page = pci_alloc_consistent(ioc->pdev,
  2567. ioc->config_page_sz, &ioc->config_page_dma);
  2568. if (!ioc->config_page) {
  2569. printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc "
  2570. "failed\n", ioc->name);
  2571. goto out;
  2572. }
  2573. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size"
  2574. "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz));
  2575. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma"
  2576. "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma));
  2577. total_sz += ioc->config_page_sz;
  2578. printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n",
  2579. ioc->name, total_sz/1024);
  2580. printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), "
  2581. "Max Controller Queue Depth(%d)\n",
  2582. ioc->name, ioc->shost->can_queue, facts->RequestCredit);
  2583. printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n",
  2584. ioc->name, ioc->shost->sg_tablesize);
  2585. return 0;
  2586. out:
  2587. return -ENOMEM;
  2588. }
  2589. /**
  2590. * mpt2sas_base_get_iocstate - Get the current state of a MPT adapter.
  2591. * @ioc: Pointer to MPT_ADAPTER structure
  2592. * @cooked: Request raw or cooked IOC state
  2593. *
  2594. * Returns all IOC Doorbell register bits if cooked==0, else just the
  2595. * Doorbell bits in MPI_IOC_STATE_MASK.
  2596. */
  2597. u32
  2598. mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked)
  2599. {
  2600. u32 s, sc;
  2601. s = readl(&ioc->chip->Doorbell);
  2602. sc = s & MPI2_IOC_STATE_MASK;
  2603. return cooked ? sc : s;
  2604. }
  2605. /**
  2606. * _base_wait_on_iocstate - waiting on a particular ioc state
  2607. * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
  2608. * @timeout: timeout in second
  2609. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2610. *
  2611. * Returns 0 for success, non-zero for failure.
  2612. */
  2613. static int
  2614. _base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
  2615. int sleep_flag)
  2616. {
  2617. u32 count, cntdn;
  2618. u32 current_state;
  2619. count = 0;
  2620. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2621. do {
  2622. current_state = mpt2sas_base_get_iocstate(ioc, 1);
  2623. if (current_state == ioc_state)
  2624. return 0;
  2625. if (count && current_state == MPI2_IOC_STATE_FAULT)
  2626. break;
  2627. if (sleep_flag == CAN_SLEEP)
  2628. msleep(1);
  2629. else
  2630. udelay(500);
  2631. count++;
  2632. } while (--cntdn);
  2633. return current_state;
  2634. }
  2635. /**
  2636. * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
  2637. * a write to the doorbell)
  2638. * @ioc: per adapter object
  2639. * @timeout: timeout in second
  2640. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2641. *
  2642. * Returns 0 for success, non-zero for failure.
  2643. *
  2644. * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
  2645. */
  2646. static int
  2647. _base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2648. int sleep_flag)
  2649. {
  2650. u32 cntdn, count;
  2651. u32 int_status;
  2652. count = 0;
  2653. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2654. do {
  2655. int_status = readl(&ioc->chip->HostInterruptStatus);
  2656. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2657. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2658. "successful count(%d), timeout(%d)\n", ioc->name,
  2659. __func__, count, timeout));
  2660. return 0;
  2661. }
  2662. if (sleep_flag == CAN_SLEEP)
  2663. msleep(1);
  2664. else
  2665. udelay(500);
  2666. count++;
  2667. } while (--cntdn);
  2668. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2669. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2670. return -EFAULT;
  2671. }
  2672. /**
  2673. * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
  2674. * @ioc: per adapter object
  2675. * @timeout: timeout in second
  2676. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2677. *
  2678. * Returns 0 for success, non-zero for failure.
  2679. *
  2680. * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
  2681. * doorbell.
  2682. */
  2683. static int
  2684. _base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2685. int sleep_flag)
  2686. {
  2687. u32 cntdn, count;
  2688. u32 int_status;
  2689. u32 doorbell;
  2690. count = 0;
  2691. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2692. do {
  2693. int_status = readl(&ioc->chip->HostInterruptStatus);
  2694. if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
  2695. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2696. "successful count(%d), timeout(%d)\n", ioc->name,
  2697. __func__, count, timeout));
  2698. return 0;
  2699. } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2700. doorbell = readl(&ioc->chip->Doorbell);
  2701. if ((doorbell & MPI2_IOC_STATE_MASK) ==
  2702. MPI2_IOC_STATE_FAULT) {
  2703. mpt2sas_base_fault_info(ioc , doorbell);
  2704. return -EFAULT;
  2705. }
  2706. } else if (int_status == 0xFFFFFFFF)
  2707. goto out;
  2708. if (sleep_flag == CAN_SLEEP)
  2709. msleep(1);
  2710. else
  2711. udelay(500);
  2712. count++;
  2713. } while (--cntdn);
  2714. out:
  2715. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2716. "int_status(%x)!\n", ioc->name, __func__, count, int_status);
  2717. return -EFAULT;
  2718. }
  2719. /**
  2720. * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
  2721. * @ioc: per adapter object
  2722. * @timeout: timeout in second
  2723. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2724. *
  2725. * Returns 0 for success, non-zero for failure.
  2726. *
  2727. */
  2728. static int
  2729. _base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout,
  2730. int sleep_flag)
  2731. {
  2732. u32 cntdn, count;
  2733. u32 doorbell_reg;
  2734. count = 0;
  2735. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2736. do {
  2737. doorbell_reg = readl(&ioc->chip->Doorbell);
  2738. if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
  2739. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  2740. "successful count(%d), timeout(%d)\n", ioc->name,
  2741. __func__, count, timeout));
  2742. return 0;
  2743. }
  2744. if (sleep_flag == CAN_SLEEP)
  2745. msleep(1);
  2746. else
  2747. udelay(500);
  2748. count++;
  2749. } while (--cntdn);
  2750. printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
  2751. "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg);
  2752. return -EFAULT;
  2753. }
  2754. /**
  2755. * _base_send_ioc_reset - send doorbell reset
  2756. * @ioc: per adapter object
  2757. * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
  2758. * @timeout: timeout in second
  2759. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2760. *
  2761. * Returns 0 for success, non-zero for failure.
  2762. */
  2763. static int
  2764. _base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout,
  2765. int sleep_flag)
  2766. {
  2767. u32 ioc_state;
  2768. int r = 0;
  2769. if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
  2770. printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n",
  2771. ioc->name, __func__);
  2772. return -EFAULT;
  2773. }
  2774. if (!(ioc->facts.IOCCapabilities &
  2775. MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
  2776. return -EFAULT;
  2777. printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name);
  2778. writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
  2779. &ioc->chip->Doorbell);
  2780. if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
  2781. r = -EFAULT;
  2782. goto out;
  2783. }
  2784. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
  2785. timeout, sleep_flag);
  2786. if (ioc_state) {
  2787. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  2788. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  2789. r = -EFAULT;
  2790. goto out;
  2791. }
  2792. out:
  2793. printk(MPT2SAS_INFO_FMT "message unit reset: %s\n",
  2794. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2795. return r;
  2796. }
  2797. /**
  2798. * _base_handshake_req_reply_wait - send request thru doorbell interface
  2799. * @ioc: per adapter object
  2800. * @request_bytes: request length
  2801. * @request: pointer having request payload
  2802. * @reply_bytes: reply length
  2803. * @reply: pointer to reply payload
  2804. * @timeout: timeout in second
  2805. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2806. *
  2807. * Returns 0 for success, non-zero for failure.
  2808. */
  2809. static int
  2810. _base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes,
  2811. u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
  2812. {
  2813. MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
  2814. int i;
  2815. u8 failed;
  2816. u16 dummy;
  2817. __le32 *mfp;
  2818. /* make sure doorbell is not in use */
  2819. if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
  2820. printk(MPT2SAS_ERR_FMT "doorbell is in use "
  2821. " (line=%d)\n", ioc->name, __LINE__);
  2822. return -EFAULT;
  2823. }
  2824. /* clear pending doorbell interrupts from previous state changes */
  2825. if (readl(&ioc->chip->HostInterruptStatus) &
  2826. MPI2_HIS_IOC2SYS_DB_STATUS)
  2827. writel(0, &ioc->chip->HostInterruptStatus);
  2828. /* send message to ioc */
  2829. writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
  2830. ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
  2831. &ioc->chip->Doorbell);
  2832. if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
  2833. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2834. "int failed (line=%d)\n", ioc->name, __LINE__);
  2835. return -EFAULT;
  2836. }
  2837. writel(0, &ioc->chip->HostInterruptStatus);
  2838. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
  2839. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2840. "ack failed (line=%d)\n", ioc->name, __LINE__);
  2841. return -EFAULT;
  2842. }
  2843. /* send message 32-bits at a time */
  2844. for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
  2845. writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
  2846. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
  2847. failed = 1;
  2848. }
  2849. if (failed) {
  2850. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2851. "sending request failed (line=%d)\n", ioc->name, __LINE__);
  2852. return -EFAULT;
  2853. }
  2854. /* now wait for the reply */
  2855. if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
  2856. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2857. "int failed (line=%d)\n", ioc->name, __LINE__);
  2858. return -EFAULT;
  2859. }
  2860. /* read the first two 16-bits, it gives the total length of the reply */
  2861. reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2862. & MPI2_DOORBELL_DATA_MASK);
  2863. writel(0, &ioc->chip->HostInterruptStatus);
  2864. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2865. printk(MPT2SAS_ERR_FMT "doorbell handshake "
  2866. "int failed (line=%d)\n", ioc->name, __LINE__);
  2867. return -EFAULT;
  2868. }
  2869. reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2870. & MPI2_DOORBELL_DATA_MASK);
  2871. writel(0, &ioc->chip->HostInterruptStatus);
  2872. for (i = 2; i < default_reply->MsgLength * 2; i++) {
  2873. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2874. printk(MPT2SAS_ERR_FMT "doorbell "
  2875. "handshake int failed (line=%d)\n", ioc->name,
  2876. __LINE__);
  2877. return -EFAULT;
  2878. }
  2879. if (i >= reply_bytes/2) /* overflow case */
  2880. dummy = readl(&ioc->chip->Doorbell);
  2881. else
  2882. reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2883. & MPI2_DOORBELL_DATA_MASK);
  2884. writel(0, &ioc->chip->HostInterruptStatus);
  2885. }
  2886. _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
  2887. if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
  2888. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use "
  2889. " (line=%d)\n", ioc->name, __LINE__));
  2890. }
  2891. writel(0, &ioc->chip->HostInterruptStatus);
  2892. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2893. mfp = (__le32 *)reply;
  2894. printk(KERN_INFO "\toffset:data\n");
  2895. for (i = 0; i < reply_bytes/4; i++)
  2896. printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
  2897. le32_to_cpu(mfp[i]));
  2898. }
  2899. return 0;
  2900. }
  2901. /**
  2902. * mpt2sas_base_sas_iounit_control - send sas iounit control to FW
  2903. * @ioc: per adapter object
  2904. * @mpi_reply: the reply payload from FW
  2905. * @mpi_request: the request payload sent to FW
  2906. *
  2907. * The SAS IO Unit Control Request message allows the host to perform low-level
  2908. * operations, such as resets on the PHYs of the IO Unit, also allows the host
  2909. * to obtain the IOC assigned device handles for a device if it has other
  2910. * identifying information about the device, in addition allows the host to
  2911. * remove IOC resources associated with the device.
  2912. *
  2913. * Returns 0 for success, non-zero for failure.
  2914. */
  2915. int
  2916. mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc,
  2917. Mpi2SasIoUnitControlReply_t *mpi_reply,
  2918. Mpi2SasIoUnitControlRequest_t *mpi_request)
  2919. {
  2920. u16 smid;
  2921. u32 ioc_state;
  2922. unsigned long timeleft;
  2923. bool issue_reset = false;
  2924. int rc;
  2925. void *request;
  2926. u16 wait_state_count;
  2927. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  2928. __func__));
  2929. mutex_lock(&ioc->base_cmds.mutex);
  2930. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  2931. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  2932. ioc->name, __func__);
  2933. rc = -EAGAIN;
  2934. goto out;
  2935. }
  2936. wait_state_count = 0;
  2937. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2938. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  2939. if (wait_state_count++ == 10) {
  2940. printk(MPT2SAS_ERR_FMT
  2941. "%s: failed due to ioc not operational\n",
  2942. ioc->name, __func__);
  2943. rc = -EFAULT;
  2944. goto out;
  2945. }
  2946. ssleep(1);
  2947. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  2948. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  2949. "operational state(count=%d)\n", ioc->name,
  2950. __func__, wait_state_count);
  2951. }
  2952. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  2953. if (!smid) {
  2954. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  2955. ioc->name, __func__);
  2956. rc = -EAGAIN;
  2957. goto out;
  2958. }
  2959. rc = 0;
  2960. ioc->base_cmds.status = MPT2_CMD_PENDING;
  2961. request = mpt2sas_base_get_msg_frame(ioc, smid);
  2962. ioc->base_cmds.smid = smid;
  2963. memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
  2964. if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2965. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
  2966. ioc->ioc_link_reset_in_progress = 1;
  2967. init_completion(&ioc->base_cmds.done);
  2968. mpt2sas_base_put_smid_default(ioc, smid);
  2969. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  2970. msecs_to_jiffies(10000));
  2971. if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  2972. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
  2973. ioc->ioc_link_reset_in_progress)
  2974. ioc->ioc_link_reset_in_progress = 0;
  2975. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  2976. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  2977. ioc->name, __func__);
  2978. _debug_dump_mf(mpi_request,
  2979. sizeof(Mpi2SasIoUnitControlRequest_t)/4);
  2980. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  2981. issue_reset = true;
  2982. goto issue_host_reset;
  2983. }
  2984. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  2985. memcpy(mpi_reply, ioc->base_cmds.reply,
  2986. sizeof(Mpi2SasIoUnitControlReply_t));
  2987. else
  2988. memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
  2989. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2990. goto out;
  2991. issue_host_reset:
  2992. if (issue_reset)
  2993. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  2994. FORCE_BIG_HAMMER);
  2995. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  2996. rc = -EFAULT;
  2997. out:
  2998. mutex_unlock(&ioc->base_cmds.mutex);
  2999. return rc;
  3000. }
  3001. /**
  3002. * mpt2sas_base_scsi_enclosure_processor - sending request to sep device
  3003. * @ioc: per adapter object
  3004. * @mpi_reply: the reply payload from FW
  3005. * @mpi_request: the request payload sent to FW
  3006. *
  3007. * The SCSI Enclosure Processor request message causes the IOC to
  3008. * communicate with SES devices to control LED status signals.
  3009. *
  3010. * Returns 0 for success, non-zero for failure.
  3011. */
  3012. int
  3013. mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc,
  3014. Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
  3015. {
  3016. u16 smid;
  3017. u32 ioc_state;
  3018. unsigned long timeleft;
  3019. bool issue_reset = false;
  3020. int rc;
  3021. void *request;
  3022. u16 wait_state_count;
  3023. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3024. __func__));
  3025. mutex_lock(&ioc->base_cmds.mutex);
  3026. if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
  3027. printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
  3028. ioc->name, __func__);
  3029. rc = -EAGAIN;
  3030. goto out;
  3031. }
  3032. wait_state_count = 0;
  3033. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  3034. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  3035. if (wait_state_count++ == 10) {
  3036. printk(MPT2SAS_ERR_FMT
  3037. "%s: failed due to ioc not operational\n",
  3038. ioc->name, __func__);
  3039. rc = -EFAULT;
  3040. goto out;
  3041. }
  3042. ssleep(1);
  3043. ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
  3044. printk(MPT2SAS_INFO_FMT "%s: waiting for "
  3045. "operational state(count=%d)\n", ioc->name,
  3046. __func__, wait_state_count);
  3047. }
  3048. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  3049. if (!smid) {
  3050. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  3051. ioc->name, __func__);
  3052. rc = -EAGAIN;
  3053. goto out;
  3054. }
  3055. rc = 0;
  3056. ioc->base_cmds.status = MPT2_CMD_PENDING;
  3057. request = mpt2sas_base_get_msg_frame(ioc, smid);
  3058. ioc->base_cmds.smid = smid;
  3059. memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
  3060. init_completion(&ioc->base_cmds.done);
  3061. mpt2sas_base_put_smid_default(ioc, smid);
  3062. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  3063. msecs_to_jiffies(10000));
  3064. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  3065. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  3066. ioc->name, __func__);
  3067. _debug_dump_mf(mpi_request,
  3068. sizeof(Mpi2SepRequest_t)/4);
  3069. if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
  3070. issue_reset = true;
  3071. goto issue_host_reset;
  3072. }
  3073. if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
  3074. memcpy(mpi_reply, ioc->base_cmds.reply,
  3075. sizeof(Mpi2SepReply_t));
  3076. else
  3077. memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
  3078. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3079. goto out;
  3080. issue_host_reset:
  3081. if (issue_reset)
  3082. mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  3083. FORCE_BIG_HAMMER);
  3084. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3085. rc = -EFAULT;
  3086. out:
  3087. mutex_unlock(&ioc->base_cmds.mutex);
  3088. return rc;
  3089. }
  3090. /**
  3091. * _base_get_port_facts - obtain port facts reply and save in ioc
  3092. * @ioc: per adapter object
  3093. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3094. *
  3095. * Returns 0 for success, non-zero for failure.
  3096. */
  3097. static int
  3098. _base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag)
  3099. {
  3100. Mpi2PortFactsRequest_t mpi_request;
  3101. Mpi2PortFactsReply_t mpi_reply;
  3102. struct mpt2sas_port_facts *pfacts;
  3103. int mpi_reply_sz, mpi_request_sz, r;
  3104. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3105. __func__));
  3106. mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
  3107. mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
  3108. memset(&mpi_request, 0, mpi_request_sz);
  3109. mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
  3110. mpi_request.PortNumber = port;
  3111. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  3112. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  3113. if (r != 0) {
  3114. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  3115. ioc->name, __func__, r);
  3116. return r;
  3117. }
  3118. pfacts = &ioc->pfacts[port];
  3119. memset(pfacts, 0, sizeof(struct mpt2sas_port_facts));
  3120. pfacts->PortNumber = mpi_reply.PortNumber;
  3121. pfacts->VP_ID = mpi_reply.VP_ID;
  3122. pfacts->VF_ID = mpi_reply.VF_ID;
  3123. pfacts->MaxPostedCmdBuffers =
  3124. le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
  3125. return 0;
  3126. }
  3127. /**
  3128. * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
  3129. * @ioc: per adapter object
  3130. * @timeout:
  3131. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3132. *
  3133. * Returns 0 for success, non-zero for failure.
  3134. */
  3135. static int
  3136. _base_wait_for_iocstate(struct MPT2SAS_ADAPTER *ioc, int timeout,
  3137. int sleep_flag)
  3138. {
  3139. u32 ioc_state, doorbell;
  3140. int rc;
  3141. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3142. __func__));
  3143. if (ioc->pci_error_recovery)
  3144. return 0;
  3145. doorbell = mpt2sas_base_get_iocstate(ioc, 0);
  3146. ioc_state = doorbell & MPI2_IOC_STATE_MASK;
  3147. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: ioc_state(0x%08x)\n",
  3148. ioc->name, __func__, ioc_state));
  3149. switch (ioc_state) {
  3150. case MPI2_IOC_STATE_READY:
  3151. case MPI2_IOC_STATE_OPERATIONAL:
  3152. return 0;
  3153. }
  3154. if (doorbell & MPI2_DOORBELL_USED) {
  3155. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT
  3156. "unexpected doorbell activ!e\n", ioc->name));
  3157. goto issue_diag_reset;
  3158. }
  3159. if (ioc_state == MPI2_IOC_STATE_FAULT) {
  3160. mpt2sas_base_fault_info(ioc, doorbell &
  3161. MPI2_DOORBELL_DATA_MASK);
  3162. goto issue_diag_reset;
  3163. }
  3164. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
  3165. timeout, sleep_flag);
  3166. if (ioc_state) {
  3167. printk(MPT2SAS_ERR_FMT
  3168. "%s: failed going to ready state (ioc_state=0x%x)\n",
  3169. ioc->name, __func__, ioc_state);
  3170. return -EFAULT;
  3171. }
  3172. issue_diag_reset:
  3173. rc = _base_diag_reset(ioc, sleep_flag);
  3174. return rc;
  3175. }
  3176. /**
  3177. * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
  3178. * @ioc: per adapter object
  3179. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3180. *
  3181. * Returns 0 for success, non-zero for failure.
  3182. */
  3183. static int
  3184. _base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3185. {
  3186. Mpi2IOCFactsRequest_t mpi_request;
  3187. Mpi2IOCFactsReply_t mpi_reply;
  3188. struct mpt2sas_facts *facts;
  3189. int mpi_reply_sz, mpi_request_sz, r;
  3190. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3191. __func__));
  3192. r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
  3193. if (r) {
  3194. printk(MPT2SAS_ERR_FMT "%s: failed getting to correct state\n",
  3195. ioc->name, __func__);
  3196. return r;
  3197. }
  3198. mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
  3199. mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
  3200. memset(&mpi_request, 0, mpi_request_sz);
  3201. mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
  3202. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  3203. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  3204. if (r != 0) {
  3205. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  3206. ioc->name, __func__, r);
  3207. return r;
  3208. }
  3209. facts = &ioc->facts;
  3210. memset(facts, 0, sizeof(struct mpt2sas_facts));
  3211. facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
  3212. facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
  3213. facts->VP_ID = mpi_reply.VP_ID;
  3214. facts->VF_ID = mpi_reply.VF_ID;
  3215. facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
  3216. facts->MaxChainDepth = mpi_reply.MaxChainDepth;
  3217. facts->WhoInit = mpi_reply.WhoInit;
  3218. facts->NumberOfPorts = mpi_reply.NumberOfPorts;
  3219. facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
  3220. facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
  3221. facts->MaxReplyDescriptorPostQueueDepth =
  3222. le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
  3223. facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
  3224. facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
  3225. if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
  3226. ioc->ir_firmware = 1;
  3227. if ((facts->IOCCapabilities &
  3228. MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
  3229. ioc->rdpq_array_capable = 1;
  3230. facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
  3231. facts->IOCRequestFrameSize =
  3232. le16_to_cpu(mpi_reply.IOCRequestFrameSize);
  3233. facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
  3234. facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
  3235. ioc->shost->max_id = -1;
  3236. facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
  3237. facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
  3238. facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
  3239. facts->HighPriorityCredit =
  3240. le16_to_cpu(mpi_reply.HighPriorityCredit);
  3241. facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
  3242. facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
  3243. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), "
  3244. "max chains per io(%d)\n", ioc->name, facts->RequestCredit,
  3245. facts->MaxChainDepth));
  3246. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), "
  3247. "reply frame size(%d)\n", ioc->name,
  3248. facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
  3249. return 0;
  3250. }
  3251. /**
  3252. * _base_send_ioc_init - send ioc_init to firmware
  3253. * @ioc: per adapter object
  3254. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3255. *
  3256. * Returns 0 for success, non-zero for failure.
  3257. */
  3258. static int
  3259. _base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3260. {
  3261. Mpi2IOCInitRequest_t mpi_request;
  3262. Mpi2IOCInitReply_t mpi_reply;
  3263. int i, r = 0;
  3264. struct timeval current_time;
  3265. u16 ioc_status;
  3266. u32 reply_post_free_array_sz = 0;
  3267. Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
  3268. dma_addr_t reply_post_free_array_dma;
  3269. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3270. __func__));
  3271. memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
  3272. mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
  3273. mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
  3274. mpi_request.VF_ID = 0; /* TODO */
  3275. mpi_request.VP_ID = 0;
  3276. mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
  3277. mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
  3278. if (_base_is_controller_msix_enabled(ioc))
  3279. mpi_request.HostMSIxVectors = ioc->reply_queue_count;
  3280. mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
  3281. mpi_request.ReplyDescriptorPostQueueDepth =
  3282. cpu_to_le16(ioc->reply_post_queue_depth);
  3283. mpi_request.ReplyFreeQueueDepth =
  3284. cpu_to_le16(ioc->reply_free_queue_depth);
  3285. mpi_request.SenseBufferAddressHigh =
  3286. cpu_to_le32((u64)ioc->sense_dma >> 32);
  3287. mpi_request.SystemReplyAddressHigh =
  3288. cpu_to_le32((u64)ioc->reply_dma >> 32);
  3289. mpi_request.SystemRequestFrameBaseAddress =
  3290. cpu_to_le64((u64)ioc->request_dma);
  3291. mpi_request.ReplyFreeQueueAddress =
  3292. cpu_to_le64((u64)ioc->reply_free_dma);
  3293. if (ioc->rdpq_array_enable) {
  3294. reply_post_free_array_sz = ioc->reply_queue_count *
  3295. sizeof(Mpi2IOCInitRDPQArrayEntry);
  3296. reply_post_free_array = pci_alloc_consistent(ioc->pdev,
  3297. reply_post_free_array_sz, &reply_post_free_array_dma);
  3298. if (!reply_post_free_array) {
  3299. printk(MPT2SAS_ERR_FMT
  3300. "reply_post_free_array: pci_alloc_consistent failed\n",
  3301. ioc->name);
  3302. r = -ENOMEM;
  3303. goto out;
  3304. }
  3305. memset(reply_post_free_array, 0, reply_post_free_array_sz);
  3306. for (i = 0; i < ioc->reply_queue_count; i++)
  3307. reply_post_free_array[i].RDPQBaseAddress =
  3308. cpu_to_le64(
  3309. (u64)ioc->reply_post[i].reply_post_free_dma);
  3310. mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
  3311. mpi_request.ReplyDescriptorPostQueueAddress =
  3312. cpu_to_le64((u64)reply_post_free_array_dma);
  3313. } else {
  3314. mpi_request.ReplyDescriptorPostQueueAddress =
  3315. cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
  3316. }
  3317. /* This time stamp specifies number of milliseconds
  3318. * since epoch ~ midnight January 1, 1970.
  3319. */
  3320. do_gettimeofday(&current_time);
  3321. mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
  3322. (current_time.tv_usec / 1000));
  3323. if (ioc->logging_level & MPT_DEBUG_INIT) {
  3324. __le32 *mfp;
  3325. int i;
  3326. mfp = (__le32 *)&mpi_request;
  3327. printk(KERN_INFO "\toffset:data\n");
  3328. for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
  3329. printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
  3330. le32_to_cpu(mfp[i]));
  3331. }
  3332. r = _base_handshake_req_reply_wait(ioc,
  3333. sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
  3334. sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
  3335. sleep_flag);
  3336. if (r != 0) {
  3337. printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
  3338. ioc->name, __func__, r);
  3339. goto out;
  3340. }
  3341. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
  3342. if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
  3343. mpi_reply.IOCLogInfo) {
  3344. printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__);
  3345. r = -EIO;
  3346. }
  3347. out:
  3348. if (reply_post_free_array)
  3349. pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
  3350. reply_post_free_array,
  3351. reply_post_free_array_dma);
  3352. return r;
  3353. }
  3354. /**
  3355. * mpt2sas_port_enable_done - command completion routine for port enable
  3356. * @ioc: per adapter object
  3357. * @smid: system request message index
  3358. * @msix_index: MSIX table index supplied by the OS
  3359. * @reply: reply message frame(lower 32bit addr)
  3360. *
  3361. * Return 1 meaning mf should be freed from _base_interrupt
  3362. * 0 means the mf is freed from this function.
  3363. */
  3364. u8
  3365. mpt2sas_port_enable_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  3366. u32 reply)
  3367. {
  3368. MPI2DefaultReply_t *mpi_reply;
  3369. u16 ioc_status;
  3370. mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
  3371. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  3372. return 1;
  3373. if (ioc->port_enable_cmds.status == MPT2_CMD_NOT_USED)
  3374. return 1;
  3375. ioc->port_enable_cmds.status |= MPT2_CMD_COMPLETE;
  3376. if (mpi_reply) {
  3377. ioc->port_enable_cmds.status |= MPT2_CMD_REPLY_VALID;
  3378. memcpy(ioc->port_enable_cmds.reply, mpi_reply,
  3379. mpi_reply->MsgLength*4);
  3380. }
  3381. ioc->port_enable_cmds.status &= ~MPT2_CMD_PENDING;
  3382. ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
  3383. if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
  3384. ioc->port_enable_failed = 1;
  3385. if (ioc->is_driver_loading) {
  3386. if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
  3387. mpt2sas_port_enable_complete(ioc);
  3388. return 1;
  3389. } else {
  3390. ioc->start_scan_failed = ioc_status;
  3391. ioc->start_scan = 0;
  3392. return 1;
  3393. }
  3394. }
  3395. complete(&ioc->port_enable_cmds.done);
  3396. return 1;
  3397. }
  3398. /**
  3399. * _base_send_port_enable - send port_enable(discovery stuff) to firmware
  3400. * @ioc: per adapter object
  3401. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3402. *
  3403. * Returns 0 for success, non-zero for failure.
  3404. */
  3405. static int
  3406. _base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3407. {
  3408. Mpi2PortEnableRequest_t *mpi_request;
  3409. Mpi2PortEnableReply_t *mpi_reply;
  3410. unsigned long timeleft;
  3411. int r = 0;
  3412. u16 smid;
  3413. u16 ioc_status;
  3414. printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
  3415. if (ioc->port_enable_cmds.status & MPT2_CMD_PENDING) {
  3416. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  3417. ioc->name, __func__);
  3418. return -EAGAIN;
  3419. }
  3420. smid = mpt2sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
  3421. if (!smid) {
  3422. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  3423. ioc->name, __func__);
  3424. return -EAGAIN;
  3425. }
  3426. ioc->port_enable_cmds.status = MPT2_CMD_PENDING;
  3427. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  3428. ioc->port_enable_cmds.smid = smid;
  3429. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  3430. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  3431. init_completion(&ioc->port_enable_cmds.done);
  3432. mpt2sas_base_put_smid_default(ioc, smid);
  3433. timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
  3434. 300*HZ);
  3435. if (!(ioc->port_enable_cmds.status & MPT2_CMD_COMPLETE)) {
  3436. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  3437. ioc->name, __func__);
  3438. _debug_dump_mf(mpi_request,
  3439. sizeof(Mpi2PortEnableRequest_t)/4);
  3440. if (ioc->port_enable_cmds.status & MPT2_CMD_RESET)
  3441. r = -EFAULT;
  3442. else
  3443. r = -ETIME;
  3444. goto out;
  3445. }
  3446. mpi_reply = ioc->port_enable_cmds.reply;
  3447. ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
  3448. if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
  3449. printk(MPT2SAS_ERR_FMT "%s: failed with (ioc_status=0x%08x)\n",
  3450. ioc->name, __func__, ioc_status);
  3451. r = -EFAULT;
  3452. goto out;
  3453. }
  3454. out:
  3455. ioc->port_enable_cmds.status = MPT2_CMD_NOT_USED;
  3456. printk(MPT2SAS_INFO_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
  3457. "SUCCESS" : "FAILED"));
  3458. return r;
  3459. }
  3460. /**
  3461. * mpt2sas_port_enable - initiate firmware discovery (don't wait for reply)
  3462. * @ioc: per adapter object
  3463. *
  3464. * Returns 0 for success, non-zero for failure.
  3465. */
  3466. int
  3467. mpt2sas_port_enable(struct MPT2SAS_ADAPTER *ioc)
  3468. {
  3469. Mpi2PortEnableRequest_t *mpi_request;
  3470. u16 smid;
  3471. printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
  3472. if (ioc->port_enable_cmds.status & MPT2_CMD_PENDING) {
  3473. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  3474. ioc->name, __func__);
  3475. return -EAGAIN;
  3476. }
  3477. smid = mpt2sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
  3478. if (!smid) {
  3479. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  3480. ioc->name, __func__);
  3481. return -EAGAIN;
  3482. }
  3483. ioc->port_enable_cmds.status = MPT2_CMD_PENDING;
  3484. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  3485. ioc->port_enable_cmds.smid = smid;
  3486. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  3487. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  3488. mpt2sas_base_put_smid_default(ioc, smid);
  3489. return 0;
  3490. }
  3491. /**
  3492. * _base_determine_wait_on_discovery - desposition
  3493. * @ioc: per adapter object
  3494. *
  3495. * Decide whether to wait on discovery to complete. Used to either
  3496. * locate boot device, or report volumes ahead of physical devices.
  3497. *
  3498. * Returns 1 for wait, 0 for don't wait
  3499. */
  3500. static int
  3501. _base_determine_wait_on_discovery(struct MPT2SAS_ADAPTER *ioc)
  3502. {
  3503. /* We wait for discovery to complete if IR firmware is loaded.
  3504. * The sas topology events arrive before PD events, so we need time to
  3505. * turn on the bit in ioc->pd_handles to indicate PD
  3506. * Also, it maybe required to report Volumes ahead of physical
  3507. * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
  3508. */
  3509. if (ioc->ir_firmware)
  3510. return 1;
  3511. /* if no Bios, then we don't need to wait */
  3512. if (!ioc->bios_pg3.BiosVersion)
  3513. return 0;
  3514. /* Bios is present, then we drop down here.
  3515. *
  3516. * If there any entries in the Bios Page 2, then we wait
  3517. * for discovery to complete.
  3518. */
  3519. /* Current Boot Device */
  3520. if ((ioc->bios_pg2.CurrentBootDeviceForm &
  3521. MPI2_BIOSPAGE2_FORM_MASK) ==
  3522. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
  3523. /* Request Boot Device */
  3524. (ioc->bios_pg2.ReqBootDeviceForm &
  3525. MPI2_BIOSPAGE2_FORM_MASK) ==
  3526. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
  3527. /* Alternate Request Boot Device */
  3528. (ioc->bios_pg2.ReqAltBootDeviceForm &
  3529. MPI2_BIOSPAGE2_FORM_MASK) ==
  3530. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
  3531. return 0;
  3532. return 1;
  3533. }
  3534. /**
  3535. * _base_unmask_events - turn on notification for this event
  3536. * @ioc: per adapter object
  3537. * @event: firmware event
  3538. *
  3539. * The mask is stored in ioc->event_masks.
  3540. */
  3541. static void
  3542. _base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event)
  3543. {
  3544. u32 desired_event;
  3545. if (event >= 128)
  3546. return;
  3547. desired_event = (1 << (event % 32));
  3548. if (event < 32)
  3549. ioc->event_masks[0] &= ~desired_event;
  3550. else if (event < 64)
  3551. ioc->event_masks[1] &= ~desired_event;
  3552. else if (event < 96)
  3553. ioc->event_masks[2] &= ~desired_event;
  3554. else if (event < 128)
  3555. ioc->event_masks[3] &= ~desired_event;
  3556. }
  3557. /**
  3558. * _base_event_notification - send event notification
  3559. * @ioc: per adapter object
  3560. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3561. *
  3562. * Returns 0 for success, non-zero for failure.
  3563. */
  3564. static int
  3565. _base_event_notification(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3566. {
  3567. Mpi2EventNotificationRequest_t *mpi_request;
  3568. unsigned long timeleft;
  3569. u16 smid;
  3570. int r = 0;
  3571. int i;
  3572. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3573. __func__));
  3574. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  3575. printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
  3576. ioc->name, __func__);
  3577. return -EAGAIN;
  3578. }
  3579. smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
  3580. if (!smid) {
  3581. printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
  3582. ioc->name, __func__);
  3583. return -EAGAIN;
  3584. }
  3585. ioc->base_cmds.status = MPT2_CMD_PENDING;
  3586. mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
  3587. ioc->base_cmds.smid = smid;
  3588. memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
  3589. mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
  3590. mpi_request->VF_ID = 0; /* TODO */
  3591. mpi_request->VP_ID = 0;
  3592. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  3593. mpi_request->EventMasks[i] =
  3594. cpu_to_le32(ioc->event_masks[i]);
  3595. init_completion(&ioc->base_cmds.done);
  3596. mpt2sas_base_put_smid_default(ioc, smid);
  3597. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
  3598. if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
  3599. printk(MPT2SAS_ERR_FMT "%s: timeout\n",
  3600. ioc->name, __func__);
  3601. _debug_dump_mf(mpi_request,
  3602. sizeof(Mpi2EventNotificationRequest_t)/4);
  3603. if (ioc->base_cmds.status & MPT2_CMD_RESET)
  3604. r = -EFAULT;
  3605. else
  3606. r = -ETIME;
  3607. } else
  3608. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: complete\n",
  3609. ioc->name, __func__));
  3610. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  3611. return r;
  3612. }
  3613. /**
  3614. * mpt2sas_base_validate_event_type - validating event types
  3615. * @ioc: per adapter object
  3616. * @event: firmware event
  3617. *
  3618. * This will turn on firmware event notification when application
  3619. * ask for that event. We don't mask events that are already enabled.
  3620. */
  3621. void
  3622. mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type)
  3623. {
  3624. int i, j;
  3625. u32 event_mask, desired_event;
  3626. u8 send_update_to_fw;
  3627. for (i = 0, send_update_to_fw = 0; i <
  3628. MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
  3629. event_mask = ~event_type[i];
  3630. desired_event = 1;
  3631. for (j = 0; j < 32; j++) {
  3632. if (!(event_mask & desired_event) &&
  3633. (ioc->event_masks[i] & desired_event)) {
  3634. ioc->event_masks[i] &= ~desired_event;
  3635. send_update_to_fw = 1;
  3636. }
  3637. desired_event = (desired_event << 1);
  3638. }
  3639. }
  3640. if (!send_update_to_fw)
  3641. return;
  3642. mutex_lock(&ioc->base_cmds.mutex);
  3643. _base_event_notification(ioc, CAN_SLEEP);
  3644. mutex_unlock(&ioc->base_cmds.mutex);
  3645. }
  3646. /**
  3647. * _base_diag_reset - the "big hammer" start of day reset
  3648. * @ioc: per adapter object
  3649. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3650. *
  3651. * Returns 0 for success, non-zero for failure.
  3652. */
  3653. static int
  3654. _base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3655. {
  3656. u32 host_diagnostic;
  3657. u32 ioc_state;
  3658. u32 count;
  3659. u32 hcb_size;
  3660. printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name);
  3661. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "clear interrupts\n",
  3662. ioc->name));
  3663. count = 0;
  3664. do {
  3665. /* Write magic sequence to WriteSequence register
  3666. * Loop until in diagnostic mode
  3667. */
  3668. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "write magic "
  3669. "sequence\n", ioc->name));
  3670. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  3671. writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
  3672. writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
  3673. writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
  3674. writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3675. writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3676. writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3677. /* wait 100 msec */
  3678. if (sleep_flag == CAN_SLEEP)
  3679. msleep(100);
  3680. else
  3681. mdelay(100);
  3682. if (count++ > 20)
  3683. goto out;
  3684. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  3685. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "wrote magic "
  3686. "sequence: count(%d), host_diagnostic(0x%08x)\n",
  3687. ioc->name, count, host_diagnostic));
  3688. } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
  3689. hcb_size = readl(&ioc->chip->HCBSize);
  3690. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "diag reset: issued\n",
  3691. ioc->name));
  3692. writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
  3693. &ioc->chip->HostDiagnostic);
  3694. /* This delay allows the chip PCIe hardware time to finish reset tasks*/
  3695. if (sleep_flag == CAN_SLEEP)
  3696. msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
  3697. else
  3698. mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
  3699. /* Approximately 300 second max wait */
  3700. for (count = 0; count < (300000000 /
  3701. MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
  3702. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  3703. if (host_diagnostic == 0xFFFFFFFF)
  3704. goto out;
  3705. if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
  3706. break;
  3707. /* Wait to pass the second read delay window */
  3708. if (sleep_flag == CAN_SLEEP)
  3709. msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
  3710. /1000);
  3711. else
  3712. mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
  3713. /1000);
  3714. }
  3715. if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
  3716. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter "
  3717. "assuming the HCB Address points to good F/W\n",
  3718. ioc->name));
  3719. host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
  3720. host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
  3721. writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  3722. drsprintk(ioc, printk(MPT2SAS_INFO_FMT
  3723. "re-enable the HCDW\n", ioc->name));
  3724. writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
  3725. &ioc->chip->HCBSize);
  3726. }
  3727. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter\n",
  3728. ioc->name));
  3729. writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
  3730. &ioc->chip->HostDiagnostic);
  3731. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "disable writes to the "
  3732. "diagnostic register\n", ioc->name));
  3733. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  3734. drsprintk(ioc, printk(MPT2SAS_INFO_FMT "Wait for FW to go to the "
  3735. "READY state\n", ioc->name));
  3736. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
  3737. sleep_flag);
  3738. if (ioc_state) {
  3739. printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
  3740. " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
  3741. goto out;
  3742. }
  3743. printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name);
  3744. return 0;
  3745. out:
  3746. printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name);
  3747. return -EFAULT;
  3748. }
  3749. /**
  3750. * _base_make_ioc_ready - put controller in READY state
  3751. * @ioc: per adapter object
  3752. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3753. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3754. *
  3755. * Returns 0 for success, non-zero for failure.
  3756. */
  3757. static int
  3758. _base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  3759. enum reset_type type)
  3760. {
  3761. u32 ioc_state;
  3762. int rc;
  3763. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3764. __func__));
  3765. if (ioc->pci_error_recovery)
  3766. return 0;
  3767. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  3768. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: ioc_state(0x%08x)\n",
  3769. ioc->name, __func__, ioc_state));
  3770. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
  3771. return 0;
  3772. if (ioc_state & MPI2_DOORBELL_USED) {
  3773. dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "unexpected doorbell "
  3774. "active!\n", ioc->name));
  3775. goto issue_diag_reset;
  3776. }
  3777. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  3778. mpt2sas_base_fault_info(ioc, ioc_state &
  3779. MPI2_DOORBELL_DATA_MASK);
  3780. goto issue_diag_reset;
  3781. }
  3782. if (type == FORCE_BIG_HAMMER)
  3783. goto issue_diag_reset;
  3784. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  3785. if (!(_base_send_ioc_reset(ioc,
  3786. MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
  3787. ioc->ioc_reset_count++;
  3788. return 0;
  3789. }
  3790. issue_diag_reset:
  3791. rc = _base_diag_reset(ioc, CAN_SLEEP);
  3792. ioc->ioc_reset_count++;
  3793. return rc;
  3794. }
  3795. /**
  3796. * _base_make_ioc_operational - put controller in OPERATIONAL state
  3797. * @ioc: per adapter object
  3798. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3799. *
  3800. * Returns 0 for success, non-zero for failure.
  3801. */
  3802. static int
  3803. _base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  3804. {
  3805. int r, i;
  3806. unsigned long flags;
  3807. u32 reply_address;
  3808. u16 smid;
  3809. struct _tr_list *delayed_tr, *delayed_tr_next;
  3810. u8 hide_flag;
  3811. struct adapter_reply_queue *reply_q;
  3812. long reply_post_free;
  3813. u32 reply_post_free_sz, index = 0;
  3814. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3815. __func__));
  3816. /* clean the delayed target reset list */
  3817. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3818. &ioc->delayed_tr_list, list) {
  3819. list_del(&delayed_tr->list);
  3820. kfree(delayed_tr);
  3821. }
  3822. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3823. &ioc->delayed_tr_volume_list, list) {
  3824. list_del(&delayed_tr->list);
  3825. kfree(delayed_tr);
  3826. }
  3827. /* initialize the scsi lookup free list */
  3828. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3829. INIT_LIST_HEAD(&ioc->free_list);
  3830. smid = 1;
  3831. for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
  3832. INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
  3833. ioc->scsi_lookup[i].cb_idx = 0xFF;
  3834. ioc->scsi_lookup[i].smid = smid;
  3835. ioc->scsi_lookup[i].scmd = NULL;
  3836. ioc->scsi_lookup[i].direct_io = 0;
  3837. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  3838. &ioc->free_list);
  3839. }
  3840. /* hi-priority queue */
  3841. INIT_LIST_HEAD(&ioc->hpr_free_list);
  3842. smid = ioc->hi_priority_smid;
  3843. for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
  3844. ioc->hpr_lookup[i].cb_idx = 0xFF;
  3845. ioc->hpr_lookup[i].smid = smid;
  3846. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  3847. &ioc->hpr_free_list);
  3848. }
  3849. /* internal queue */
  3850. INIT_LIST_HEAD(&ioc->internal_free_list);
  3851. smid = ioc->internal_smid;
  3852. for (i = 0; i < ioc->internal_depth; i++, smid++) {
  3853. ioc->internal_lookup[i].cb_idx = 0xFF;
  3854. ioc->internal_lookup[i].smid = smid;
  3855. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  3856. &ioc->internal_free_list);
  3857. }
  3858. /* chain pool */
  3859. INIT_LIST_HEAD(&ioc->free_chain_list);
  3860. for (i = 0; i < ioc->chain_depth; i++)
  3861. list_add_tail(&ioc->chain_lookup[i].tracker_list,
  3862. &ioc->free_chain_list);
  3863. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3864. /* initialize Reply Free Queue */
  3865. for (i = 0, reply_address = (u32)ioc->reply_dma ;
  3866. i < ioc->reply_free_queue_depth ; i++, reply_address +=
  3867. ioc->reply_sz)
  3868. ioc->reply_free[i] = cpu_to_le32(reply_address);
  3869. /* initialize reply queues */
  3870. if (ioc->is_driver_loading)
  3871. _base_assign_reply_queues(ioc);
  3872. /* initialize Reply Post Free Queue */
  3873. reply_post_free_sz = ioc->reply_post_queue_depth *
  3874. sizeof(Mpi2DefaultReplyDescriptor_t);
  3875. reply_post_free = (long)ioc->reply_post[index].reply_post_free;
  3876. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  3877. reply_q->reply_post_host_index = 0;
  3878. reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
  3879. reply_post_free;
  3880. for (i = 0; i < ioc->reply_post_queue_depth; i++)
  3881. reply_q->reply_post_free[i].Words =
  3882. cpu_to_le64(ULLONG_MAX);
  3883. if (!_base_is_controller_msix_enabled(ioc))
  3884. goto skip_init_reply_post_free_queue;
  3885. /*
  3886. * If RDPQ is enabled, switch to the next allocation.
  3887. * Otherwise advance within the contiguous region.
  3888. */
  3889. if (ioc->rdpq_array_enable)
  3890. reply_post_free = (long)
  3891. ioc->reply_post[++index].reply_post_free;
  3892. else
  3893. reply_post_free += reply_post_free_sz;
  3894. }
  3895. skip_init_reply_post_free_queue:
  3896. r = _base_send_ioc_init(ioc, sleep_flag);
  3897. if (r)
  3898. return r;
  3899. /* initialize reply free host index */
  3900. ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
  3901. writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
  3902. /* initialize reply post host index */
  3903. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  3904. writel(reply_q->msix_index << MPI2_RPHI_MSIX_INDEX_SHIFT,
  3905. &ioc->chip->ReplyPostHostIndex);
  3906. if (!_base_is_controller_msix_enabled(ioc))
  3907. goto skip_init_reply_post_host_index;
  3908. }
  3909. skip_init_reply_post_host_index:
  3910. _base_unmask_interrupts(ioc);
  3911. r = _base_event_notification(ioc, sleep_flag);
  3912. if (r)
  3913. return r;
  3914. if (sleep_flag == CAN_SLEEP)
  3915. _base_static_config_pages(ioc);
  3916. if (ioc->is_driver_loading) {
  3917. if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
  3918. == 0x80) {
  3919. hide_flag = (u8) (
  3920. le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
  3921. MFG_PAGE10_HIDE_SSDS_MASK);
  3922. if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
  3923. ioc->mfg_pg10_hide_flag = hide_flag;
  3924. }
  3925. ioc->wait_for_discovery_to_complete =
  3926. _base_determine_wait_on_discovery(ioc);
  3927. return r; /* scan_start and scan_finished support */
  3928. }
  3929. r = _base_send_port_enable(ioc, sleep_flag);
  3930. if (r)
  3931. return r;
  3932. return r;
  3933. }
  3934. /**
  3935. * mpt2sas_base_free_resources - free resources controller resources (io/irq/memap)
  3936. * @ioc: per adapter object
  3937. *
  3938. * Return nothing.
  3939. */
  3940. void
  3941. mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc)
  3942. {
  3943. struct pci_dev *pdev = ioc->pdev;
  3944. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3945. __func__));
  3946. /* synchronizing freeing resource with pci_access_mutex lock */
  3947. mutex_lock(&ioc->pci_access_mutex);
  3948. if (ioc->chip_phys && ioc->chip) {
  3949. _base_mask_interrupts(ioc);
  3950. ioc->shost_recovery = 1;
  3951. _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3952. ioc->shost_recovery = 0;
  3953. }
  3954. _base_free_irq(ioc);
  3955. _base_disable_msix(ioc);
  3956. if (ioc->chip_phys && ioc->chip)
  3957. iounmap(ioc->chip);
  3958. ioc->chip_phys = 0;
  3959. if (pci_is_enabled(pdev)) {
  3960. pci_release_selected_regions(ioc->pdev, ioc->bars);
  3961. pci_disable_pcie_error_reporting(pdev);
  3962. pci_disable_device(pdev);
  3963. }
  3964. mutex_unlock(&ioc->pci_access_mutex);
  3965. return;
  3966. }
  3967. /**
  3968. * mpt2sas_base_attach - attach controller instance
  3969. * @ioc: per adapter object
  3970. *
  3971. * Returns 0 for success, non-zero for failure.
  3972. */
  3973. int
  3974. mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc)
  3975. {
  3976. int r, i;
  3977. int cpu_id, last_cpu_id = 0;
  3978. dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  3979. __func__));
  3980. /* setup cpu_msix_table */
  3981. ioc->cpu_count = num_online_cpus();
  3982. for_each_online_cpu(cpu_id)
  3983. last_cpu_id = cpu_id;
  3984. ioc->cpu_msix_table_sz = last_cpu_id + 1;
  3985. ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
  3986. ioc->reply_queue_count = 1;
  3987. if (!ioc->cpu_msix_table) {
  3988. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation for "
  3989. "cpu_msix_table failed!!!\n", ioc->name));
  3990. r = -ENOMEM;
  3991. goto out_free_resources;
  3992. }
  3993. if (ioc->is_warpdrive) {
  3994. ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
  3995. sizeof(resource_size_t *), GFP_KERNEL);
  3996. if (!ioc->reply_post_host_index) {
  3997. dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation "
  3998. "for cpu_msix_table failed!!!\n", ioc->name));
  3999. r = -ENOMEM;
  4000. goto out_free_resources;
  4001. }
  4002. }
  4003. ioc->rdpq_array_enable_assigned = 0;
  4004. ioc->dma_mask = 0;
  4005. r = mpt2sas_base_map_resources(ioc);
  4006. if (r)
  4007. goto out_free_resources;
  4008. if (ioc->is_warpdrive) {
  4009. ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
  4010. &ioc->chip->ReplyPostHostIndex;
  4011. for (i = 1; i < ioc->cpu_msix_table_sz; i++)
  4012. ioc->reply_post_host_index[i] =
  4013. (resource_size_t __iomem *)
  4014. ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
  4015. * 4)));
  4016. }
  4017. pci_set_drvdata(ioc->pdev, ioc->shost);
  4018. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  4019. if (r)
  4020. goto out_free_resources;
  4021. r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  4022. if (r)
  4023. goto out_free_resources;
  4024. ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
  4025. sizeof(struct mpt2sas_port_facts), GFP_KERNEL);
  4026. if (!ioc->pfacts) {
  4027. r = -ENOMEM;
  4028. goto out_free_resources;
  4029. }
  4030. for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
  4031. r = _base_get_port_facts(ioc, i, CAN_SLEEP);
  4032. if (r)
  4033. goto out_free_resources;
  4034. }
  4035. r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
  4036. if (r)
  4037. goto out_free_resources;
  4038. init_waitqueue_head(&ioc->reset_wq);
  4039. /* allocate memory pd handle bitmask list */
  4040. ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
  4041. if (ioc->facts.MaxDevHandle % 8)
  4042. ioc->pd_handles_sz++;
  4043. ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
  4044. GFP_KERNEL);
  4045. if (!ioc->pd_handles) {
  4046. r = -ENOMEM;
  4047. goto out_free_resources;
  4048. }
  4049. ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
  4050. GFP_KERNEL);
  4051. if (!ioc->blocking_handles) {
  4052. r = -ENOMEM;
  4053. goto out_free_resources;
  4054. }
  4055. ioc->fwfault_debug = mpt2sas_fwfault_debug;
  4056. /* base internal command bits */
  4057. mutex_init(&ioc->base_cmds.mutex);
  4058. ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4059. ioc->base_cmds.status = MPT2_CMD_NOT_USED;
  4060. /* port_enable command bits */
  4061. ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4062. ioc->port_enable_cmds.status = MPT2_CMD_NOT_USED;
  4063. /* transport internal command bits */
  4064. ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4065. ioc->transport_cmds.status = MPT2_CMD_NOT_USED;
  4066. mutex_init(&ioc->transport_cmds.mutex);
  4067. /* scsih internal command bits */
  4068. ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4069. ioc->scsih_cmds.status = MPT2_CMD_NOT_USED;
  4070. mutex_init(&ioc->scsih_cmds.mutex);
  4071. /* task management internal command bits */
  4072. ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4073. ioc->tm_cmds.status = MPT2_CMD_NOT_USED;
  4074. mutex_init(&ioc->tm_cmds.mutex);
  4075. /* config page internal command bits */
  4076. ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4077. ioc->config_cmds.status = MPT2_CMD_NOT_USED;
  4078. mutex_init(&ioc->config_cmds.mutex);
  4079. /* ctl module internal command bits */
  4080. ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4081. ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  4082. ioc->ctl_cmds.status = MPT2_CMD_NOT_USED;
  4083. mutex_init(&ioc->ctl_cmds.mutex);
  4084. if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
  4085. !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
  4086. !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
  4087. !ioc->ctl_cmds.sense) {
  4088. r = -ENOMEM;
  4089. goto out_free_resources;
  4090. }
  4091. if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
  4092. !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
  4093. !ioc->config_cmds.reply || !ioc->ctl_cmds.reply) {
  4094. r = -ENOMEM;
  4095. goto out_free_resources;
  4096. }
  4097. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  4098. ioc->event_masks[i] = -1;
  4099. /* here we enable the events we care about */
  4100. _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
  4101. _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
  4102. _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
  4103. _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
  4104. _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
  4105. _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
  4106. _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
  4107. _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
  4108. _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
  4109. _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
  4110. _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
  4111. r = _base_make_ioc_operational(ioc, CAN_SLEEP);
  4112. if (r)
  4113. goto out_free_resources;
  4114. ioc->non_operational_loop = 0;
  4115. return 0;
  4116. out_free_resources:
  4117. ioc->remove_host = 1;
  4118. mpt2sas_base_free_resources(ioc);
  4119. _base_release_memory_pools(ioc);
  4120. pci_set_drvdata(ioc->pdev, NULL);
  4121. kfree(ioc->cpu_msix_table);
  4122. if (ioc->is_warpdrive)
  4123. kfree(ioc->reply_post_host_index);
  4124. kfree(ioc->pd_handles);
  4125. kfree(ioc->blocking_handles);
  4126. kfree(ioc->tm_cmds.reply);
  4127. kfree(ioc->transport_cmds.reply);
  4128. kfree(ioc->scsih_cmds.reply);
  4129. kfree(ioc->config_cmds.reply);
  4130. kfree(ioc->base_cmds.reply);
  4131. kfree(ioc->port_enable_cmds.reply);
  4132. kfree(ioc->ctl_cmds.reply);
  4133. kfree(ioc->ctl_cmds.sense);
  4134. kfree(ioc->pfacts);
  4135. ioc->ctl_cmds.reply = NULL;
  4136. ioc->base_cmds.reply = NULL;
  4137. ioc->tm_cmds.reply = NULL;
  4138. ioc->scsih_cmds.reply = NULL;
  4139. ioc->transport_cmds.reply = NULL;
  4140. ioc->config_cmds.reply = NULL;
  4141. ioc->pfacts = NULL;
  4142. return r;
  4143. }
  4144. /**
  4145. * mpt2sas_base_detach - remove controller instance
  4146. * @ioc: per adapter object
  4147. *
  4148. * Return nothing.
  4149. */
  4150. void
  4151. mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc)
  4152. {
  4153. dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
  4154. __func__));
  4155. mpt2sas_base_stop_watchdog(ioc);
  4156. mpt2sas_base_free_resources(ioc);
  4157. _base_release_memory_pools(ioc);
  4158. pci_set_drvdata(ioc->pdev, NULL);
  4159. kfree(ioc->cpu_msix_table);
  4160. if (ioc->is_warpdrive)
  4161. kfree(ioc->reply_post_host_index);
  4162. kfree(ioc->pd_handles);
  4163. kfree(ioc->blocking_handles);
  4164. kfree(ioc->pfacts);
  4165. kfree(ioc->ctl_cmds.reply);
  4166. kfree(ioc->ctl_cmds.sense);
  4167. kfree(ioc->base_cmds.reply);
  4168. kfree(ioc->port_enable_cmds.reply);
  4169. kfree(ioc->tm_cmds.reply);
  4170. kfree(ioc->transport_cmds.reply);
  4171. kfree(ioc->scsih_cmds.reply);
  4172. kfree(ioc->config_cmds.reply);
  4173. }
  4174. /**
  4175. * _base_reset_handler - reset callback handler (for base)
  4176. * @ioc: per adapter object
  4177. * @reset_phase: phase
  4178. *
  4179. * The handler for doing any required cleanup or initialization.
  4180. *
  4181. * The reset phase can be MPT2_IOC_PRE_RESET, MPT2_IOC_AFTER_RESET,
  4182. * MPT2_IOC_DONE_RESET
  4183. *
  4184. * Return nothing.
  4185. */
  4186. static void
  4187. _base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
  4188. {
  4189. mpt2sas_scsih_reset_handler(ioc, reset_phase);
  4190. mpt2sas_ctl_reset_handler(ioc, reset_phase);
  4191. switch (reset_phase) {
  4192. case MPT2_IOC_PRE_RESET:
  4193. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  4194. "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
  4195. break;
  4196. case MPT2_IOC_AFTER_RESET:
  4197. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  4198. "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
  4199. if (ioc->transport_cmds.status & MPT2_CMD_PENDING) {
  4200. ioc->transport_cmds.status |= MPT2_CMD_RESET;
  4201. mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid);
  4202. complete(&ioc->transport_cmds.done);
  4203. }
  4204. if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
  4205. ioc->base_cmds.status |= MPT2_CMD_RESET;
  4206. mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid);
  4207. complete(&ioc->base_cmds.done);
  4208. }
  4209. if (ioc->port_enable_cmds.status & MPT2_CMD_PENDING) {
  4210. ioc->port_enable_failed = 1;
  4211. ioc->port_enable_cmds.status |= MPT2_CMD_RESET;
  4212. mpt2sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
  4213. if (ioc->is_driver_loading) {
  4214. ioc->start_scan_failed =
  4215. MPI2_IOCSTATUS_INTERNAL_ERROR;
  4216. ioc->start_scan = 0;
  4217. ioc->port_enable_cmds.status =
  4218. MPT2_CMD_NOT_USED;
  4219. } else
  4220. complete(&ioc->port_enable_cmds.done);
  4221. }
  4222. if (ioc->config_cmds.status & MPT2_CMD_PENDING) {
  4223. ioc->config_cmds.status |= MPT2_CMD_RESET;
  4224. mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid);
  4225. ioc->config_cmds.smid = USHRT_MAX;
  4226. complete(&ioc->config_cmds.done);
  4227. }
  4228. break;
  4229. case MPT2_IOC_DONE_RESET:
  4230. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
  4231. "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
  4232. break;
  4233. }
  4234. }
  4235. /**
  4236. * _wait_for_commands_to_complete - reset controller
  4237. * @ioc: Pointer to MPT_ADAPTER structure
  4238. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  4239. *
  4240. * This function waiting(3s) for all pending commands to complete
  4241. * prior to putting controller in reset.
  4242. */
  4243. static void
  4244. _wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
  4245. {
  4246. u32 ioc_state;
  4247. unsigned long flags;
  4248. u16 i;
  4249. ioc->pending_io_count = 0;
  4250. if (sleep_flag != CAN_SLEEP)
  4251. return;
  4252. ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
  4253. if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
  4254. return;
  4255. /* pending command count */
  4256. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  4257. for (i = 0; i < ioc->scsiio_depth; i++)
  4258. if (ioc->scsi_lookup[i].cb_idx != 0xFF)
  4259. ioc->pending_io_count++;
  4260. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  4261. if (!ioc->pending_io_count)
  4262. return;
  4263. /* wait for pending commands to complete */
  4264. wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
  4265. }
  4266. /**
  4267. * mpt2sas_base_hard_reset_handler - reset controller
  4268. * @ioc: Pointer to MPT_ADAPTER structure
  4269. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  4270. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  4271. *
  4272. * Returns 0 for success, non-zero for failure.
  4273. */
  4274. int
  4275. mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
  4276. enum reset_type type)
  4277. {
  4278. int r;
  4279. unsigned long flags;
  4280. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: enter\n", ioc->name,
  4281. __func__));
  4282. if (ioc->pci_error_recovery) {
  4283. printk(MPT2SAS_ERR_FMT "%s: pci error recovery reset\n",
  4284. ioc->name, __func__);
  4285. r = 0;
  4286. goto out_unlocked;
  4287. }
  4288. if (mpt2sas_fwfault_debug)
  4289. mpt2sas_halt_firmware(ioc);
  4290. /* TODO - What we really should be doing is pulling
  4291. * out all the code associated with NO_SLEEP; its never used.
  4292. * That is legacy code from mpt fusion driver, ported over.
  4293. * I will leave this BUG_ON here for now till its been resolved.
  4294. */
  4295. BUG_ON(sleep_flag == NO_SLEEP);
  4296. /* wait for an active reset in progress to complete */
  4297. if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
  4298. do {
  4299. ssleep(1);
  4300. } while (ioc->shost_recovery == 1);
  4301. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
  4302. __func__));
  4303. return ioc->ioc_reset_in_progress_status;
  4304. }
  4305. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  4306. ioc->shost_recovery = 1;
  4307. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  4308. _base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
  4309. _wait_for_commands_to_complete(ioc, sleep_flag);
  4310. _base_mask_interrupts(ioc);
  4311. r = _base_make_ioc_ready(ioc, sleep_flag, type);
  4312. if (r)
  4313. goto out;
  4314. _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET);
  4315. /* If this hard reset is called while port enable is active, then
  4316. * there is no reason to call make_ioc_operational
  4317. */
  4318. if (ioc->is_driver_loading && ioc->port_enable_failed) {
  4319. ioc->remove_host = 1;
  4320. r = -EFAULT;
  4321. goto out;
  4322. }
  4323. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  4324. if (r)
  4325. goto out;
  4326. if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
  4327. panic("%s: Issue occurred with flashing controller firmware."
  4328. "Please reboot the system and ensure that the correct"
  4329. " firmware version is running\n", ioc->name);
  4330. r = _base_make_ioc_operational(ioc, sleep_flag);
  4331. if (!r)
  4332. _base_reset_handler(ioc, MPT2_IOC_DONE_RESET);
  4333. out:
  4334. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: %s\n",
  4335. ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
  4336. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  4337. ioc->ioc_reset_in_progress_status = r;
  4338. ioc->shost_recovery = 0;
  4339. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  4340. mutex_unlock(&ioc->reset_in_progress_mutex);
  4341. out_unlocked:
  4342. dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
  4343. __func__));
  4344. return r;
  4345. }