tegra132-norrin.dts 30 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra132.dtsi"
  4. / {
  5. model = "NVIDIA Tegra132 Norrin";
  6. compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";
  7. aliases {
  8. rtc0 = "/i2c@0,7000d000/as3722@40";
  9. rtc1 = "/rtc@0,7000e000";
  10. };
  11. chosen { };
  12. memory {
  13. device_type = "memory";
  14. reg = <0x0 0x80000000 0x0 0x80000000>;
  15. };
  16. host1x@0,50000000 {
  17. hdmi@0,54280000 {
  18. status = "disabled";
  19. vdd-supply = <&vdd_3v3_hdmi>;
  20. pll-supply = <&vdd_hdmi_pll>;
  21. hdmi-supply = <&vdd_5v0_hdmi>;
  22. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  23. nvidia,hpd-gpio =
  24. <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  25. };
  26. sor@0,54540000 {
  27. status = "okay";
  28. nvidia,dpaux = <&dpaux>;
  29. nvidia,panel = <&panel>;
  30. };
  31. dpaux: dpaux@0,545c0000 {
  32. vdd-supply = <&vdd_3v3_panel>;
  33. status = "okay";
  34. };
  35. };
  36. gpu@0,57000000 {
  37. status = "okay";
  38. vdd-supply = <&vdd_gpu>;
  39. };
  40. pinmux@0,70000868 {
  41. pinctrl-names = "default";
  42. pinctrl-0 = <&pinmux_default>;
  43. pinmux_default: pinmux@0 {
  44. dap_mclk1_pw4 {
  45. nvidia,pins = "dap_mclk1_pw4";
  46. nvidia,function = "extperiph1";
  47. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  48. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  49. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  50. };
  51. dap2_din_pa4 {
  52. nvidia,pins = "dap2_din_pa4";
  53. nvidia,function = "i2s1";
  54. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  55. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  56. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  57. };
  58. dap2_dout_pa5 {
  59. nvidia,pins = "dap2_dout_pa5",
  60. "dap2_fs_pa2",
  61. "dap2_sclk_pa3";
  62. nvidia,function = "i2s1";
  63. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  64. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  65. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  66. };
  67. dap3_dout_pp2 {
  68. nvidia,pins = "dap3_dout_pp2";
  69. nvidia,function = "i2s2";
  70. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  71. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  72. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  73. };
  74. dvfs_pwm_px0 {
  75. nvidia,pins = "dvfs_pwm_px0",
  76. "dvfs_clk_px2";
  77. nvidia,function = "cldvfs";
  78. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  79. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  80. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  81. };
  82. ulpi_clk_py0 {
  83. nvidia,pins = "ulpi_clk_py0",
  84. "ulpi_nxt_py2",
  85. "ulpi_stp_py3";
  86. nvidia,function = "spi1";
  87. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  88. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  89. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  90. };
  91. ulpi_dir_py1 {
  92. nvidia,pins = "ulpi_dir_py1";
  93. nvidia,function = "spi1";
  94. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  95. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  96. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  97. };
  98. cam_i2c_scl_pbb1 {
  99. nvidia,pins = "cam_i2c_scl_pbb1",
  100. "cam_i2c_sda_pbb2";
  101. nvidia,function = "i2c3";
  102. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  103. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  104. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  105. nvidia,lock = <TEGRA_PIN_DISABLE>;
  106. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  107. };
  108. gen2_i2c_scl_pt5 {
  109. nvidia,pins = "gen2_i2c_scl_pt5",
  110. "gen2_i2c_sda_pt6";
  111. nvidia,function = "i2c2";
  112. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  113. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  114. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  115. nvidia,lock = <TEGRA_PIN_DISABLE>;
  116. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  117. };
  118. pj7 {
  119. nvidia,pins = "pj7";
  120. nvidia,function = "uartd";
  121. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  122. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  124. };
  125. spdif_in_pk6 {
  126. nvidia,pins = "spdif_in_pk6";
  127. nvidia,function = "spdif";
  128. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  131. };
  132. pk7 {
  133. nvidia,pins = "pk7";
  134. nvidia,function = "uartd";
  135. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  136. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  137. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  138. };
  139. pg4 {
  140. nvidia,pins = "pg4",
  141. "pg5",
  142. "pg6",
  143. "pi3";
  144. nvidia,function = "spi4";
  145. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  146. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  147. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  148. };
  149. pg7 {
  150. nvidia,pins = "pg7";
  151. nvidia,function = "spi4";
  152. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  153. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  154. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  155. };
  156. ph1 {
  157. nvidia,pins = "ph1";
  158. nvidia,function = "pwm1";
  159. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  160. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  161. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  162. };
  163. pk0 {
  164. nvidia,pins = "pk0",
  165. "kb_row15_ps7",
  166. "clk_32k_out_pa0";
  167. nvidia,function = "soc";
  168. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  169. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  170. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  171. };
  172. sdmmc1_clk_pz0 {
  173. nvidia,pins = "sdmmc1_clk_pz0";
  174. nvidia,function = "sdmmc1";
  175. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  176. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  177. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  178. };
  179. sdmmc1_cmd_pz1 {
  180. nvidia,pins = "sdmmc1_cmd_pz1",
  181. "sdmmc1_dat0_py7",
  182. "sdmmc1_dat1_py6",
  183. "sdmmc1_dat2_py5",
  184. "sdmmc1_dat3_py4";
  185. nvidia,function = "sdmmc1";
  186. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  187. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  188. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  189. };
  190. sdmmc3_clk_pa6 {
  191. nvidia,pins = "sdmmc3_clk_pa6";
  192. nvidia,function = "sdmmc3";
  193. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  194. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  195. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  196. };
  197. sdmmc3_cmd_pa7 {
  198. nvidia,pins = "sdmmc3_cmd_pa7",
  199. "sdmmc3_dat0_pb7",
  200. "sdmmc3_dat1_pb6",
  201. "sdmmc3_dat2_pb5",
  202. "sdmmc3_dat3_pb4",
  203. "kb_col4_pq4",
  204. "sdmmc3_clk_lb_out_pee4",
  205. "sdmmc3_clk_lb_in_pee5",
  206. "sdmmc3_cd_n_pv2";
  207. nvidia,function = "sdmmc3";
  208. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  209. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  211. };
  212. sdmmc4_clk_pcc4 {
  213. nvidia,pins = "sdmmc4_clk_pcc4";
  214. nvidia,function = "sdmmc4";
  215. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  216. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  217. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  218. };
  219. sdmmc4_cmd_pt7 {
  220. nvidia,pins = "sdmmc4_cmd_pt7",
  221. "sdmmc4_dat0_paa0",
  222. "sdmmc4_dat1_paa1",
  223. "sdmmc4_dat2_paa2",
  224. "sdmmc4_dat3_paa3",
  225. "sdmmc4_dat4_paa4",
  226. "sdmmc4_dat5_paa5",
  227. "sdmmc4_dat6_paa6",
  228. "sdmmc4_dat7_paa7";
  229. nvidia,function = "sdmmc4";
  230. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  231. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  232. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  233. };
  234. mic_det_l {
  235. nvidia,pins = "kb_row7_pr7";
  236. nvidia,function = "rsvd2";
  237. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  238. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  239. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  240. };
  241. kb_row10_ps2 {
  242. nvidia,pins = "kb_row10_ps2";
  243. nvidia,function = "uarta";
  244. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  245. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  246. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  247. };
  248. kb_row9_ps1 {
  249. nvidia,pins = "kb_row9_ps1";
  250. nvidia,function = "uarta";
  251. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  252. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  253. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  254. };
  255. pwr_i2c_scl_pz6 {
  256. nvidia,pins = "pwr_i2c_scl_pz6",
  257. "pwr_i2c_sda_pz7";
  258. nvidia,function = "i2cpwr";
  259. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  260. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  261. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  262. nvidia,lock = <TEGRA_PIN_DISABLE>;
  263. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  264. };
  265. jtag_rtck {
  266. nvidia,pins = "jtag_rtck";
  267. nvidia,function = "rtck";
  268. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  269. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  270. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  271. };
  272. clk_32k_in {
  273. nvidia,pins = "clk_32k_in";
  274. nvidia,function = "clk";
  275. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  276. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  277. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  278. };
  279. core_pwr_req {
  280. nvidia,pins = "core_pwr_req";
  281. nvidia,function = "pwron";
  282. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  283. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  284. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  285. };
  286. cpu_pwr_req {
  287. nvidia,pins = "cpu_pwr_req";
  288. nvidia,function = "cpu";
  289. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  290. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  291. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  292. };
  293. kb_col0_ap {
  294. nvidia,pins = "kb_col0_pq0";
  295. nvidia,function = "rsvd4";
  296. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  297. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  298. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  299. };
  300. en_vdd_sd {
  301. nvidia,pins = "kb_row0_pr0";
  302. nvidia,function = "rsvd4";
  303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  305. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  306. };
  307. lid_open {
  308. nvidia,pins = "kb_row4_pr4";
  309. nvidia,function = "rsvd3";
  310. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  311. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  312. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  313. };
  314. pwr_int_n {
  315. nvidia,pins = "pwr_int_n";
  316. nvidia,function = "pmi";
  317. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  318. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  319. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  320. };
  321. reset_out_n {
  322. nvidia,pins = "reset_out_n";
  323. nvidia,function = "reset_out_n";
  324. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  325. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  326. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  327. };
  328. clk3_out_pee0 {
  329. nvidia,pins = "clk3_out_pee0";
  330. nvidia,function = "extperiph3";
  331. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  332. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  333. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  334. };
  335. gen1_i2c_scl_pc4 {
  336. nvidia,pins = "gen1_i2c_scl_pc4",
  337. "gen1_i2c_sda_pc5";
  338. nvidia,function = "i2c1";
  339. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  340. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  341. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  342. nvidia,lock = <TEGRA_PIN_DISABLE>;
  343. nvidia,open-drain = <TEGRA_PIN_ENABLE>;
  344. };
  345. hdmi_cec_pee3 {
  346. nvidia,pins = "hdmi_cec_pee3";
  347. nvidia,function = "cec";
  348. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  349. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  350. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  351. nvidia,lock = <TEGRA_PIN_DISABLE>;
  352. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  353. };
  354. hdmi_int_pn7 {
  355. nvidia,pins = "hdmi_int_pn7";
  356. nvidia,function = "rsvd1";
  357. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  358. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  359. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  360. };
  361. ddc_scl_pv4 {
  362. nvidia,pins = "ddc_scl_pv4",
  363. "ddc_sda_pv5";
  364. nvidia,function = "i2c4";
  365. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  366. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  367. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  368. nvidia,lock = <TEGRA_PIN_DISABLE>;
  369. nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
  370. };
  371. usb_vbus_en0_pn4 {
  372. nvidia,pins = "usb_vbus_en0_pn4",
  373. "usb_vbus_en1_pn5",
  374. "usb_vbus_en2_pff1";
  375. nvidia,function = "usb";
  376. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  377. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  378. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  379. nvidia,lock = <TEGRA_PIN_DISABLE>;
  380. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  381. };
  382. drive_sdio1 {
  383. nvidia,pins = "drive_sdio1";
  384. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  385. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  386. nvidia,pull-down-strength = <36>;
  387. nvidia,pull-up-strength = <20>;
  388. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
  389. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
  390. };
  391. drive_sdio3 {
  392. nvidia,pins = "drive_sdio3";
  393. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  394. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  395. nvidia,pull-down-strength = <22>;
  396. nvidia,pull-up-strength = <36>;
  397. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  398. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  399. };
  400. drive_gma {
  401. nvidia,pins = "drive_gma";
  402. nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
  403. nvidia,schmitt = <TEGRA_PIN_DISABLE>;
  404. nvidia,pull-down-strength = <2>;
  405. nvidia,pull-up-strength = <1>;
  406. nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  407. nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
  408. nvidia,drive-type = <1>;
  409. };
  410. ac_ok {
  411. nvidia,pins = "pj0";
  412. nvidia,function = "gmi";
  413. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  414. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  415. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  416. };
  417. codec_irq_l {
  418. nvidia,pins = "ph4";
  419. nvidia,function = "gmi";
  420. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  421. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  422. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  423. };
  424. lcd_bl_en {
  425. nvidia,pins = "ph2";
  426. nvidia,function = "gmi";
  427. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  428. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  429. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  430. };
  431. touch_irq_l {
  432. nvidia,pins = "gpio_w3_aud_pw3";
  433. nvidia,function = "spi6";
  434. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  435. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  436. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  437. };
  438. tpm_davint_l {
  439. nvidia,pins = "ph6";
  440. nvidia,function = "gmi";
  441. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  442. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  443. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  444. };
  445. ts_irq_l {
  446. nvidia,pins = "pk2";
  447. nvidia,function = "gmi";
  448. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  449. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  450. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  451. };
  452. ts_reset_l {
  453. nvidia,pins = "pk4";
  454. nvidia,function = "gmi";
  455. nvidia,pull = <1>;
  456. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  457. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  458. };
  459. ts_shdn_l {
  460. nvidia,pins = "pk1";
  461. nvidia,function = "gmi";
  462. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  463. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  464. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  465. };
  466. ph7 {
  467. nvidia,pins = "ph7";
  468. nvidia,function = "gmi";
  469. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  470. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  471. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  472. };
  473. sensor_irq_l {
  474. nvidia,pins = "pi6";
  475. nvidia,function = "gmi";
  476. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  477. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  478. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  479. };
  480. wifi_en {
  481. nvidia,pins = "gpio_x7_aud_px7";
  482. nvidia,function = "rsvd4";
  483. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  484. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  485. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  486. };
  487. chromeos_write_protect {
  488. nvidia,pins = "kb_row1_pr1";
  489. nvidia,function = "rsvd4";
  490. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  491. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  492. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  493. };
  494. hp_det_l {
  495. nvidia,pins = "pi7";
  496. nvidia,function = "rsvd1";
  497. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  498. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  499. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  500. };
  501. soc_warm_reset_l {
  502. nvidia,pins = "pi5";
  503. nvidia,function = "gmi";
  504. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  505. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  506. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  507. };
  508. };
  509. };
  510. serial@0,70006000 {
  511. status = "okay";
  512. };
  513. pwm: pwm@0,7000a000 {
  514. status = "okay";
  515. };
  516. /* HDMI DDC */
  517. hdmi_ddc: i2c@0,7000c700 {
  518. status = "okay";
  519. clock-frequency = <100000>;
  520. };
  521. i2c@0,7000d000 {
  522. status = "okay";
  523. clock-frequency = <400000>;
  524. as3722: pmic@40 {
  525. compatible = "ams,as3722";
  526. reg = <0x40>;
  527. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  528. ams,system-power-controller;
  529. #interrupt-cells = <2>;
  530. interrupt-controller;
  531. #gpio-cells = <2>;
  532. gpio-controller;
  533. pinctrl-names = "default";
  534. pinctrl-0 = <&as3722_default>;
  535. as3722_default: pinmux@0 {
  536. gpio0 {
  537. pins = "gpio0";
  538. function = "gpio";
  539. bias-pull-down;
  540. };
  541. gpio1 {
  542. pins = "gpio1";
  543. function = "gpio";
  544. bias-pull-up;
  545. };
  546. gpio2_4_7 {
  547. pins = "gpio2", "gpio4", "gpio7";
  548. function = "gpio";
  549. bias-pull-up;
  550. };
  551. gpio3 {
  552. pins = "gpio3";
  553. function = "gpio";
  554. bias-high-impedance;
  555. };
  556. gpio5 {
  557. pins = "gpio5";
  558. function = "clk32k-out";
  559. bias-pull-down;
  560. };
  561. gpio6 {
  562. pins = "gpio6";
  563. function = "clk32k-out";
  564. bias-pull-down;
  565. };
  566. };
  567. regulators {
  568. vsup-sd2-supply = <&vdd_5v0_sys>;
  569. vsup-sd3-supply = <&vdd_5v0_sys>;
  570. vsup-sd4-supply = <&vdd_5v0_sys>;
  571. vsup-sd5-supply = <&vdd_5v0_sys>;
  572. vin-ldo0-supply = <&vdd_1v35_lp0>;
  573. vin-ldo1-6-supply = <&vdd_3v3_sys>;
  574. vin-ldo2-5-7-supply = <&vddio_1v8>;
  575. vin-ldo3-4-supply = <&vdd_3v3_sys>;
  576. vin-ldo9-10-supply = <&vdd_5v0_sys>;
  577. vin-ldo11-supply = <&vdd_3v3_run>;
  578. sd0 {
  579. regulator-name = "+VDD_CPU_AP";
  580. regulator-min-microvolt = <700000>;
  581. regulator-max-microvolt = <1350000>;
  582. regulator-max-microamp = <3500000>;
  583. regulator-always-on;
  584. regulator-boot-on;
  585. ams,ext-control = <2>;
  586. };
  587. sd1 {
  588. regulator-name = "+VDD_CORE";
  589. regulator-min-microvolt = <700000>;
  590. regulator-max-microvolt = <1350000>;
  591. regulator-max-microamp = <4000000>;
  592. regulator-always-on;
  593. regulator-boot-on;
  594. ams,ext-control = <1>;
  595. };
  596. vdd_1v35_lp0: sd2 {
  597. regulator-name = "+1.35V_LP0(sd2)";
  598. regulator-min-microvolt = <1350000>;
  599. regulator-max-microvolt = <1350000>;
  600. regulator-always-on;
  601. regulator-boot-on;
  602. };
  603. sd3 {
  604. regulator-name = "+1.35V_LP0(sd3)";
  605. regulator-min-microvolt = <1350000>;
  606. regulator-max-microvolt = <1350000>;
  607. regulator-always-on;
  608. regulator-boot-on;
  609. };
  610. vdd_1v05_run: sd4 {
  611. regulator-name = "+1.05V_RUN";
  612. regulator-min-microvolt = <1050000>;
  613. regulator-max-microvolt = <1050000>;
  614. };
  615. vddio_1v8: sd5 {
  616. regulator-name = "+1.8V_VDDIO";
  617. regulator-min-microvolt = <1800000>;
  618. regulator-max-microvolt = <1800000>;
  619. regulator-always-on;
  620. regulator-boot-on;
  621. };
  622. vdd_gpu: sd6 {
  623. regulator-name = "+VDD_GPU_AP";
  624. regulator-min-microvolt = <800000>;
  625. regulator-max-microvolt = <1200000>;
  626. regulator-min-microamp = <3500000>;
  627. regulator-max-microamp = <3500000>;
  628. regulator-always-on;
  629. regulator-boot-on;
  630. };
  631. ldo0 {
  632. regulator-name = "+1.05_RUN_AVDD";
  633. regulator-min-microvolt = <1050000>;
  634. regulator-max-microvolt = <1050000>;
  635. regulator-always-on;
  636. regulator-boot-on;
  637. ams,ext-control = <1>;
  638. };
  639. ldo1 {
  640. regulator-name = "+1.8V_RUN_CAM";
  641. regulator-min-microvolt = <1800000>;
  642. regulator-max-microvolt = <1800000>;
  643. };
  644. ldo2 {
  645. regulator-name = "+1.2V_GEN_AVDD";
  646. regulator-min-microvolt = <1200000>;
  647. regulator-max-microvolt = <1200000>;
  648. regulator-always-on;
  649. regulator-boot-on;
  650. };
  651. ldo3 {
  652. regulator-name = "+1.00V_LP0_VDD_RTC";
  653. regulator-min-microvolt = <1000000>;
  654. regulator-max-microvolt = <1000000>;
  655. regulator-always-on;
  656. regulator-boot-on;
  657. ams,enable-tracking;
  658. };
  659. vdd_run_cam: ldo4 {
  660. regulator-name = "+2.8V_RUN_CAM";
  661. regulator-min-microvolt = <2800000>;
  662. regulator-max-microvolt = <2800000>;
  663. };
  664. ldo5 {
  665. regulator-name = "+1.2V_RUN_CAM_FRONT";
  666. regulator-min-microvolt = <1200000>;
  667. regulator-max-microvolt = <1200000>;
  668. };
  669. vddio_sdmmc3: ldo6 {
  670. regulator-name = "+VDDIO_SDMMC3";
  671. regulator-min-microvolt = <1800000>;
  672. regulator-max-microvolt = <3300000>;
  673. };
  674. ldo7 {
  675. regulator-name = "+1.05V_RUN_CAM_REAR";
  676. regulator-min-microvolt = <1050000>;
  677. regulator-max-microvolt = <1050000>;
  678. };
  679. ldo9 {
  680. regulator-name = "+2.8V_RUN_TOUCH";
  681. regulator-min-microvolt = <2800000>;
  682. regulator-max-microvolt = <2800000>;
  683. };
  684. ldo10 {
  685. regulator-name = "+2.8V_RUN_CAM_AF";
  686. regulator-min-microvolt = <2800000>;
  687. regulator-max-microvolt = <2800000>;
  688. };
  689. ldo11 {
  690. regulator-name = "+1.8V_RUN_VPP_FUSE";
  691. regulator-min-microvolt = <1800000>;
  692. regulator-max-microvolt = <1800000>;
  693. };
  694. };
  695. };
  696. };
  697. spi@0,7000d400 {
  698. status = "okay";
  699. ec: cros-ec@0 {
  700. compatible = "google,cros-ec-spi";
  701. spi-max-frequency = <3000000>;
  702. interrupt-parent = <&gpio>;
  703. interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
  704. reg = <0>;
  705. google,cros-ec-spi-msg-delay = <2000>;
  706. i2c_20: i2c-tunnel {
  707. compatible = "google,cros-ec-i2c-tunnel";
  708. #address-cells = <1>;
  709. #size-cells = <0>;
  710. google,remote-bus = <0>;
  711. charger: bq24735 {
  712. compatible = "ti,bq24735";
  713. reg = <0x9>;
  714. interrupt-parent = <&gpio>;
  715. interrupts = <TEGRA_GPIO(J, 0)
  716. GPIO_ACTIVE_HIGH>;
  717. ti,ac-detect-gpios = <&gpio
  718. TEGRA_GPIO(J, 0)
  719. GPIO_ACTIVE_HIGH>;
  720. };
  721. battery: smart-battery {
  722. compatible = "sbs,sbs-battery";
  723. reg = <0xb>;
  724. battery-name = "battery";
  725. sbs,i2c-retry-count = <2>;
  726. sbs,poll-retry-count = <10>;
  727. /* power-supplies = <&charger>; */
  728. };
  729. };
  730. keyboard-controller {
  731. compatible = "google,cros-ec-keyb";
  732. keypad,num-rows = <8>;
  733. keypad,num-columns = <13>;
  734. google,needs-ghost-filter;
  735. linux,keymap =
  736. <MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
  737. MATRIX_KEY(0x00, 0x02, KEY_F1)
  738. MATRIX_KEY(0x00, 0x03, KEY_B)
  739. MATRIX_KEY(0x00, 0x04, KEY_F10)
  740. MATRIX_KEY(0x00, 0x06, KEY_N)
  741. MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
  742. MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
  743. MATRIX_KEY(0x01, 0x01, KEY_ESC)
  744. MATRIX_KEY(0x01, 0x02, KEY_F4)
  745. MATRIX_KEY(0x01, 0x03, KEY_G)
  746. MATRIX_KEY(0x01, 0x04, KEY_F7)
  747. MATRIX_KEY(0x01, 0x06, KEY_H)
  748. MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
  749. MATRIX_KEY(0x01, 0x09, KEY_F9)
  750. MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
  751. MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
  752. MATRIX_KEY(0x02, 0x01, KEY_TAB)
  753. MATRIX_KEY(0x02, 0x02, KEY_F3)
  754. MATRIX_KEY(0x02, 0x03, KEY_T)
  755. MATRIX_KEY(0x02, 0x04, KEY_F6)
  756. MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
  757. MATRIX_KEY(0x02, 0x06, KEY_Y)
  758. MATRIX_KEY(0x02, 0x07, KEY_102ND)
  759. MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
  760. MATRIX_KEY(0x02, 0x09, KEY_F8)
  761. MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
  762. MATRIX_KEY(0x03, 0x02, KEY_F2)
  763. MATRIX_KEY(0x03, 0x03, KEY_5)
  764. MATRIX_KEY(0x03, 0x04, KEY_F5)
  765. MATRIX_KEY(0x03, 0x06, KEY_6)
  766. MATRIX_KEY(0x03, 0x08, KEY_MINUS)
  767. MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
  768. MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
  769. MATRIX_KEY(0x04, 0x01, KEY_A)
  770. MATRIX_KEY(0x04, 0x02, KEY_D)
  771. MATRIX_KEY(0x04, 0x03, KEY_F)
  772. MATRIX_KEY(0x04, 0x04, KEY_S)
  773. MATRIX_KEY(0x04, 0x05, KEY_K)
  774. MATRIX_KEY(0x04, 0x06, KEY_J)
  775. MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
  776. MATRIX_KEY(0x04, 0x09, KEY_L)
  777. MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
  778. MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
  779. MATRIX_KEY(0x05, 0x01, KEY_Z)
  780. MATRIX_KEY(0x05, 0x02, KEY_C)
  781. MATRIX_KEY(0x05, 0x03, KEY_V)
  782. MATRIX_KEY(0x05, 0x04, KEY_X)
  783. MATRIX_KEY(0x05, 0x05, KEY_COMMA)
  784. MATRIX_KEY(0x05, 0x06, KEY_M)
  785. MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
  786. MATRIX_KEY(0x05, 0x08, KEY_SLASH)
  787. MATRIX_KEY(0x05, 0x09, KEY_DOT)
  788. MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
  789. MATRIX_KEY(0x06, 0x01, KEY_1)
  790. MATRIX_KEY(0x06, 0x02, KEY_3)
  791. MATRIX_KEY(0x06, 0x03, KEY_4)
  792. MATRIX_KEY(0x06, 0x04, KEY_2)
  793. MATRIX_KEY(0x06, 0x05, KEY_8)
  794. MATRIX_KEY(0x06, 0x06, KEY_7)
  795. MATRIX_KEY(0x06, 0x08, KEY_0)
  796. MATRIX_KEY(0x06, 0x09, KEY_9)
  797. MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
  798. MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
  799. MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
  800. MATRIX_KEY(0x07, 0x01, KEY_Q)
  801. MATRIX_KEY(0x07, 0x02, KEY_E)
  802. MATRIX_KEY(0x07, 0x03, KEY_R)
  803. MATRIX_KEY(0x07, 0x04, KEY_W)
  804. MATRIX_KEY(0x07, 0x05, KEY_I)
  805. MATRIX_KEY(0x07, 0x06, KEY_U)
  806. MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
  807. MATRIX_KEY(0x07, 0x08, KEY_P)
  808. MATRIX_KEY(0x07, 0x09, KEY_O)
  809. MATRIX_KEY(0x07, 0x0b, KEY_UP)
  810. MATRIX_KEY(0x07, 0x0c, KEY_LEFT)>;
  811. };
  812. };
  813. };
  814. pmc@0,7000e400 {
  815. nvidia,invert-interrupt;
  816. nvidia,suspend-mode = <0>;
  817. #wake-cells = <3>;
  818. nvidia,cpu-pwr-good-time = <500>;
  819. nvidia,cpu-pwr-off-time = <300>;
  820. nvidia,core-pwr-good-time = <641 3845>;
  821. nvidia,core-pwr-off-time = <61036>;
  822. nvidia,core-power-req-active-high;
  823. nvidia,sys-clock-req-active-high;
  824. nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  825. };
  826. /* WIFI/BT module */
  827. sdhci@0,700b0000 {
  828. status = "disabled";
  829. };
  830. /* external SD/MMC */
  831. sdhci@0,700b0400 {
  832. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  833. power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
  834. wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
  835. status = "okay";
  836. bus-width = <4>;
  837. vqmmc-supply = <&vddio_sdmmc3>;
  838. };
  839. /* EMMC 4.51 */
  840. sdhci@0,700b0600 {
  841. status = "okay";
  842. bus-width = <8>;
  843. non-removable;
  844. };
  845. usb@0,7d000000 {
  846. status = "okay";
  847. };
  848. usb-phy@0,7d000000 {
  849. status = "okay";
  850. vbus-supply = <&vdd_usb1_vbus>;
  851. };
  852. usb@0,7d004000 {
  853. status = "okay";
  854. };
  855. usb-phy@0,7d004000 {
  856. status = "okay";
  857. vbus-supply = <&vdd_run_cam>;
  858. };
  859. usb@0,7d008000 {
  860. status = "okay";
  861. };
  862. usb-phy@0,7d008000 {
  863. status = "okay";
  864. vbus-supply = <&vdd_usb3_vbus>;
  865. };
  866. backlight: backlight {
  867. compatible = "pwm-backlight";
  868. enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  869. power-supply = <&vdd_led>;
  870. pwms = <&pwm 1 1000000>;
  871. brightness-levels = <0 4 8 16 32 64 128 255>;
  872. default-brightness-level = <6>;
  873. backlight-boot-off;
  874. };
  875. clocks {
  876. compatible = "simple-bus";
  877. #address-cells = <1>;
  878. #size-cells = <0>;
  879. clk32k_in: clock@0 {
  880. compatible = "fixed-clock";
  881. reg=<0>;
  882. #clock-cells = <0>;
  883. clock-frequency = <32768>;
  884. };
  885. };
  886. gpio-keys {
  887. compatible = "gpio-keys";
  888. lid {
  889. label = "Lid";
  890. gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
  891. linux,input-type = <5>;
  892. linux,code = <0>;
  893. debounce-interval = <1>;
  894. gpio-key,wakeup;
  895. };
  896. power {
  897. label = "Power";
  898. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  899. linux,code = <KEY_POWER>;
  900. debounce-interval = <10>;
  901. gpio-key,wakeup;
  902. };
  903. };
  904. panel: panel {
  905. compatible = "innolux,n116bge", "simple-panel";
  906. backlight = <&backlight>;
  907. ddc-i2c-bus = <&dpaux>;
  908. };
  909. regulators {
  910. compatible = "simple-bus";
  911. #address-cells = <1>;
  912. #size-cells = <0>;
  913. vdd_mux: regulator@0 {
  914. compatible = "regulator-fixed";
  915. reg = <0>;
  916. regulator-name = "+VDD_MUX";
  917. regulator-min-microvolt = <19000000>;
  918. regulator-max-microvolt = <19000000>;
  919. regulator-always-on;
  920. regulator-boot-on;
  921. };
  922. vdd_5v0_sys: regulator@1 {
  923. compatible = "regulator-fixed";
  924. reg = <1>;
  925. regulator-name = "+5V_SYS";
  926. regulator-min-microvolt = <5000000>;
  927. regulator-max-microvolt = <5000000>;
  928. regulator-always-on;
  929. regulator-boot-on;
  930. vin-supply = <&vdd_mux>;
  931. };
  932. vdd_3v3_sys: regulator@2 {
  933. compatible = "regulator-fixed";
  934. reg = <2>;
  935. regulator-name = "+3.3V_SYS";
  936. regulator-min-microvolt = <3300000>;
  937. regulator-max-microvolt = <3300000>;
  938. regulator-always-on;
  939. regulator-boot-on;
  940. vin-supply = <&vdd_mux>;
  941. };
  942. vdd_3v3_run: regulator@3 {
  943. compatible = "regulator-fixed";
  944. reg = <3>;
  945. regulator-name = "+3.3V_RUN";
  946. regulator-min-microvolt = <3300000>;
  947. regulator-max-microvolt = <3300000>;
  948. regulator-always-on;
  949. regulator-boot-on;
  950. gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
  951. enable-active-high;
  952. vin-supply = <&vdd_3v3_sys>;
  953. };
  954. vdd_3v3_hdmi: regulator@4 {
  955. compatible = "regulator-fixed";
  956. reg = <4>;
  957. regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
  958. regulator-min-microvolt = <3300000>;
  959. regulator-max-microvolt = <3300000>;
  960. vin-supply = <&vdd_3v3_run>;
  961. };
  962. vdd_led: regulator@5 {
  963. compatible = "regulator-fixed";
  964. reg = <5>;
  965. regulator-name = "+VDD_LED";
  966. regulator-min-microvolt = <3300000>;
  967. regulator-max-microvolt = <3300000>;
  968. gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  969. enable-active-high;
  970. vin-supply = <&vdd_mux>;
  971. };
  972. vdd_usb1_vbus: regulator@6 {
  973. compatible = "regulator-fixed";
  974. reg = <6>;
  975. regulator-name = "+5V_USB_HS";
  976. regulator-min-microvolt = <5000000>;
  977. regulator-max-microvolt = <5000000>;
  978. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  979. enable-active-high;
  980. gpio-open-drain;
  981. vin-supply = <&vdd_5v0_sys>;
  982. };
  983. vdd_usb3_vbus: regulator@7 {
  984. compatible = "regulator-fixed";
  985. reg = <7>;
  986. regulator-name = "+5V_USB_SS";
  987. regulator-min-microvolt = <5000000>;
  988. regulator-max-microvolt = <5000000>;
  989. gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
  990. enable-active-high;
  991. gpio-open-drain;
  992. vin-supply = <&vdd_5v0_sys>;
  993. };
  994. vdd_3v3_panel: regulator@8 {
  995. compatible = "regulator-fixed";
  996. reg = <8>;
  997. regulator-name = "+3.3V_PANEL";
  998. regulator-min-microvolt = <3300000>;
  999. regulator-max-microvolt = <3300000>;
  1000. gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
  1001. enable-active-high;
  1002. vin-supply = <&vdd_3v3_sys>;
  1003. };
  1004. vdd_hdmi_pll: regulator@9 {
  1005. compatible = "regulator-fixed";
  1006. reg = <9>;
  1007. regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";
  1008. regulator-min-microvolt = <1050000>;
  1009. regulator-max-microvolt = <1050000>;
  1010. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
  1011. vin-supply = <&vdd_1v05_run>;
  1012. };
  1013. vdd_5v0_hdmi: regulator@10 {
  1014. compatible = "regulator-fixed";
  1015. reg = <10>;
  1016. regulator-name = "+5V_HDMI_CON";
  1017. regulator-min-microvolt = <5000000>;
  1018. regulator-max-microvolt = <5000000>;
  1019. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1020. enable-active-high;
  1021. vin-supply = <&vdd_5v0_sys>;
  1022. };
  1023. vdd_5v0_ts: regulator@11 {
  1024. compatible = "regulator-fixed";
  1025. reg = <11>;
  1026. regulator-name = "+5V_VDD_TS";
  1027. regulator-min-microvolt = <5000000>;
  1028. regulator-max-microvolt = <5000000>;
  1029. regulator-always-on;
  1030. regulator-boot-on;
  1031. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  1032. enable-active-high;
  1033. };
  1034. };
  1035. };