hdmi5.c 18 KB

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  1. /*
  2. * HDMI driver for OMAP5
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated
  5. *
  6. * Authors:
  7. * Yong Zhi
  8. * Mythri pk
  9. * Archit Taneja <archit@ti.com>
  10. * Tomi Valkeinen <tomi.valkeinen@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License version 2 as published by
  14. * the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program. If not, see <http://www.gnu.org/licenses/>.
  23. */
  24. #define DSS_SUBSYS_NAME "HDMI"
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/err.h>
  28. #include <linux/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/string.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/clk.h>
  36. #include <linux/gpio.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/component.h>
  39. #include <linux/of.h>
  40. #include <video/omapdss.h>
  41. #include <sound/omap-hdmi-audio.h>
  42. #include "hdmi5_core.h"
  43. #include "dss.h"
  44. #include "dss_features.h"
  45. static struct omap_hdmi hdmi;
  46. static int hdmi_runtime_get(void)
  47. {
  48. int r;
  49. DSSDBG("hdmi_runtime_get\n");
  50. r = pm_runtime_get_sync(&hdmi.pdev->dev);
  51. WARN_ON(r < 0);
  52. if (r < 0)
  53. return r;
  54. return 0;
  55. }
  56. static void hdmi_runtime_put(void)
  57. {
  58. int r;
  59. DSSDBG("hdmi_runtime_put\n");
  60. r = pm_runtime_put_sync(&hdmi.pdev->dev);
  61. WARN_ON(r < 0 && r != -ENOSYS);
  62. }
  63. static irqreturn_t hdmi_irq_handler(int irq, void *data)
  64. {
  65. struct hdmi_wp_data *wp = data;
  66. u32 irqstatus;
  67. irqstatus = hdmi_wp_get_irqstatus(wp);
  68. hdmi_wp_set_irqstatus(wp, irqstatus);
  69. if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  70. irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  71. u32 v;
  72. /*
  73. * If we get both connect and disconnect interrupts at the same
  74. * time, turn off the PHY, clear interrupts, and restart, which
  75. * raises connect interrupt if a cable is connected, or nothing
  76. * if cable is not connected.
  77. */
  78. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  79. /*
  80. * We always get bogus CONNECT & DISCONNECT interrupts when
  81. * setting the PHY to LDOON. To ignore those, we force the RXDET
  82. * line to 0 until the PHY power state has been changed.
  83. */
  84. v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
  85. v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
  86. v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
  87. hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
  88. hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  89. HDMI_IRQ_LINK_DISCONNECT);
  90. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  91. REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
  92. } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  93. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  94. } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  95. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  96. }
  97. return IRQ_HANDLED;
  98. }
  99. static int hdmi_init_regulator(void)
  100. {
  101. struct regulator *reg;
  102. if (hdmi.vdda_reg != NULL)
  103. return 0;
  104. reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
  105. if (IS_ERR(reg)) {
  106. DSSERR("can't get VDDA regulator\n");
  107. return PTR_ERR(reg);
  108. }
  109. hdmi.vdda_reg = reg;
  110. return 0;
  111. }
  112. static int hdmi_power_on_core(struct omap_dss_device *dssdev)
  113. {
  114. int r;
  115. r = regulator_enable(hdmi.vdda_reg);
  116. if (r)
  117. return r;
  118. r = hdmi_runtime_get();
  119. if (r)
  120. goto err_runtime_get;
  121. /* Make selection of HDMI in DSS */
  122. dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
  123. hdmi.core_enabled = true;
  124. return 0;
  125. err_runtime_get:
  126. regulator_disable(hdmi.vdda_reg);
  127. return r;
  128. }
  129. static void hdmi_power_off_core(struct omap_dss_device *dssdev)
  130. {
  131. hdmi.core_enabled = false;
  132. hdmi_runtime_put();
  133. regulator_disable(hdmi.vdda_reg);
  134. }
  135. static int hdmi_power_on_full(struct omap_dss_device *dssdev)
  136. {
  137. int r;
  138. struct omap_video_timings *p;
  139. enum omap_channel channel = dssdev->dispc_channel;
  140. struct dss_pll_clock_info hdmi_cinfo = { 0 };
  141. unsigned pc;
  142. r = hdmi_power_on_core(dssdev);
  143. if (r)
  144. return r;
  145. p = &hdmi.cfg.timings;
  146. DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
  147. pc = p->pixelclock;
  148. if (p->double_pixel)
  149. pc *= 2;
  150. hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo);
  151. /* disable and clear irqs */
  152. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  153. hdmi_wp_set_irqstatus(&hdmi.wp,
  154. hdmi_wp_get_irqstatus(&hdmi.wp));
  155. r = dss_pll_enable(&hdmi.pll.pll);
  156. if (r) {
  157. DSSERR("Failed to enable PLL\n");
  158. goto err_pll_enable;
  159. }
  160. r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
  161. if (r) {
  162. DSSERR("Failed to configure PLL\n");
  163. goto err_pll_cfg;
  164. }
  165. r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
  166. hdmi_cinfo.clkout[0]);
  167. if (r) {
  168. DSSDBG("Failed to start PHY\n");
  169. goto err_phy_cfg;
  170. }
  171. r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
  172. if (r)
  173. goto err_phy_pwr;
  174. hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
  175. /* bypass TV gamma table */
  176. dispc_enable_gamma_table(0);
  177. /* tv size */
  178. dss_mgr_set_timings(channel, p);
  179. r = dss_mgr_enable(channel);
  180. if (r)
  181. goto err_mgr_enable;
  182. r = hdmi_wp_video_start(&hdmi.wp);
  183. if (r)
  184. goto err_vid_enable;
  185. hdmi_wp_set_irqenable(&hdmi.wp,
  186. HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
  187. return 0;
  188. err_vid_enable:
  189. dss_mgr_disable(channel);
  190. err_mgr_enable:
  191. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  192. err_phy_pwr:
  193. err_phy_cfg:
  194. err_pll_cfg:
  195. dss_pll_disable(&hdmi.pll.pll);
  196. err_pll_enable:
  197. hdmi_power_off_core(dssdev);
  198. return -EIO;
  199. }
  200. static void hdmi_power_off_full(struct omap_dss_device *dssdev)
  201. {
  202. enum omap_channel channel = dssdev->dispc_channel;
  203. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  204. hdmi_wp_video_stop(&hdmi.wp);
  205. dss_mgr_disable(channel);
  206. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  207. dss_pll_disable(&hdmi.pll.pll);
  208. hdmi_power_off_core(dssdev);
  209. }
  210. static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
  211. struct omap_video_timings *timings)
  212. {
  213. if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings))
  214. return -EINVAL;
  215. return 0;
  216. }
  217. static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
  218. struct omap_video_timings *timings)
  219. {
  220. mutex_lock(&hdmi.lock);
  221. hdmi.cfg.timings = *timings;
  222. dispc_set_tv_pclk(timings->pixelclock);
  223. mutex_unlock(&hdmi.lock);
  224. }
  225. static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
  226. struct omap_video_timings *timings)
  227. {
  228. *timings = hdmi.cfg.timings;
  229. }
  230. static void hdmi_dump_regs(struct seq_file *s)
  231. {
  232. mutex_lock(&hdmi.lock);
  233. if (hdmi_runtime_get()) {
  234. mutex_unlock(&hdmi.lock);
  235. return;
  236. }
  237. hdmi_wp_dump(&hdmi.wp, s);
  238. hdmi_pll_dump(&hdmi.pll, s);
  239. hdmi_phy_dump(&hdmi.phy, s);
  240. hdmi5_core_dump(&hdmi.core, s);
  241. hdmi_runtime_put();
  242. mutex_unlock(&hdmi.lock);
  243. }
  244. static int read_edid(u8 *buf, int len)
  245. {
  246. int r;
  247. int idlemode;
  248. mutex_lock(&hdmi.lock);
  249. r = hdmi_runtime_get();
  250. BUG_ON(r);
  251. idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  252. /* No-idle mode */
  253. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  254. r = hdmi5_read_edid(&hdmi.core, buf, len);
  255. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
  256. hdmi_runtime_put();
  257. mutex_unlock(&hdmi.lock);
  258. return r;
  259. }
  260. static void hdmi_start_audio_stream(struct omap_hdmi *hd)
  261. {
  262. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  263. hdmi_wp_audio_enable(&hd->wp, true);
  264. hdmi_wp_audio_core_req_enable(&hd->wp, true);
  265. }
  266. static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
  267. {
  268. hdmi_wp_audio_core_req_enable(&hd->wp, false);
  269. hdmi_wp_audio_enable(&hd->wp, false);
  270. REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
  271. }
  272. static int hdmi_display_enable(struct omap_dss_device *dssdev)
  273. {
  274. struct omap_dss_device *out = &hdmi.output;
  275. unsigned long flags;
  276. int r = 0;
  277. DSSDBG("ENTER hdmi_display_enable\n");
  278. mutex_lock(&hdmi.lock);
  279. if (!out->dispc_channel_connected) {
  280. DSSERR("failed to enable display: no output/manager\n");
  281. r = -ENODEV;
  282. goto err0;
  283. }
  284. r = hdmi_power_on_full(dssdev);
  285. if (r) {
  286. DSSERR("failed to power on device\n");
  287. goto err0;
  288. }
  289. if (hdmi.audio_configured) {
  290. r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
  291. hdmi.cfg.timings.pixelclock);
  292. if (r) {
  293. DSSERR("Error restoring audio configuration: %d", r);
  294. hdmi.audio_abort_cb(&hdmi.pdev->dev);
  295. hdmi.audio_configured = false;
  296. }
  297. }
  298. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  299. if (hdmi.audio_configured && hdmi.audio_playing)
  300. hdmi_start_audio_stream(&hdmi);
  301. hdmi.display_enabled = true;
  302. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  303. mutex_unlock(&hdmi.lock);
  304. return 0;
  305. err0:
  306. mutex_unlock(&hdmi.lock);
  307. return r;
  308. }
  309. static void hdmi_display_disable(struct omap_dss_device *dssdev)
  310. {
  311. unsigned long flags;
  312. DSSDBG("Enter hdmi_display_disable\n");
  313. mutex_lock(&hdmi.lock);
  314. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  315. hdmi_stop_audio_stream(&hdmi);
  316. hdmi.display_enabled = false;
  317. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  318. hdmi_power_off_full(dssdev);
  319. mutex_unlock(&hdmi.lock);
  320. }
  321. static int hdmi_core_enable(struct omap_dss_device *dssdev)
  322. {
  323. int r = 0;
  324. DSSDBG("ENTER omapdss_hdmi_core_enable\n");
  325. mutex_lock(&hdmi.lock);
  326. r = hdmi_power_on_core(dssdev);
  327. if (r) {
  328. DSSERR("failed to power on device\n");
  329. goto err0;
  330. }
  331. mutex_unlock(&hdmi.lock);
  332. return 0;
  333. err0:
  334. mutex_unlock(&hdmi.lock);
  335. return r;
  336. }
  337. static void hdmi_core_disable(struct omap_dss_device *dssdev)
  338. {
  339. DSSDBG("Enter omapdss_hdmi_core_disable\n");
  340. mutex_lock(&hdmi.lock);
  341. hdmi_power_off_core(dssdev);
  342. mutex_unlock(&hdmi.lock);
  343. }
  344. static int hdmi_connect(struct omap_dss_device *dssdev,
  345. struct omap_dss_device *dst)
  346. {
  347. enum omap_channel channel = dssdev->dispc_channel;
  348. int r;
  349. r = hdmi_init_regulator();
  350. if (r)
  351. return r;
  352. r = dss_mgr_connect(channel, dssdev);
  353. if (r)
  354. return r;
  355. r = omapdss_output_set_device(dssdev, dst);
  356. if (r) {
  357. DSSERR("failed to connect output to new device: %s\n",
  358. dst->name);
  359. dss_mgr_disconnect(channel, dssdev);
  360. return r;
  361. }
  362. return 0;
  363. }
  364. static void hdmi_disconnect(struct omap_dss_device *dssdev,
  365. struct omap_dss_device *dst)
  366. {
  367. enum omap_channel channel = dssdev->dispc_channel;
  368. WARN_ON(dst != dssdev->dst);
  369. if (dst != dssdev->dst)
  370. return;
  371. omapdss_output_unset_device(dssdev);
  372. dss_mgr_disconnect(channel, dssdev);
  373. }
  374. static int hdmi_read_edid(struct omap_dss_device *dssdev,
  375. u8 *edid, int len)
  376. {
  377. bool need_enable;
  378. int r;
  379. need_enable = hdmi.core_enabled == false;
  380. if (need_enable) {
  381. r = hdmi_core_enable(dssdev);
  382. if (r)
  383. return r;
  384. }
  385. r = read_edid(edid, len);
  386. if (need_enable)
  387. hdmi_core_disable(dssdev);
  388. return r;
  389. }
  390. static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
  391. const struct hdmi_avi_infoframe *avi)
  392. {
  393. hdmi.cfg.infoframe = *avi;
  394. return 0;
  395. }
  396. static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
  397. bool hdmi_mode)
  398. {
  399. hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
  400. return 0;
  401. }
  402. static const struct omapdss_hdmi_ops hdmi_ops = {
  403. .connect = hdmi_connect,
  404. .disconnect = hdmi_disconnect,
  405. .enable = hdmi_display_enable,
  406. .disable = hdmi_display_disable,
  407. .check_timings = hdmi_display_check_timing,
  408. .set_timings = hdmi_display_set_timing,
  409. .get_timings = hdmi_display_get_timings,
  410. .read_edid = hdmi_read_edid,
  411. .set_infoframe = hdmi_set_infoframe,
  412. .set_hdmi_mode = hdmi_set_hdmi_mode,
  413. };
  414. static void hdmi_init_output(struct platform_device *pdev)
  415. {
  416. struct omap_dss_device *out = &hdmi.output;
  417. out->dev = &pdev->dev;
  418. out->id = OMAP_DSS_OUTPUT_HDMI;
  419. out->output_type = OMAP_DISPLAY_TYPE_HDMI;
  420. out->name = "hdmi.0";
  421. out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
  422. out->ops.hdmi = &hdmi_ops;
  423. out->owner = THIS_MODULE;
  424. omapdss_register_output(out);
  425. }
  426. static void hdmi_uninit_output(struct platform_device *pdev)
  427. {
  428. struct omap_dss_device *out = &hdmi.output;
  429. omapdss_unregister_output(out);
  430. }
  431. static int hdmi_probe_of(struct platform_device *pdev)
  432. {
  433. struct device_node *node = pdev->dev.of_node;
  434. struct device_node *ep;
  435. int r;
  436. ep = omapdss_of_get_first_endpoint(node);
  437. if (!ep)
  438. return 0;
  439. r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
  440. if (r)
  441. goto err;
  442. of_node_put(ep);
  443. return 0;
  444. err:
  445. of_node_put(ep);
  446. return r;
  447. }
  448. /* Audio callbacks */
  449. static int hdmi_audio_startup(struct device *dev,
  450. void (*abort_cb)(struct device *dev))
  451. {
  452. struct omap_hdmi *hd = dev_get_drvdata(dev);
  453. int ret = 0;
  454. mutex_lock(&hd->lock);
  455. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  456. ret = -EPERM;
  457. goto out;
  458. }
  459. hd->audio_abort_cb = abort_cb;
  460. out:
  461. mutex_unlock(&hd->lock);
  462. return ret;
  463. }
  464. static int hdmi_audio_shutdown(struct device *dev)
  465. {
  466. struct omap_hdmi *hd = dev_get_drvdata(dev);
  467. mutex_lock(&hd->lock);
  468. hd->audio_abort_cb = NULL;
  469. hd->audio_configured = false;
  470. hd->audio_playing = false;
  471. mutex_unlock(&hd->lock);
  472. return 0;
  473. }
  474. static int hdmi_audio_start(struct device *dev)
  475. {
  476. struct omap_hdmi *hd = dev_get_drvdata(dev);
  477. unsigned long flags;
  478. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  479. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  480. if (hd->display_enabled)
  481. hdmi_start_audio_stream(hd);
  482. hd->audio_playing = true;
  483. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  484. return 0;
  485. }
  486. static void hdmi_audio_stop(struct device *dev)
  487. {
  488. struct omap_hdmi *hd = dev_get_drvdata(dev);
  489. unsigned long flags;
  490. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  491. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  492. if (hd->display_enabled)
  493. hdmi_stop_audio_stream(hd);
  494. hd->audio_playing = false;
  495. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  496. }
  497. static int hdmi_audio_config(struct device *dev,
  498. struct omap_dss_audio *dss_audio)
  499. {
  500. struct omap_hdmi *hd = dev_get_drvdata(dev);
  501. int ret;
  502. mutex_lock(&hd->lock);
  503. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  504. ret = -EPERM;
  505. goto out;
  506. }
  507. ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
  508. hd->cfg.timings.pixelclock);
  509. if (!ret) {
  510. hd->audio_configured = true;
  511. hd->audio_config = *dss_audio;
  512. }
  513. out:
  514. mutex_unlock(&hd->lock);
  515. return ret;
  516. }
  517. static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
  518. .audio_startup = hdmi_audio_startup,
  519. .audio_shutdown = hdmi_audio_shutdown,
  520. .audio_start = hdmi_audio_start,
  521. .audio_stop = hdmi_audio_stop,
  522. .audio_config = hdmi_audio_config,
  523. };
  524. static int hdmi_audio_register(struct device *dev)
  525. {
  526. struct omap_hdmi_audio_pdata pdata = {
  527. .dev = dev,
  528. .dss_version = omapdss_get_version(),
  529. .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
  530. .ops = &hdmi_audio_ops,
  531. };
  532. hdmi.audio_pdev = platform_device_register_data(
  533. dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
  534. &pdata, sizeof(pdata));
  535. if (IS_ERR(hdmi.audio_pdev))
  536. return PTR_ERR(hdmi.audio_pdev);
  537. hdmi_runtime_get();
  538. hdmi.wp_idlemode =
  539. REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  540. hdmi_runtime_put();
  541. return 0;
  542. }
  543. /* HDMI HW IP initialisation */
  544. static int hdmi5_bind(struct device *dev, struct device *master, void *data)
  545. {
  546. struct platform_device *pdev = to_platform_device(dev);
  547. int r;
  548. int irq;
  549. hdmi.pdev = pdev;
  550. dev_set_drvdata(&pdev->dev, &hdmi);
  551. mutex_init(&hdmi.lock);
  552. spin_lock_init(&hdmi.audio_playing_lock);
  553. if (pdev->dev.of_node) {
  554. r = hdmi_probe_of(pdev);
  555. if (r)
  556. return r;
  557. }
  558. r = hdmi_wp_init(pdev, &hdmi.wp);
  559. if (r)
  560. return r;
  561. r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
  562. if (r)
  563. return r;
  564. r = hdmi_phy_init(pdev, &hdmi.phy);
  565. if (r)
  566. goto err;
  567. r = hdmi5_core_init(pdev, &hdmi.core);
  568. if (r)
  569. goto err;
  570. irq = platform_get_irq(pdev, 0);
  571. if (irq < 0) {
  572. DSSERR("platform_get_irq failed\n");
  573. r = -ENODEV;
  574. goto err;
  575. }
  576. r = devm_request_threaded_irq(&pdev->dev, irq,
  577. NULL, hdmi_irq_handler,
  578. IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
  579. if (r) {
  580. DSSERR("HDMI IRQ request failed\n");
  581. goto err;
  582. }
  583. pm_runtime_enable(&pdev->dev);
  584. hdmi_init_output(pdev);
  585. r = hdmi_audio_register(&pdev->dev);
  586. if (r) {
  587. DSSERR("Registering HDMI audio failed %d\n", r);
  588. hdmi_uninit_output(pdev);
  589. pm_runtime_disable(&pdev->dev);
  590. return r;
  591. }
  592. dss_debugfs_create_file("hdmi", hdmi_dump_regs);
  593. return 0;
  594. err:
  595. hdmi_pll_uninit(&hdmi.pll);
  596. return r;
  597. }
  598. static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
  599. {
  600. struct platform_device *pdev = to_platform_device(dev);
  601. if (hdmi.audio_pdev)
  602. platform_device_unregister(hdmi.audio_pdev);
  603. hdmi_uninit_output(pdev);
  604. hdmi_pll_uninit(&hdmi.pll);
  605. pm_runtime_disable(&pdev->dev);
  606. }
  607. static const struct component_ops hdmi5_component_ops = {
  608. .bind = hdmi5_bind,
  609. .unbind = hdmi5_unbind,
  610. };
  611. static int hdmi5_probe(struct platform_device *pdev)
  612. {
  613. return component_add(&pdev->dev, &hdmi5_component_ops);
  614. }
  615. static int hdmi5_remove(struct platform_device *pdev)
  616. {
  617. component_del(&pdev->dev, &hdmi5_component_ops);
  618. return 0;
  619. }
  620. static int hdmi_runtime_suspend(struct device *dev)
  621. {
  622. dispc_runtime_put();
  623. return 0;
  624. }
  625. static int hdmi_runtime_resume(struct device *dev)
  626. {
  627. int r;
  628. r = dispc_runtime_get();
  629. if (r < 0)
  630. return r;
  631. return 0;
  632. }
  633. static const struct dev_pm_ops hdmi_pm_ops = {
  634. .runtime_suspend = hdmi_runtime_suspend,
  635. .runtime_resume = hdmi_runtime_resume,
  636. };
  637. static const struct of_device_id hdmi_of_match[] = {
  638. { .compatible = "ti,omap5-hdmi", },
  639. { .compatible = "ti,dra7-hdmi", },
  640. {},
  641. };
  642. static struct platform_driver omapdss_hdmihw_driver = {
  643. .probe = hdmi5_probe,
  644. .remove = hdmi5_remove,
  645. .driver = {
  646. .name = "omapdss_hdmi5",
  647. .pm = &hdmi_pm_ops,
  648. .of_match_table = hdmi_of_match,
  649. .suppress_bind_attrs = true,
  650. },
  651. };
  652. int __init hdmi5_init_platform_driver(void)
  653. {
  654. return platform_driver_register(&omapdss_hdmihw_driver);
  655. }
  656. void hdmi5_uninit_platform_driver(void)
  657. {
  658. platform_driver_unregister(&omapdss_hdmihw_driver);
  659. }