 Andrew Bresticker
|
15d68e8c2e
clk: tegra: Initialize UTMI PLL when enabling PLLU
|
пре 9 година |
 Rhyland Klein
|
926655f929
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
|
пре 9 година |
 Thierry Reding
|
1ec7032ad5
clk: tegra: Add fixed factor peripheral clock type
|
пре 10 година |
|
Thierry Reding
|
7e14f22305
clk: tegra: Constify peripheral clock registers
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пре 10 година |
|
Rhyland Klein
|
6b301a059e
clk: tegra: Add support for Tegra210 clocks
|
пре 10 година |
 Bill Huang
|
139fd30943
clk: tegra: Add Super Gen5 Logic
|
пре 10 година |
|
Bill Huang
|
0ef9db6cf2
clk: tegra: pll: Add logic for SS
|
пре 10 година |
|
Rhyland Klein
|
17e9273a9e
clk: tegra: pll: Add dyn_ramp callback
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пре 10 година |
|
Bill Huang
|
b985114e2f
clk: tegra: pll: Add Set_default logic
|
пре 10 година |
|
Bill Huang
|
b5512b45d5
clk: tegra: pll: Adjust vco_min if SDM present
|
пре 10 година |
|
Rhyland Klein
|
6929715cf6
clk: tegra: pll: Add support for PLLMB for Tegra210
|
пре 10 година |
|
Rhyland Klein
|
dd322f047d
clk: tegra: pll: Add specialized logic for Tegra210
|
пре 10 година |
|
Bill Huang
|
fde207eb15
clk: tegra: pll: Add code to handle if resets are supported by PLL
|
пре 10 година |
|
Rhyland Klein
|
407254da29
clk: tegra: pll: Add logic for out-of-table rates for T210
|
пре 10 година |
|
Rhyland Klein
|
d907f4b4a1
clk: tegra: pll: Add logic for handling SDM data
|
пре 10 година |
|
Bill Huang
|
56fd27b31f
clk: tegra: pll: Change misc_reg count from 3 to 6
|
пре 10 година |
|
Rhyland Klein
|
6583a6309e
clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header
|
пре 10 година |
|
Thierry Reding
|
385f9adf62
clk: tegra: Constify pdiv-to-hw mappings
|
пре 10 година |
|
Rhyland Klein
|
88d909bedf
clk: tegra: Modify tegra_audio_clk_init to accept more plls
|
пре 10 година |
|
Thierry Reding
|
db592c4e2b
clk: tegra: Update struct tegra_clk_pll_params kerneldoc
|
пре 10 година |
|
Rhyland Klein
|
fdc1feadc0
clk: tegra: Fix comments for structure definitions
|
пре 10 година |
 Mikko Perttunen
|
66b6f3d074
clk: tegra: Introduce ability for SoC-specific reset control callbacks
|
пре 10 година |
|
Thierry Reding
|
31b52ba42d
clk: tegra: EMC clock driver depends on EMC driver
|
пре 10 година |
 Mikko Perttunen
|
2db04f16b5
clk: tegra: Add EMC clock driver
|
пре 10 година |
|
Thierry Reding
|
63cc5a4da1
clk: tegra: Model oscillator as clock
|
пре 10 година |
|
Thierry Reding
|
8106462faa
clk: tegra: Fix typo tabel -> table
|
пре 11 година |
|
Thierry Reding
|
4f4f85fa0b
clk: tegra: Implement memory-controller clock
|
пре 11 година |
 Stephen Warren
|
2ae77527bb
clk: tegra: remove legacy reset APIs
|
пре 12 година |
|
Stephen Warren
|
6d5b988e7d
clk: tegra: implement a reset driver
|
пре 12 година |
 Peter De Schrijver
|
b29f9e9264
clk: tegra: add TEGRA_PERIPH_NO_GATE
|
пре 12 година |
