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@@ -14,6 +14,40 @@
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reg = <0x0 0x80000000 0x0 0x80000000>;
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reg = <0x0 0x80000000 0x0 0x80000000>;
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};
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};
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ ipu2_memory_region: ipu2-memory@95800000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0x0 0x95800000 0x0 0x3800000>;
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+ reusable;
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+ status = "okay";
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+ };
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+
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+ dsp1_memory_region: dsp1-memory@99000000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0x0 0x99000000 0x0 0x4000000>;
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+ reusable;
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+ status = "okay";
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+ };
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+
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+ ipu1_memory_region: ipu1-memory@9d000000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0x0 0x9d000000 0x0 0x2000000>;
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+ reusable;
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+ status = "okay";
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+ };
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+
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+ dsp2_memory_region: dsp2-memory@9f000000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0x0 0x9f000000 0x0 0x800000>;
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+ reusable;
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+ status = "okay";
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+ };
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+ };
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+
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status-leds {
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status-leds {
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compatible = "gpio-leds";
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compatible = "gpio-leds";
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cpu0-led {
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cpu0-led {
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@@ -75,3 +109,23 @@
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&pcie1_ep {
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&pcie1_ep {
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gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
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gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
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};
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};
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+
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+&ipu2 {
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+ status = "okay";
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+ memory-region = <&ipu2_memory_region>;
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+};
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+
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+&ipu1 {
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+ status = "okay";
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+ memory-region = <&ipu1_memory_region>;
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+};
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+
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+&dsp1 {
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+ status = "okay";
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+ memory-region = <&dsp1_memory_region>;
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+};
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+
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+&dsp2 {
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+ status = "okay";
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+ memory-region = <&dsp2_memory_region>;
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+};
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