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@@ -47,6 +47,24 @@ static inline bool drm_arch_can_wc_memory(void)
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return false;
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return false;
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#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
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#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3)
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return false;
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return false;
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+#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
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+ /*
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+ * The DRM driver stack is designed to work with cache coherent devices
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+ * only, but permits an optimization to be enabled in some cases, where
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+ * for some buffers, both the CPU and the GPU use uncached mappings,
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+ * removing the need for DMA snooping and allocation in the CPU caches.
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+ *
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+ * The use of uncached GPU mappings relies on the correct implementation
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+ * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU
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+ * will use cached mappings nonetheless. On x86 platforms, this does not
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+ * seem to matter, as uncached CPU mappings will snoop the caches in any
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+ * case. However, on ARM and arm64, enabling this optimization on a
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+ * platform where NoSnoop is ignored results in loss of coherency, which
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+ * breaks correct operation of the device. Since we have no way of
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+ * detecting whether NoSnoop works or not, just disable this
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+ * optimization entirely for ARM and arm64.
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+ */
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+ return false;
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#else
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#else
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return true;
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return true;
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#endif
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#endif
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