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@@ -480,6 +480,10 @@ has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE_LIST(midr_list)
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+/* Track overall mitigation state. We are only mitigated if all cores are ok */
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+static bool __hardenbp_enab = true;
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+static bool __spectrev2_safe = true;
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+
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/*
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* Generic helper for handling capabilties with multiple (match,enable) pairs
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* of call backs, sharing the same capability bit.
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@@ -522,6 +526,10 @@ static const struct midr_range spectre_v2_safe_list[] = {
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{ /* sentinel */ }
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};
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+/*
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+ * Track overall bp hardening for all heterogeneous cores in the machine.
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+ * We are only considered "safe" if all booted cores are known safe.
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+ */
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static bool __maybe_unused
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check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
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{
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@@ -543,6 +551,8 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
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if (!need_wa)
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return false;
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+ __spectrev2_safe = false;
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+
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if (!IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR)) {
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pr_warn_once("spectrev2 mitigation disabled by kernel configuration\n");
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__hardenbp_enab = false;
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@@ -552,11 +562,14 @@ check_branch_predictor(const struct arm64_cpu_capabilities *entry, int scope)
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/* forced off */
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if (__nospectre_v2) {
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pr_info_once("spectrev2 mitigation disabled by command line option\n");
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+ __hardenbp_enab = false;
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return false;
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}
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- if (need_wa < 0)
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+ if (need_wa < 0) {
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pr_warn_once("ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware\n");
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+ __hardenbp_enab = false;
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+ }
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return (need_wa > 0);
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}
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@@ -753,3 +766,15 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
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{
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return sprintf(buf, "Mitigation: __user pointer sanitization\n");
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}
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+
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+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
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+ char *buf)
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+{
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+ if (__spectrev2_safe)
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+ return sprintf(buf, "Not affected\n");
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+
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+ if (__hardenbp_enab)
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+ return sprintf(buf, "Mitigation: Branch predictor hardening\n");
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+
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+ return sprintf(buf, "Vulnerable\n");
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+}
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