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@@ -19,6 +19,13 @@
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/* mpu clocks */
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#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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+/* dsp clocks */
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+#define DRA7_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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+#define DRA7_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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+
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+/* ipu1 clocks */
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+#define DRA7_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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+
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/* ipu clocks */
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#define DRA7_IPU_CLKCTRL_OFFSET 0x40
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#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
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@@ -48,6 +55,9 @@
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#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
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#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
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+/* ipu2 clocks */
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+#define DRA7_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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+
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/* dma clocks */
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#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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@@ -103,6 +113,8 @@
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#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
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#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
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#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
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+#define DRA7_PRUSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x18)
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+#define DRA7_PRUSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x20)
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#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
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#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
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#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
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