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@@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __
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/* mux clocks */
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static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
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MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
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- MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
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- CPU_CLK_STATUS, 0, 1, "armclk"),
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+ MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
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};
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/* divider clocks */
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@@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
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PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
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};
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+/*
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+ * Clock aliases for legacy clkdev look-up.
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+ */
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+static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
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+ ALIAS(CLK_ARM_CLK, NULL, "armclk"),
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+};
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+
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/* register exynos5440 clocks */
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static void __init exynos5440_clk_init(struct device_node *np)
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{
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@@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
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ARRAY_SIZE(exynos5440_div_clks));
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samsung_clk_register_gate(ctx, exynos5440_gate_clks,
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ARRAY_SIZE(exynos5440_gate_clks));
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+ samsung_clk_register_alias(ctx, exynos5440_aliases,
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+ ARRAY_SIZE(exynos5440_aliases));
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samsung_clk_of_add_provider(np, ctx);
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