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@@ -23,6 +23,9 @@
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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#include "clk.h"
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#include "common.h"
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@@ -55,6 +58,8 @@
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#define ccm(x) (CRM_BASE + (x))
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+static struct clk_onecell_data clk_data;
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+
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static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
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static const char *per_sel_clks[] = { "ahb", "upll", };
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@@ -82,12 +87,12 @@ enum mx25_clks {
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static struct clk *clk[clk_max];
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-int __init mx25_clocks_init(void)
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+static int __init __mx25_clocks_init(unsigned long osc_rate)
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{
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int i;
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clk[dummy] = imx_clk_fixed("dummy", 0);
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- clk[osc] = imx_clk_fixed("osc", 24000000);
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+ clk[osc] = imx_clk_fixed("osc", osc_rate);
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clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
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clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
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clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
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@@ -219,6 +224,16 @@ int __init mx25_clocks_init(void)
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clk_prepare_enable(clk[emi_ahb]);
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+ clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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+ clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
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+
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+ return 0;
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+}
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+
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+int __init mx25_clocks_init(void)
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+{
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+ __mx25_clocks_init(24000000);
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+
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/* i.mx25 has the i.mx21 type uart */
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clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
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clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
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@@ -230,8 +245,6 @@ int __init mx25_clocks_init(void)
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clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
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clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
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clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
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- clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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- clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
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clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
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clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
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clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
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@@ -289,5 +302,40 @@ int __init mx25_clocks_init(void)
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clk_register_clkdev(clk[iim_ipg], "iim", NULL);
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mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
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+
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+ return 0;
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+}
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+
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+int __init mx25_clocks_init_dt(void)
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+{
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+ struct device_node *np;
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+ void __iomem *base;
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+ int irq;
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+ unsigned long osc_rate = 24000000;
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+
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+ /* retrieve the freqency of fixed clocks from device tree */
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+ for_each_compatible_node(np, NULL, "fixed-clock") {
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+ u32 rate;
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+ if (of_property_read_u32(np, "clock-frequency", &rate))
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+ continue;
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+
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+ if (of_device_is_compatible(np, "fsl,imx-osc"))
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+ osc_rate = rate;
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+ }
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+
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+ np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
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+ clk_data.clks = clk;
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+ clk_data.clk_num = ARRAY_SIZE(clk);
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+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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+
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+ __mx25_clocks_init(osc_rate);
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+
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+ np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
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+ base = of_iomap(np, 0);
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+ WARN_ON(!base);
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+ irq = irq_of_parse_and_map(np, 0);
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+
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+ mxc_timer_init(base, irq);
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+
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return 0;
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}
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