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@@ -232,12 +232,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
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struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
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struct mt9p031_platform_data *pdata = mt9p031->pdata;
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+ int ret;
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mt9p031->clk = devm_clk_get(&client->dev, NULL);
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if (IS_ERR(mt9p031->clk))
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return PTR_ERR(mt9p031->clk);
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- clk_set_rate(mt9p031->clk, pdata->ext_freq);
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+ ret = clk_set_rate(mt9p031->clk, pdata->ext_freq);
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+ if (ret < 0)
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+ return ret;
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/* If the external clock frequency is out of bounds for the PLL use the
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* pixel clock divider only and disable the PLL.
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@@ -318,8 +321,14 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031)
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return ret;
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/* Enable clock */
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- if (mt9p031->clk)
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- clk_prepare_enable(mt9p031->clk);
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+ if (mt9p031->clk) {
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+ ret = clk_prepare_enable(mt9p031->clk);
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+ if (ret) {
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+ regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators),
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+ mt9p031->regulators);
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+ return ret;
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+ }
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+ }
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/* Now RESET_BAR must be high */
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if (gpio_is_valid(mt9p031->reset)) {
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