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@@ -666,9 +666,9 @@
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#clock-cells = <0>;
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clock-output-names = "sd2";
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};
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- sd3_clk: sd3_clk@e615007c {
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+ sd3_clk: sd3_clk@e615026c {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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- reg = <0 0xe615007c 0 4>;
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+ reg = <0 0xe615026c 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd3";
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