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@@ -29,32 +29,38 @@
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#size-cells = <2>;
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ranges;
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- mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@9b000000 {
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+ secure_ddr: secure_ddr@9e800000 {
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+ reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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+ alignment = <0x1000>;
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+ no-map;
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+ };
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+
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+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
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compatible = "shared-dma-pool";
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- reg = <0 0x9b000000 0 0x100000>;
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+ reg = <0 0xa0000000 0 0x100000>;
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no-map;
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};
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- mcu_r5fss0_core1_memory_region: r5f-memory@9b100000 {
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+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
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compatible = "shared-dma-pool";
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- reg = <0 0x9b100000 0 0xf00000>;
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+ reg = <0 0xa0100000 0 0xf00000>;
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no-map;
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};
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- mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c000000 {
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+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
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compatible = "shared-dma-pool";
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- reg = <0 0x9c000000 0 0x100000>;
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+ reg = <0 0xa1000000 0 0x100000>;
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no-map;
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};
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- mcu_r5fss0_core0_memory_region: r5f-memory@9c100000 {
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+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
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compatible = "shared-dma-pool";
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- reg = <0 0x9c100000 0 0x700000>;
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+ reg = <0 0xa1100000 0 0xf00000>;
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no-map;
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};
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- secure_ddr: secure_ddr@9e800000 {
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- reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
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+ rtos_ipc_memory_region: ipc-memories@a2000000 {
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+ reg = <0x00 0xa2000000 0x00 0x00100000>;
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alignment = <0x1000>;
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no-map;
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};
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