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@@ -473,8 +473,10 @@ static void pxad_free_phy(struct pxad_chan *chan)
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return;
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/* clear the channel mapping in DRCMR */
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- reg = pxad_drcmr(chan->drcmr);
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- writel_relaxed(0, chan->phy->base + reg);
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+ if (chan->drcmr <= DRCMR_CHLNUM) {
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+ reg = pxad_drcmr(chan->drcmr);
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+ writel_relaxed(0, chan->phy->base + reg);
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+ }
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spin_lock_irqsave(&pdev->phy_lock, flags);
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for (i = 0; i < 32; i++)
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@@ -516,8 +518,10 @@ static void phy_enable(struct pxad_phy *phy, bool misaligned)
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"%s(); phy=%p(%d) misaligned=%d\n", __func__,
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phy, phy->idx, misaligned);
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- reg = pxad_drcmr(phy->vchan->drcmr);
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- writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
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+ if (phy->vchan->drcmr <= DRCMR_CHLNUM) {
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+ reg = pxad_drcmr(phy->vchan->drcmr);
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+ writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
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+ }
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dalgn = phy_readl_relaxed(phy, DALGN);
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if (misaligned)
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@@ -911,14 +915,18 @@ static void pxad_get_config(struct pxad_chan *chan,
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width = chan->cfg.src_addr_width;
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dev_addr = chan->cfg.src_addr;
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*dev_src = dev_addr;
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- *dcmd |= PXA_DCMD_INCTRGADDR | PXA_DCMD_FLOWSRC;
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+ *dcmd |= PXA_DCMD_INCTRGADDR;
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+ if (chan->drcmr <= DRCMR_CHLNUM)
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+ *dcmd |= PXA_DCMD_FLOWSRC;
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}
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if (dir == DMA_MEM_TO_DEV) {
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maxburst = chan->cfg.dst_maxburst;
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width = chan->cfg.dst_addr_width;
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dev_addr = chan->cfg.dst_addr;
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*dev_dst = dev_addr;
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- *dcmd |= PXA_DCMD_INCSRCADDR | PXA_DCMD_FLOWTRG;
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+ *dcmd |= PXA_DCMD_INCSRCADDR;
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+ if (chan->drcmr <= DRCMR_CHLNUM)
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+ *dcmd |= PXA_DCMD_FLOWTRG;
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}
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if (dir == DMA_MEM_TO_MEM)
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*dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR |
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