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@@ -157,7 +157,7 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
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* HOLD register should be bypassed in case there is no phase shift
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* applied on CMD/DATA that is sent to the card.
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*/
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- if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel))
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+ if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->cur_slot)
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set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags);
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}
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