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@@ -1328,17 +1328,16 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
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hwmgr->dyn_state.vce_clock_voltage_dependency_table;
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/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
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- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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- PHM_PlatformCaps_StablePState)
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- || hwmgr->en_umd_pstate) {
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+ if (PP_CAP(PHM_PlatformCaps_StablePState) ||
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+ hwmgr->en_umd_pstate) {
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cz_hwmgr->vce_dpm.hard_min_clk =
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ptable->entries[ptable->count - 1].ecclk;
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smum_send_msg_to_smc_with_parameter(hwmgr,
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- PPSMC_MSG_SetEclkHardMin,
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- cz_get_eclk_level(hwmgr,
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- cz_hwmgr->vce_dpm.hard_min_clk,
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- PPSMC_MSG_SetEclkHardMin));
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+ PPSMC_MSG_SetEclkHardMin,
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+ cz_get_eclk_level(hwmgr,
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+ cz_hwmgr->vce_dpm.hard_min_clk,
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+ PPSMC_MSG_SetEclkHardMin));
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} else {
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/*Program HardMin based on the vce_arbiter.ecclk */
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if (hwmgr->vce_arbiter.ecclk == 0) {
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@@ -1351,10 +1350,10 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
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} else {
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cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
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smum_send_msg_to_smc_with_parameter(hwmgr,
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- PPSMC_MSG_SetEclkHardMin,
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- cz_get_eclk_level(hwmgr,
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- cz_hwmgr->vce_dpm.hard_min_clk,
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- PPSMC_MSG_SetEclkHardMin));
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+ PPSMC_MSG_SetEclkHardMin,
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+ cz_get_eclk_level(hwmgr,
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+ cz_hwmgr->vce_dpm.hard_min_clk,
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+ PPSMC_MSG_SetEclkHardMin));
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}
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}
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return 0;
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