arm64: dts: ti: k3-j721e-main: Add C66x DSP nodes

The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.

NOTE:
The power-domains property is currently commented out until the local
resets integration is sorted out (not represented in SoC data). Otherwise,
the genpd integration tries to enable the DSP (release from reset) even
before the driver is probed.

Signed-off-by: Suman Anna <s-anna@ti.com>

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

@@ -1396,4 +1396,32 @@
 			mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
 		};
 	};
+
+	c66_0: dsp@4d80800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x80800000 0x00 0x00048000>,
+		      <0x4d 0x80e00000 0x00 0x00008000>,
+		      <0x4d 0x80f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <142>;
+		ti,sci-proc-ids = <0x03 0xFF>;
+		resets = <&k3_reset 142 1>;
+		/*power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;*/
+		mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
+	};
+
+	c66_1: dsp@4d81800000 {
+		compatible = "ti,j721e-c66-dsp";
+		reg = <0x4d 0x81800000 0x00 0x00048000>,
+		      <0x4d 0x81e00000 0x00 0x00008000>,
+		      <0x4d 0x81f00000 0x00 0x00008000>;
+		reg-names = "l2sram", "l1pram", "l1dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <143>;
+		ti,sci-proc-ids = <0x04 0xFF>;
+		resets = <&k3_reset 143 1>;
+		/*power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;*/
+		mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
+	};
 };