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@@ -72,7 +72,7 @@
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#define SCLK_MACREF_OUT 106
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#define SCLK_VOP0_PWM 107
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#define SCLK_VOP1_PWM 108
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-#define SCLK_RGA 109
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+#define SCLK_RGA_CORE 109
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#define SCLK_ISP0 110
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#define SCLK_ISP1 111
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#define SCLK_HDMI_CEC 112
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@@ -129,6 +129,8 @@
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#define SCLK_DPHY_TX0_CFG 163
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#define SCLK_DPHY_TX1RX1_CFG 164
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#define SCLK_DPHY_RX0_CFG 165
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+#define SCLK_RMII_SRC 166
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+#define SCLK_PCIEPHY_REF100M 167
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#define DCLK_VOP0 180
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#define DCLK_VOP1 181
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@@ -671,6 +673,7 @@
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#define SRST_P_EDP_CTRL 285
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/* cru_softrst_con18 */
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+#define SRST_A_GPU 288
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#define SRST_A_GPU_NOC 289
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#define SRST_A_GPU_GRF 290
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#define SRST_PVTM_GPU 291
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Heiko Stuebner